JPH0499378A - Semiconductor device - Google Patents

Abstract

PURPOSE:To eliminate an irregularity in a potential on a gate array region by arranging a second power source system pads partly on a power source system bus in the array region, supplying power from the pads of a periphery and supplying power also from the second pads. CONSTITUTION:On a gate array region 7 is provided with a power source bus 5 connected to power source pads 3 to supply power to a gate array region 7 and a GND bus 6 connected to a GND pad 4 to GND-connect the region 7. Further, second power source system pads, i.e., second power source pads 8 and second GND pad 9 are formed partly at the bus 5 and the bus 6 arranged in the region 7. Power is supplied by using the pads 3 and the pad 4 arranged on a periphery, and power is supplied to gate elements 10 of the region 7 through the bus 5 and the bus 6. Simultaneously, power is also supplied to the pads 8 and the pad 9 provided on the region 7.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a semiconductor device having a gate array structure.

[Conventional technology]

In a conventional gate array semiconductor device, as shown in the plan view in FIG. 4 are installed. Also,
A gate array region 7 in which a plurality of gate elements are regularly arranged is formed in the center, and this gate array region 7
, power system lotuses such as a power supply bus 5 and a GND lotus 6 connected to the power supply pad 3 and the GND pad 4 are formed.

In such a gate array semiconductor device, a power supply pad 3 and a GND pad 4 arranged outside the gate array region 7 are
Supply power from outside between these power pads 3 and GN.
A predetermined potential can be applied to the gate in the gate array region 7 via the power supply bus 5 and the GND bus 6 connected to the D pad 4 to operate the gate.

[Problems to be Solved by the Invention] This conventional gate array semiconductor device supplies power to the power supply pad 3 and the GND pad 4 arranged outside the gate region 7, so it is difficult to arrange these pads. Therefore, the length required to arrange all the pads increases, resulting in an increase in the size of the gate array semiconductor device. As the gate array semiconductor device becomes larger as described above, the lengths of the power supply bus 5 and the GND bus 6 become longer, and a potential drop is likely to occur due to the resistance of these buses. For this reason, power supply pad 3 and GND pad 4
The power supply potential supplied between the two gate arrays is gradually lowered along the helical line in the central portion of the gate array semiconductor device, that is, the gate region 7, and the potential within the gate array region 7 becomes non-uniform, thereby obtaining the required characteristics of the semiconductor device. The problem is that it becomes impossible to do so.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device with a gate array structure that eliminates potential non-uniformity and ensures desired characteristics.

(Means for Solving the Problems) In the semiconductor device of the present invention, a second power system pad is provided in a part of the power system lot that connects the power system pad and the gate array region.

[Effect]

According to the present invention, by supplying power from the second power system pad in addition to power supply from the power system pad in the peripheral area, the potential in the gate array area caused by the potential drop of the power system bus can be reduced. Eliminate non-uniformity.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a diagram of a gate array semiconductor device according to an embodiment of the present invention. 2 is a gate array semiconductor device, 2 is an input/output pad used for signal input/output, and 3 and 4 are power supply pads for supplying power from the outside to the gate array semiconductor device, that is, a power supply pad and a GND pad. . A gate array region 7 is formed in the center surrounded by these pads, and a plurality of gate elements 10 (see FIG. 2) are arranged in an array. The gate array region 7 includes a power bus 5 connected to the power pad 3 to supply power to the gate array region 7, and a power bus 5 connected to the power pad 3 to supply power to the gate array region 7;
A GND bus 6 is provided which is connected to the D pad 4 and connects the gate array region 7 to GND.

Further, second power system pads, that is, a second power supply pad 8 and a second GND pad 9, are formed on each part of the power supply bus 5 and the GND bus 6 arranged in the gate array region 7, respectively. .

FIG. 2 is an enlarged view of part A in FIG. 1, in which a power supply bus 5. G
The ND buses 6 are formed so as to overlap each other, and each part of the GND bus 6 from the power supply bus 5 is configured as a second power supply pad 8 and a second GND pad 9.

According to this gate array semiconductor device, power is supplied using the power supply pad 3 and GND pad 4 arranged in the peripheral area, and is supplied to each gate element 10 in the gate array region 7 through the power supply bus 5 and the GND bus 6, respectively. Supply power. At the same time, power is also supplied to the second power pad 8 and GND pad 9 provided in the gate array region 7.

As a result, even if a potential drop due to the power supply bus 5 and the GND bus 6 is a problem, the second power supply pad 8 and the
By simultaneously supplying power from the ND pad 9, it becomes possible to equalize the potential of each gate element 10 in the gate array region 7, and it becomes possible to ensure the required characteristics of the semiconductor device.

Note that the second power supply pad 8 is a gate with a large potential drop.
? It is placed on the power supply bus 5 in the iI area 7, and the second GN
The D pad 9 is connected to the GN in the gate region 7 where the potential drop is large.
Needless to say, it is placed on the D bus 6.

〔Effect of the invention〕

As explained above, the present invention provides a second power system pad in a part of the power system bus in the gate array area, and supplies power from the power system pads in the peripheral area. By supplying power from the gate array, it is possible to eliminate potential nonuniformity in the gate array region caused by a potential drop in the power supply bus, and to ensure desired semiconductor device characteristics.

[Brief explanation of drawings]

FIG. 1 is a plan view of one embodiment of the semiconductor device of the present invention, and FIG.
The figure is an enlarged view of section A in FIG. 1, and FIG. 3 is a plan view of a conventional semiconductor device. DESCRIPTION OF SYMBOLS 1... Gate array semiconductor device, 2... Input/output pad, 3... Power supply pad, 4... GND pad, 5...
...Power bus, 6...GND bus, 7...Gate array area, 8...Second power supply pad, 9...Second GN
D Pad, 10... Gate element. Third

Claims (1)

[Claims] 1. Arrange input/output pads and power supply pads in the periphery, provide a gate array region in which gate elements are arranged in an array in the center, and connect the power supply pads and the gate array region with a power supply bus. What is claimed is: 1. A semiconductor device in which a second power supply system pad is disposed in a part of the power supply system bus in the gate array region.