JPH0498375A - Pattern recognition device - Google Patents

Abstract

PURPOSE:To execute the recognition operation of a picture including variable density by changing a segment address in such a way that a value obtained by means of adding the squares of the difference between an optimum lightness correction coefficient, picture data and a standard pattern picture element as to whole picture elements becomes the minimum. CONSTITUTION:An input picture processing means supplies data required for an optimum lightness correction coefficient generation means 3 and an evaluation value processing means 4 and an evaluation value processing means 4 is inputted to a position calculation means 5. The optimum lightness correction coefficient used when the evaluation value is obtained by adding the squares of the difference between the values obtained by multiplying the optimum lightness correction coefficient for respective picture element data X(i) of a recognized pattern and picture element data Y(i) of the corresponding standard pattern as to the whole obtained picture elements is set to be the same as a value by making into the minimum the evaluation value obtained by obtaining the square of the difference with picture element data Y(i) of the standard pattern corresponding to the value obtained by multiplying the prescribed lightness correction coefficient K for respective picture elements data X(i) of the recognized pattern and adding them as to the whole picture elements. Thus, the range of an object which can be recognized can be enlarged.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a pattern recognition device that detects a target object from an image obtained using an image sensor and performs pattern recognition such as positioning.

Conventional technology Conventionally, this type of pattern recognition device performs recognition by applying pattern matching to a binarized image obtained by appropriately binarizing an image from an image sensor such as a television camera. known as a device.

FIG. 5 is a block diagram showing the configuration of a conventional recognition device.

In FIG. 5, a television camera 31, which is an image sensor, obtains an image signal of an object to be recognized. The television camera 31 supplies the image signal to the binarization circuit 32. The binarization circuit 32 converts the image signal into binary data of "0" and "1" at an appropriate binarization level. The binarization circuit 32 supplies a binary input image to a binary image memory 33 and stores it for one screen. A standard pattern memory 34 separate from this binary image memory 33 stores, for example, a 16×16 pattern from the binary input image.
The data cut out for the pixel area is stored as a standard pattern.

In addition, the cutout address generation circuit 35 is connected to the binary image memory 3
For the input image No. 3, cutout addresses for determining areas to be compared with the standard pattern are sequentially generated. This cutout address generation circuit 35 supplies the cutout address to an adder 37. The sweep address generation circuit 36 supplies the sweep address to the adder 37. The adder 37 adds the two addresses, generates a read address for reading out an area of, for example, 16×16 pixels, and provides this address to the binary image memory 33. The sweep address generation circuit 36 also generates a sweep address for an area of, for example, 16×16 pixels in the standard pattern memory 34, and supplies this address to the standard pattern memory 34. The binary image memory 33 is
The image data is supplied to a comparison circuit 38. The standard pattern image from the standard pattern memory 34 is input to the comparison circuit 38, and the comparison circuit 38 compares the two images and returns "0" when the two images have the same value, and "0" when they have different values. Outputs 1”. This comparison circuit 38 inputs the comparison result to an accumulator 39, and this accumulator 39 is reset before the sweep address generation circuit 36 starts sweeping, and the input image output from the comparison circuit 38 and the standard pattern image are The comparison results are accumulated during the sweep of the 16×16 pixel area and held as evaluation values. The minimum value holding circuit 40 resets the minimum value of this circuit before the cutting address generation circuit 35 starts cutting out the input image, and the minimum value of the accumulator 39 is reset every time the sweep of the 16×16 pixel area is completed. Compare the evaluation value held by the output with the minimum value of this circuit, and if the evaluation value is smaller, replace the minimum value with the evaluation value,
It outputs a replacement pulse indicating that it has been replaced. The output of the minimum value holding circuit 40 is input to the cutout address holding register 41, which receives the cutout address generated by the cutout address generation circuit 35, and the minimum value holding circuit 40 receives the replacement pulse. Memorize the extraction address when outputting.

The operation of such a device will be explained.

First, from a binary input image obtained by operating the television camera 31, the binarization circuit 32, and the binary image memory 33, a portion of the shape to be recognized that captures the feature is stored as a standard pattern in the standard pattern memory 34. Let me remember it.

The following recognition operation consists of a first large loop operation that finds the minimum evaluation value while changing the cutout address of the binary image memory 33, and a first large loop operation that searches for the minimum value of the evaluation while changing the cutout address of the binary image memory 33, and a sweep operation of the binary image memory successive address and standard pattern memory read address. It is divided into a second small loop operation that calculates the evaluation value. This second loop operation is included within the first loop.

First, prior to the first large loop operation, the extraction address generation circuit 35 sends a minimum value reset to the minimum value holding circuit 40 to set the minimum value to a large value.

Next, a first large loop operation is entered, and the cutout address output from the cutout address generation circuit 35 is r9J in the X direction.
The minimum evaluation value is determined while sweeping the rectangular area of "9" in the Y direction.

An accumulator reset signal is output from the sweep address generation circuit 36 to one of the extracted addresses in the first large loop, and the evaluation value of the accumulator 39 is set to "0".

Next, a second small loop operation is entered, and the sweep address generation circuit 36 generates a sweep address to sweep a 16×16 area. This sweep address becomes the standard pattern memory successive address, and is output one after another so as to sweep the 16×16 area of the standard pattern, starting from the address indicating the pixel at the upper left corner of the standard pattern. The sweep address is added to the cutout address outputted from the cutout address generation circuit 35 in the adder 37 and becomes the readout address of the binary image memory 33. The successive addresses of the binary image memory 33 are output one after another starting from the cutting address of the binary input image and sweeping a 16×16 area with this address as the upper left corner. The read address of the binary image memory 33 is
The address for reading the input image stored in the binary image memory 33 is determined. Binary image method 3
The input image read from 3 is sent to a comparison circuit 38. On the other hand, the standard pattern read address is sent to the standard pattern memory 34, and the subsequent address of the standard pattern image stored in the standard pattern memory 34 is determined.

The standard pattern image read out from the standard pattern memory 34 is sent to the comparator circuit 38 and is then read out from the binary image memory 33.
The input image sent from the standard pattern image is compared with the standard pattern image, and the result is sent to the accumulator 39. The accumulator 39 adds the output of the comparison circuit 38 to the accumulator 39 for each pixel according to the sweep of the 16×16 area of the binary image memory 33 and the standard pattern memory 34 according to the instruction from the sweep address generation circuit 36. do. When the sweep of the 16×16 area of the binary image memory 33 and the standard pattern memory 34 is completed, an evaluation value has been obtained in the accumulator 39, and this value is sent to the minimum value holding circuit 40. The minimum value holding circuit 40 compares the evaluation value and the minimum value using the evaluation strobe signal output from the sweep address generation circuit 36, and when the evaluation value is smaller, replaces the minimum value with the evaluation value and cuts out a replacement pulse. It is output to the address holding circuit 41. The cutout address holding circuit 41 holds the cutout address output from the cutout address generation circuit 35 according to the replacement pulse, and stores the cutout address that has obtained the minimum evaluation value. When the second small loop operation for sweeping the 16×16 area of the binary image memory 33 and the standard pattern memory 34 is completed, and the evaluation value and the minimum value are compared using the evaluation strobe signal, the extraction address generation circuit 35 outputs the Continue execution of the first large loop with the extracted address as the next value. When the extraction address output by the extraction address generation circuit 35 sweeps a rectangular area where X and Y are respectively "9", the first large loop operation is completed, and the minimum evaluation value and the values of X and Y are is required, and the desired recognition operation is completed.

Problems to be Solved by the Invention However, the conventional recognition device described above has the problem that it is necessary to find an appropriate binarization level at the time of recognition, and that it is difficult to recognize multiple gradations including shading.

The present invention solves the above-mentioned conventional problems,
The object of the present invention is to provide an excellent pattern recognition device that can expand the range of objects that can be recognized.

Means for Solving the Problems In order to achieve the above object, the present invention provides input image processing means for digitizing an image signal from an image sensor to obtain a digital image and storing the digital image in a frame memory;
a standard pattern memory for cutting out a part of the digital image of the frame memory of the input image processing means and storing it as a standard pattern; and storing an average value of the entire standard pattern, and cutting out a recognized pattern from the digital image according to the cutting address. , optimal brightness correction coefficient generation means for obtaining an optimal brightness correction coefficient obtained by dividing the average value of the entire standard pattern by the average value of the entire recognized pattern, and the optimal brightness correction coefficient for each pixel data of the recognized pattern at the time of recognition. The value multiplied by the optimal brightness correction coefficient from the coefficient acquisition means,
an evaluation value processing means for calculating a difference between pixel data of the recognized pattern and a value of pixel data of a corresponding standard pattern, and calculating the absolute value or square of this difference to obtain an evaluation value for all pixels; and the evaluation value processing means. This patent is characterized in that it includes a position calculation means for determining a cutout position of an input image at which the evaluation value from the means is minimized.

Although the present invention has the above-described configuration, the following points have been found. In other words, the square of the difference between the value obtained by multiplying each pixel data X'(i) of the recognized pattern by the optimum brightness correction coefficient and the corresponding pixel data Y(i) of the standard pattern is calculated and added for all pixels. The optimal brightness correction coefficient (-the quotient obtained by dividing the average value Y of the entire standard pattern by the average value X of the entire recognized pattern) used when obtaining the evaluation value (the right side of box 0 below) is the Evaluation value obtained by calculating the square of the difference between the pixel data Y (1) of the standard pattern corresponding to the value multiplied by a constant brightness correction coefficient K for each pixel de-X (i), and adding it for all pixels It is the same as the one that minimizes (the left side of bundle 02 below).

If we consider Σ on the left side as a function of X and Y and set it as F(x, y), then: Σ(K
(i)) Partially differentiated with respect to x and y, d (F(x, y))/dx = 2K N...
・・■ d (F(x, y))/dy = 2N
...■F(x,y) is minimum when ■=0. ■〉0. ■-〇, ■〉0. Therefore, since ■: 0, here, K=Y/X.

The present invention configured in this way has the following effects. In other words, the optimal brightness correction coefficient multiplied by the recognition pattern,
By determining the minimum evaluation value and the cutout position of the input image, it is possible to determine the position in the input image that is most similar in shape to the standard pattern containing grayscale information collected in advance.

Example Embodiments of the present invention will be described below based on the drawings.

FIG. 1 is a block diagram showing the configuration of a pattern recognition device according to an embodiment of the present invention.

In FIG. 1, the input image processing means 1 converts an image signal from a television camera 11, which is an image sensor, into a digital image using an A/D converter 12, and stores the digital image in a frame memory 13. A part of the digital image in the frame memory 13 of the input image processing means 1 is cut out to form a standard pattern and stored in the standard pattern memory 2.

The input image processing means 1 is capable of supplying necessary data to the optimum brightness correction coefficient generation means 3 and the evaluation value processing means 4.

The optimum brightness correction coefficient generation means 3 stores the average value of the entire standard pattern in the standard pattern average value holding circuit 19, and also stores the average value of the entire standard pattern in the standard pattern average value holding circuit 19. The pattern to be recognized is cut out from the digital image in the frame memory 13 using the cutout addresses output from the sweep address generation circuit 16 and the adder 17, the average value of the entire pattern to be recognized is calculated by the average value calculation circuit 18, and the average value of the entire pattern to be recognized is calculated by the divider 20. The optimum brightness correction coefficient obtained by dividing the average value of the entire standard pattern by the average value of the entire recognized pattern can be stored in the optimum brightness correction coefficient holding circuit 21.

At the time of recognition, the evaluation value processing means 4 multiplies each pixel data of the recognized pattern read out according to the extraction address outputted from the adder 17 in the multiplier 22 from the optimum brightness correction coefficient holding circuit 21. Multiply by the optimum brightness correction coefficient, read out the standard pattern corresponding to the pixel data of the recognized pattern from the standard pattern memory 2, multiply by the correction coefficient, and subtract the difference between the value and the value of the standard pattern.
The difference is squared by a squarer 24, and an accumulator 25 obtains evaluation values for all pixels.

The evaluation value from the evaluation value processing means 4 is processed by the position calculation means 5.
is input. This position calculation means 5 replaces the minimum value with the evaluation value when the evaluation value from the accumulator 25 of the evaluation value processing means 4 is smaller than the minimum value held, and outputs a pulse indicating the replacement. It consists of a holding circuit 26 and a cutout address holding circuit 27 that stores the cutout address of the cutout address generation circuit 15 using a pulse from the minimum value holding circuit 26.

Further, to explain the above configuration in detail, the television camera 11, which is an image sensor, can obtain an image signal of a target object to perform a recognition operation. The television camera 11
The image signal is input to the A/D converter 12. The A/D converter 12 converts the image portion signal into a digital image and provides it to the frame memory 13. Frame memory 1
3 stores the input digital image for one screen.

In this embodiment, the binary standard pattern memory 2 can cut out a 16×16 pixel area from the input digital image and store it in advance as a standard pattern.

The cutout address generation circuit 15 is connected to the frame memory memory 1
In this embodiment, for the input image No. 3, the cutout addresses for determining the area to be compared with the standard turn are sequentially generated 9×9 times.

The sweep address generation circuit 16 can generate a sweep address for sweeping a 16×16 pixel area in the frame memory 13 and the standard pattern memory 2, and this sweep address is sent to the standard pattern memory 2 as a standard pattern memory successive address. . The cutout address generation circuit 15 and the sweep address generation circuit 16 are connected to an adder 17, and the adder 17 adds the cutout address and the sweep address and sends the sum to the frame memory 13 as a frame memory read address. do.

The average value calculation circuit 18 takes in data of a 16×16 pixel recognition area from the frame memory 13 starting from the frame memory read address output by the adder 17 in the frame memory 13, and averages the data. The standard pattern average value holding circuit 19 averages the data in the binary standard pattern memory 2 and stores the value in advance. The outputs of the average value calculation circuit 18 and the standard pattern average value holding circuit 19 are connected to the input terminal of the divider 20.
outputs the quotient obtained by dividing the standard pattern average value outputted from the standard pattern average value holding circuit 19 by the average value of the recognition area outputted from the average value calculation circuit 18 as the optimum brightness correction coefficient. The output of the divider 20 is connected to the optimum brightness correction coefficient holding circuit 21.
holds the optimum brightness correction coefficient. This optimum brightness correction coefficient holding circuit 21 is connected to a multiplier 22 that takes in data from the frame memory 13. The multiplication unit 22 is connected to the adder 1 in the frame memory 13 to the frame memory 13.
The pixel data to be recognized pointed to by the frame memory successive address outputted by 7 is multiplied by the optimum brightness correction coefficient held in the optimum brightness correction coefficient holding circuit 21, and is output as optimized pixel data to be recognized.

The output of the multiplier 22 is connected to a subtracter 23, and the subtracter 23 converts the pixel data to be recognized from the multiplier 22 into the standard pattern memory continuous address output by the sweep address generation circuit 16. Subtract the pixel data pointed to. The output from the subtracter 23 is connected to a squarer 24, which is a circuit for obtaining the square of the difference between the pixel data to be recognized from the subtracter 23 and the standard pattern data. This squarer 24 is connected to an accumulator 25.
5, the output of the squarer 24 is accumulated during the sweep of the 16×16 pixel area and held as an evaluation value. The output of this accumulator 25 is given to a minimum value holding circuit 26. The minimum value holding circuit 26 is the cutout address generation circuit 15
The minimum value held by this circuit is reset before starting cutting out the input image, and each time the sweep of the 16 x 16 pixel area is completed, the evaluation value held by the output of the accumulator 24 and the value held by this circuit are reset. When the evaluation value is smaller than the minimum value, the smaller value can be replaced with the evaluation value, and a replacement pulse can be output to indicate that the evaluation value has been replaced. The output of this minimum value holding circuit 26 is the cutout address holding circuit 27.
It is designed to be given to This cutout address holding circuit 27 is configured to store the cutout address at that time when the minimum value holding circuit 26 outputs a replacement pulse.

Next, the operation of the above embodiment will be explained.

FIG. 2 is a timing chart explaining the operation of the above embodiment. In FIG. 2, the horizontal axis shows the minimum value reset signal output from the extraction address generation circuit 15, the extraction address, the accumulator recent signal output from the sweep address generation circuit 16, the evaluation strobe signal, and the standard pattern memory successive address. , the frame memory read address output from the adder 17, and the timing of the optimum brightness correction coefficient held by the optimum brightness correction coefficient holding circuit 21, and time is shown on the horizontal axis.

FIG. 3 is a diagram for explaining the address of an input image of a frame memory consisting of 24 pixels in both the X direction and the Y direction.

Here, at the timing when the cutout address in FIG. 2 is "1", the frame memory address of x=rlJY=rlJ indicated by the address "1" in FIG. 3 is output, and the cutout address "2" in FIG. At the timing of
= r2J , frame memory address of Y = "1", ......, at the timing of cutout address "9" in Figure 2, X = r9J indicated by address "9" in Figure 3
, Y= rlJ frame memory address as the second
At the timing of the cutout address "25" in the figure, the frame memory addresses of x=rlJ, Y=r2J indicated by the address "25" in FIG. 3 are sequentially output as follows. . In this way, while sequentially increasing the extraction address, the rectangular area of "9" in the X direction and "9" in the Y direction is swept, and finally, when the address of the frame memory in FIG. 2 is r201J, the 3rd Address r201 in the diagram
The frame memory address of X=r9J and Y-r9J indicated by J is output. Furthermore, this cutout address (X-
r9J, r201j in Y-r9J) is determined, this extraction address (r201J) is set as the upper left pixel,
Address "201" ~r216J, r225J~
r240Jr249J~r264J, ・・・・・・
A 16×16 pixel area consisting of r561J to “576” is the subject of evaluation.

FIG. 4 is a diagram for explaining the address of the standard pattern in the standard pattern memory, which is composed of 16 pixels in both the X direction and the Y direction.

The operation of the above embodiment will be explained below using FIGS. 1, 2, 3, and 4.

An image obtained from a television camera 11, which is an image sensor, is digitized by an A/D converter 12 and stored in a frame memory 13. Frame memory 1 like this
A portion of the shape to be recognized that captures the feature is obtained from the input image stored in step 3 as a standard pattern, and is set in the standard pattern memory 2 as the standard pattern.

Further, the average value of the standard pattern data over the entire area is stored in the standard turn average value holding circuit 19.

In the next (7) V, m operation, find the minimum evaluation value while changing the extraction address of the frame memory 13.
16X while sweeping the frame memory read address in the frame memory 13 with the first large loop operation of times
A second small loop operation that averages the data of the 16 pixel recognition area, and while sweeping the frame memory successive address and standard pattern memory successive address,
This is divided into a third small loop operation that calculates the cumulative total of evaluation values for six pixels. The second and third loop operations are included in the first loop operation.

First, prior to the first large loop operation, the cutout address generation circuit 15 sends a minimum value reset signal to the minimum value holding circuit 26 (time t) to set the minimum value to an appropriately large value. , enters the first large loop operation (time t).

In the first large loop operation, the cutout address generation circuit 1
As shown in Figures 2 and 3, the output address of 5 is changed by sweeping the rectangular area of ``9'' in the X direction and ``9'' in the Y direction, while finding the minimum evaluation value. demand.

Next, a second small loop operation is entered (time 1), and the sweep address generation circuit 16 generates a sweep address to sweep a 16×16 area. The sweep address is added to the cutout address outputted from the cutout address generation circuit 15 in the adder 17 and becomes a frame memory read address. The frame memory successive addresses start from the cutout address (rlJ) of the input image and are 16x16 with this address (rlJ) as the upper left corner.
Set the address from "1" to "16J" to sweep the area of
, r25J~r40J, r49J~"64"...
... Output one after another like r361J to r3V6J. This frame memory read address is sent to the frame memory 13 and determines the subsequent address of the input image stored in the frame memory 13. Frame memory 1
The pixel data to be recognized read out in this way from 3 is input one after another to the average calculation circuit 18, and the average value calculation is performed. When the second loop ends (time 12), the average value calculation circuit 18 obtains the average value of the entire recognition area.

The multiplier 20 divides the standard pattern average value from the standard pattern average value holding circuit 19 by the average value of the recognized area from the average value calculation circuit 18, and calculates the quotient or the optimum brightness correction coefficient as the optimum brightness correction coefficient holding circuit. It is held at 21.

Next, before entering the third small loop operation, as shown in FIG.
3).

Then, when entering the third small loop operation (time 14)
, the sweep address generation circuit 16 outputs sweep addresses one after another so as to sweep a 16×16 area. The sweep address is generated by the cutout address generation circuit 15 in the adder 17.
It is added to the cutout address output from , and becomes the frame memory successive address. The frame memory successive addresses are
First, starting from the cutout address of the input image, sweep a 16x16 area with this address as the upper left corner, "1" ~ r16J, r25J ~ r40J, r
49J~r64J, ・・・・・・・・・7 ``361
”~r376J are output one after another. Such a frame memory successive address is sent to the frame memory 13 and determines the readout address of the input image stored in the frame memory 13. The pixel data to be recognized read out from the frame memory 13 as described above is multiplied by the optimum brightness correction coefficient sent from the optimum brightness correction coefficient holding circuit 21 in the multiplier 22 to obtain an optimized image. It is sent to the subtracter 23 as recognized pixel data.

On the other hand, the standard pattern read address is sent to the standard pattern memory 2, and the read address of the standard pattern image stored in the standard pattern memory 2 is determined. The standard pattern image data read out from the standard pattern memory 2 as described above is sent to the subtracter 23, where the corresponding standard pattern pixel data is subtracted from the optimized pixel data to be recognized from the multiplier 22, and the result is squared. It is sent to the container 24. squarer 2
4, the square of the difference between the corresponding standard pattern pixel data is calculated from the pixel data to be recognized, and the calculation result is given to the accumulator 25. The accumulator 25 sweeps the 16×16 area of the frame memory 13 and the standard turn memory 2 according to the instructions from the sweep address generation circuit 16.
An accumulator 25 accumulates the square of the difference image for each -pixel. 16x of frame memory 13 and standard pattern memory 2
When the sweep of the 16 areas is completed, that is, the third small loop is completed (time t5), an evaluation value has been obtained in the accumulator 25, and this value is sent to the minimum value holding circuit 26.

The minimum value holding circuit 26 compares the evaluation value and the minimum value using the evaluation strobe signal output from the sweep address generation circuit 16 at time t6 in FIG. 2, and when the evaluation value is smaller, replaces it with the minimum value. A replacement pulse is output to the cutout address holding circuit 27. The cutout address holding circuit 27 holds the cutout address output from the cutout address generation circuit 15 according to the replacement pulse, and stores the cutout address with the minimum evaluation value. On the other hand, the minimum value holding circuit 26 compares the evaluation value and the minimum value using the evaluation strobe signal output at time t6 in FIG. 2, and when the evaluation value is greater than or equal to the minimum value, the minimum value is also replaced. There is no output from Nokurusu either.

When this comparison is completed, the extraction address generation circuit 15
Set the extraction addresses to the following values r2J and r3J.

Continue executing the first large loop while changing "4", . . . , r201J.

The cutout address output by the cutout address generation circuit 15 is
, Y each sweeps the rectangular area of "9", and the first large loop operation is completed. At time 18), the minimum evaluation value within the rectangular area and the address of X and Y that obtained this value are found. The target recognition operation is completed.

In this way, according to the above embodiment, the square of the difference between the standard pattern pixel corresponding to the product of the quotient (optimum brightness correction coefficient) obtained by dividing the average value of the entire standard pattern by the average value of the entire recognition pattern and the input pixel is calculated. By changing the cutout address within a predetermined range so that the value added for all pixels is the minimum, the value obtained by adding the pixel of the recognition pattern for all the fixed made pixels is the minimum. Since the same recognition result can be obtained by changing the output address and brightness correction coefficient within a predetermined range, it is possible to recognize images including light and shade.

Furthermore, if the squarer 24 in the above embodiment is replaced with an absolute value circuit, the standard corresponding to the product of the input pixel and the quotient of the average value of the entire standard pattern divided by the average value of the entire recognized pattern By changing the cut-out address within a predetermined range so that the absolute value of the difference between pattern pixels is minimized for all pixels, it is possible to recognize an image including light and shade. Here, the standard pattern may be obtained by using a standard pattern that has been passed through the television camera 11 and the A/D converter 12, or by passing a median filter through a recognition image that is also the recognition target image. There are also possible methods to use. In addition, the size of the standard pattern was changed to 8 while keeping the average value the same.
It is also conceivable to prepare 0% and 120%, and use the minimum value evaluation of the three standard patterns as the evaluation value.

Effects of the Invention As is clear from the above embodiments, the present invention provides pixel data obtained by multiplying the input pixel by the optimal brightness correction coefficient obtained by dividing the average value of the standard pattern by the recognized pattern. By changing the extraction address within a predetermined range so that the sum of the squares of the differences of standard pattern pixels corresponding to the pixel data for all pixels is the minimum, it is possible to recognize images including shading. can be,
Moreover, it has the advantage of being able to respond stably to changes in the sensitivity of the image sensor, changes in the brightness of the illumination, and changes in the meaning of the object. Furthermore, the present invention has the advantage that the recognition time is short because there is no binarization level and no procedure to obtain it.

[Brief explanation of drawings]

FIG. 1 is a schematic block diagram of a pattern recognition device according to an embodiment of the present invention, FIG. 2 is a timing chart shown to explain the operation of the device, and FIG. Address sweep area, with the last pixel in the same area as the viewpoint 11...TV camera, 12...
・A/D controller, router, 13... Frame memory, 14... Standard pattern memory, 15... Cutout address generation circuit, 16... Sweep address generation circuit, 17
...Adder, 18...Average value calculation circuit, 19...
Standard pattern average value holding circuit, 20...Divider, 2
DESCRIPTION OF SYMBOLS 1... Optimum brightness correction coefficient holding circuit, 22... Multiplier, 23... Subtractor, 25... Accumulator, 26...
Minimum value holding circuit, 27... cutout address holding circuit. Agent's name: Patent attorney Shige Awano

Claims (1)

[Scope of Claims] Input image processing means for digitizing an image signal from an image sensor to obtain a digital image and storing it in a frame memory; and a part of the digital image in the frame memory of the input image processing means. A standard pattern memory that stores the average value of the entire standard pattern as a cutout standard pattern, cuts out the recognized pattern from the digital image using the cutout address, and calculates the average value of the entire standard pattern as the average value of the entire recognized pattern. an optimum brightness correction coefficient generating means for obtaining an optimum brightness correction coefficient obtained by dividing by the value; and a value obtained by multiplying each pixel data of the recognized pattern by the optimum brightness correction coefficient from the optimum brightness correction coefficient obtaining means during recognition; an evaluation value processing means for calculating the difference between the pixel data of the recognized pattern and the value of the pixel data of the corresponding standard pattern, and calculating the absolute value or square of this difference to obtain evaluation values for all pixels; A pattern recognition device comprising: position calculation means for determining a cutout position of an input image at which an evaluation value from the means is minimized;