JPH0495185A - Self-synchronization type transfer control circuit - Google Patents

Abstract

PURPOSE:To prevent the malfunction caused by annihilation of a pulse and an excessive transfer thereof by executing surely the control of the transfer at every one pulse. CONSTITUTION:A first storage means 111 has a reset function, stores a first pulse, and a second storage means 112 has a reset function, and it reset in response to an inhibited state of an instruction signal. A logical means 103 outputs a pulse in response to a fact that a first storage means 111, a fact that a second storage means 112 is in a reset state, and a fact that the instruc tion signal is in a permitted state, a first storage means 111 is reset by a pulse outputted from the logical means 103, and a second storage means 112 stores the pulse outputted from the logical means 103 and generates a second pulse. In such a way, a malfunction caused by annihilation of the pulse and an exces sive transfer of the pulse is prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a self-synchronous transfer control circuit, and more particularly to a self-synchronous transfer control circuit for controlling pulse transfer.

[Prior Art] In a data flow type system, data flows in synchronization with pulses, and processing is performed as the data moves. FIG. 12 is a block diagram showing the configuration of a data transmission path for transmitting data in a data flow type system.

The data transmission path consists of self-synchronized transfer control circuits 1 and D.
It includes a data holding circuit 2 consisting of a type flip-flop. The transfer control circuit 1 includes a pulse input terminal CI that receives pulses from a front stage section (not shown), a transfer permission output terminal RO1 that outputs a transfer permission signal indicating permission or prohibition of transfer to the front stage section, and a rear stage section (not shown). It has a pulse output terminal CO1 that outputs a pulse (first) and a transfer permission input terminal R1 that receives a transfer permission signal indicating permission or prohibition of transfer from a subsequent stage. When the transfer control circuit 1 receives a pulse from the front stage, it outputs a pulse to the rear stage and also sends eight pulses to the data holding circuit 2 if the transfer permission signal from the rear stage is in the permission state. Data holding circuit 2
In response to a pulse given from the transfer control circuit 1,
The data DI given from the front stage section is held, and the held data is given to the rear stage section as output data Do.

FIG. 13 is a circuit diagram showing an example of a conventional self-synchronous transfer control circuit.

The pulse input terminal CI receives a pulse from the previous stage, and the transfer permission output terminal RO outputs a transfer permission signal to the previous stage.

The pulse output terminal CO outputs a pulse to the subsequent stage, and the transfer permission input terminal R1 receives a transfer permission signal from the subsequent stage. Mask reset input terminal MR receives a mask reset signal.

NAND gates 301 and 302 constitute an RS flip-flop 111. When a negative pulse is applied to node S, Rs flip-flop 111 is set.

As a result, the RS flip-flop 111 stores a negative pulse and outputs "1" to the node Q. Furthermore, when a negative pulse is applied to node i, the RS flip-flop 111 is reset. As a result, the RS flip-flop 111 outputs "0" to the node Q.
An inverted signal of the signal at node Q is output.

Node Q is connected to the transfer permission output terminal RO via an inverter 305, and node Q is connected via an inverter 306 to one input terminal of the two-man NAND game 30B. The other input terminal of NAND gate 3.3 is connected to transfer enable input terminal R1. The output terminal of the NAND gate 3o3 is connected to the pulse output terminal co via the delay circuit 304.
and to node R of the RS flip-flop 111.

Next, the operation of the transfer control circuit shown in FIG. 13 will be explained with reference to the timing chart shown in FIG. 14.

First, when a negative pulse is applied to the mask reset terminal MR, this transfer control circuit is initialized.

As a result, "1°" is output to the pulse output terminal co1 node and the transfer permission output terminal RO.The output of the transfer permission output terminal RO is "1", indicating the transfer permission state, and "0". indicates that transfer is prohibited.

When a negative pulse is applied from the previous stage to the pulse input terminal CI based on the fact that the transfer permission signal from the transfer permission output terminal RO is in the permission state, the RS flip-flop 111
is set, and the output of node Q becomes "1". As a result, the output from the transfer permission output terminal RO becomes “0” (M
(stop state).

Further, the output from node Q becomes "0#", and the signal at node RQ becomes "1" by inverter 306.

When the transfer permission signal applied from the subsequent stage to the transfer permission input terminal R1 is “1° (permission state), the gate 3
The output of 03 becomes "0", and the RS flip-flop 11
1 is reset. This allows the output of node Q to be “
0", and the transfer permission signal from the transfer permission output terminal RO becomes "1" (inhibited state). Also, the output of node Q becomes "1", and the signal at node RQ becomes "0". , the input to node R returns to "1", and the RS flip-flop 111 returns to its initial state.

Through the series of operations described above, a negative pulse is applied to node R. This negative pulse is transmitted to the delay circuit 304
It is output from the pulse output terminal CO via the pulse output terminal CO.

If the transfer permission signal applied to the transfer permission input terminal R1 is “0” (prohibited state) when the signal at node RQ becomes “1”, the input to node R will not become “0”. . Therefore, pulse transfer is suspended.

In this way, the pulse input to the pulse input terminal CI is autonomously transmitted to the pulse output terminal C based on the state of the transfer permission signal applied from the subsequent stage to the transfer permission input terminal R1.
Transferred to O.

Note that each of the front stage section and the rear stage section is a peripheral circuit or a similar transfer control circuit.

FIG. 15 shows a plurality of transfer control circuits 1a, lb.

1c is a block diagram showing an example in which a plurality of data holding circuits 2a, 2b, and 2C are connected in series. FIG.

In FIG. 15, the pulse output terminal CO of the transfer control circuit 1a is connected to the pulse input terminal CI of the transfer control circuit 1b, and the pulse input terminal CI of the transfer control circuit 1c is connected to the pulse output terminal CO of the transfer control circuit 1b. Connected. The transfer permission output terminal RO of the transfer control circuit 1b is connected to the transfer permission input terminal R1 of the transfer control circuit 1a, and the transfer permission input terminal R1 of the transfer control circuit 1b is connected to the transfer permission output terminal RO of the transfer control circuit 1c. be done.

FIG. 16 is a timing chart for explaining the operation of the transfer control circuits connected in series as shown in FIG. 15.

In FIG. 16, the time Tt from the fall of the input of the pulse input terminal CI to the fall of the output of the pulse output terminal CO indicates the propagation delay time when the pulse passes through the transfer control circuit. Also, the time T'' from one fall of the output from the pulse output terminal CO to the next fall indicates the data input/output interval.Which of the propagation delay time Tt and the data input/output interval T'' is also determined by the configuration of the transfer control circuit.

[Problems to be Solved by the Invention] The transfer control circuit shown in FIG. 13 mainly has three problems, as explained below.

(1) The transfer permission signal applied to the transfer permission input terminal R1 only indicates permission or prohibition of the transfer of pulses to the subsequent stage, and the pulse output from the pulse output terminal CO is not safely received by the subsequent stage. Whether it is or not is not considered. Therefore, even if the pulse output from the pulse output terminal CO disappears due to some factor in the process until it reaches the subsequent stage, it will not be clear. This causes system malfunction.

In addition, when the distance or time from the transfer control circuit to the subsequent stage is long, such as when many buffers are inserted between the transfer control circuit and the subsequent stage, or when the transfer permission input is input from the subsequent stage. When the response of the transfer permission signal applied to the terminal R1 is slow, when pulses are continuously applied to the pulse input terminal CI, the pulses are continuously output from the pulse output terminal CO. Therefore, the subsequent stage cannot receive these continuous pulses, and there is a possibility of malfunction.

(2) If the input to the pulse input terminal CI remains at "0" after the input to the node R of the RS flip-flop 111 becomes "0" until it returns to "1" again. In this case, the input to the node S and the input to the node R of the RS flip-flop 111 are both "0". This state is a prohibited state. As a result, as shown in FIG. It will oscillate.

In other words, even though the RS flip-flop 111 is not actually reset, the input to the node R is “
0", it becomes a prohibited state, and the output from node Q becomes "1". Therefore, the signal at node RQ becomes "1".
0'', and the input to node R returns to ``1'' again. However, since the RS flip-flop 111 is in the set state, the output from node Q remains ``1''. The output from Q becomes "O" again.Thereby, the input to node R becomes "0" again. Such operations are repeated.

Therefore, the pulse width of the negative pulse applied to the pulse input terminal CI needs to be sufficiently short (the period of "0" is short). However, in this case, there is a risk that the pulses are likely to disappear during the pulse transmission process.

(3) The width of the pulse output from the pulse output terminal CO is preferably as long as possible in order to eliminate the risk of the pulse disappearing.

In addition, when configuring a data flow pipeline system using a self-synchronous transfer control circuit, the processing time for data between pipeline stages is the time from the input of a pulse to the pulse input terminal CI to the pulse output terminal CO. The propagation delay time until the pulse is output is determined by Tt. If the propagation delay time Tt is short, high-speed operation becomes possible, or the data processing time in one stage of the pipeline becomes short.

Therefore, the processing content is limited, or more pipelines are required to perform a certain amount of processing. On the other hand, if the propagation delay time Tt is long, the content that can be processed in one stage of the pipeline will be rich, but the system operation will be slow. Therefore, it is desirable to set the optimum delay time of the transfer control circuit according to the system specifications.

In the transfer control circuit shown in Fig. 13, the width of the output pulse and the time from when the pulse is input to the pulse input terminal CI until it is output from the pulse output terminal CO are set to optimal values for the reasons shown below. It is extremely difficult to configure.

First, we will consider how to widen the pulse width. As is clear from the timing chart of FIG. 14, the width of the pulse output from the pulse output terminal CO is determined by the delay time from input to gate 302 to output from gate 303. Therefore, an attempt is made to widen the pulse width by increasing the delay time of the inverter 306. The results of this adjustment are shown in the timing chart of FIG. As shown in FIG. 18, the width of the pulse propagating through node RQ is wide. However, before the signal at node RQ returns to "0", the input to node R returns to "1" in response to a transmission permission signal applied from the subsequent stage to transmission permission input terminal RI. As a result, the width of the pulse output from the pulse output terminal CO is not widened as desired.

Therefore, in order to slow down the response to the input to the transmission permission input terminal R1, try increasing the delay time of the delay circuit 304. The result of the adjustment is shown in the timing chart of FIG. The width of the pulse transmitted through node RQ is widened as described above.

Furthermore, due to the expansion of the delay time of the delay circuit 304, the fall of the input to the transmission permission input terminal R1 provided from the previous stage is delayed. This slows down the rise of the input to node R. As a result, the width of the pulse output from the pulse output terminal CO is also widened as desired.

However, as the width of the pulse transmitted through node RQ increases, the period during which the input to node R is "0" also becomes longer. If the input to node R is “Oo”, pulse input terminal CI
Even if the input to node Q is “0”, the output from node Q is “1”.
'' remains unchanged, and the signal at node RQ remains at "0" and does not change. Therefore, no pulse can be input to pulse input terminal CI during the period when the input to node R is "0".

In this way, as the period during which the input to the node R is "0" is expanded, the period during which no pulse can be input to the pulse input terminal CI is also lengthened. Moreover, even though the output from the transmission permission output terminal RO is "1" (permission state), a period T1 occurs during which no pulse can be input to the pulse input terminal CI.As a result, The significance of the transmission permission signal output from the transmission permission output terminal RO is almost completely lost.This phenomenon also appears in FIG.

In order to deal with this contradiction, try delaying the timing at which the output from the transmission permission output terminal RO returns to "12".

Then, this timing delay is also reflected in the later stages,
The input to the transmission permission input terminal R1 is shifted to the right at the timing when it rises to "1" (position of point A).As a result, the timing at which the output from the pulse output terminal CO falls to "0" (position at point B) is shifted to the right. ) is also shifted to the right.As a result, only the data input/output interval Tr becomes larger.

The shorter the data input/output interval Tr, the greater the amount of data processed per unit time, and the faster the system becomes. On the other hand, the larger the pulse propagation delay time Tt,
The content that can be processed in one stage of the pipeline becomes richer. Pulse propagation delay time Tt is data input/output interval Tr
Although it is impossible to make the former larger than the latter, it is extremely important to make the former as close as possible to the latter in order to configure a system that is efficient in terms of timing. As shown in FIG. 19, increasing only the data input/output interval Tr increases waste in timing.
Undesirable.

For the reasons mentioned above, the pulse width, propagation delay time Tt, and data input/8
It is necessary to set the force interval Tr to an optimal value.

However, as described above, in the conventional transfer control circuit, it is extremely difficult to set these values to optimal values.

The purpose of this invention is to: 1) prevent malfunctions due to pulse extinction or excessive pulse transfer; 1) prevent oscillation even when the input pulse width is long; and 2) easily adjust the pulse width and propagation delay time. An object of the present invention is to provide a configurable self-synchronous transfer control circuit.

Another object of the present invention is to provide a self-synchronized transfer control circuit having a function of inhibiting transfer at any timing.

[Means for Solving the Problems] The transfer control circuit according to the first invention converts a first pulse given from a previous stage into a second pulse to a second pulse based on an instruction signal instructing permission or prohibition of transfer. A self-synchronized transfer control circuit for transferring data to a computer, the self-synchronized transfer control circuit comprising a first storage means, a second storage means and a logic means. The first storage means has a reset function and stores the first pulse. The second storage means has a reset function and is reset in response to the inhibited state of the instruction signal. The logic means stores the first pulse, the first pulse is not applied to the first storage means, and the second storage means is in a reset state. and outputs a pulse in response to the instruction signal being in the permission state. The first storage means is reset by a pulse output from the logic means, and the second storage means stores the pulse output from the logic means and generates a second pulse.

The self-synchronized transfer control circuit according to the second invention further includes, in addition to the transfer control circuit according to the first invention, delay means for delaying the second pulse output from the second storage means.

The self-synchronized transfer control circuit according to the third invention includes, in addition to the transfer control circuit according to the first invention, a blocking means for forcibly blocking the output of pulses from the logic means in response to a predetermined prohibition signal. Furthermore, it is equipped with.

A self-synchronized transfer control circuit according to a fourth invention further includes, in addition to the transfer control circuit according to the first invention, blocking means for forcibly blocking the output of the second pulse from the second storage means. Be prepared.

A self-synchronized transfer control circuit according to a fifth aspect of the invention further includes prohibition signal generating means and blocking means in addition to the transfer control circuit according to the first invention. The prohibition signal generating means generates a predetermined prohibition signal in response to the application of a predetermined request signal and the reset state of the second storage means. The blocking means blocks output of the second pulse from the second storage means in response to the inhibit signal.

[Operation] In the self-synchronized transfer control circuit according to the first to fifth inventions, unless the instruction signal becomes an inhibited state and the second storage means is reset, the second storage means does not receive the second pulse. Maintain output state.

Therefore, malfunctions due to pulse disappearance are prevented.

Furthermore, the second storage means is reset when the instruction signal is in the prohibited state, and the second storage means does not output the next second pulse unless the instruction signal is subsequently placed in the permission state.

Therefore, malfunctions due to excessive pulse transfer are prevented.

Furthermore, while the first pulse is input to the first storage means, the logic means does not generate a pulse, and the transfer of the pulse from the first storage means to the second storage means is suspended. Therefore, even if the width of the first pulse is sufficiently long, the output of the logic means does not oscillate.

Therefore, it becomes possible to input a first pulse having an arbitrary width into the first storage means.

In particular, in the self-synchronized transfer control circuit according to the second invention, by setting the delay time of the delay means to an arbitrary value, the operations of the first and second storage means and logic means are not affected at all. It is possible to set the optimal output pulse width and propagation delay time according to the system specifications without having to worry about the system specifications.

Further, even if the delay time of the delay means is adjusted, the difference between the propagation delay time and the data input/output interval is always constant, so there is no deterioration in timing performance.

Further, the amount of change in the pulse width of the output pulse due to adjustment of the delay time and the amount of change in the data input/output interval are 1:2, which is an optimal value. Therefore, in this respect as well, there is no performance deterioration due to delay time adjustment.

According to the self-synchronous transfer control circuit according to the fifth aspect of the invention, when a predetermined request signal is given and the second storage means is in the reset state, the prohibition signal is generated, and the prohibition signal is generated when the second storage means is in the reset state. The pressure of the second pulse is blocked. Therefore, no matter what timing the request signal is applied, the transfer of the pulse is immediately blocked, or the transfer of the next pulse is blocked after the current pulse has been successfully transferred. In this way, one of two stable blocking operations is performed.

Furthermore, even if a sufficiently slow pulse occurs that the operation of the first and second storage means cannot be guaranteed, one of the two stable operations described above is guaranteed. Therefore, there is no need to predict the operations of the first and second storage means.

[Embodiments] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a circuit diagram showing the configuration of a self-synchronous transfer control circuit according to a first embodiment of the present invention.

Figure 1 NIOITE, NAND gates 101 and 102 are RS
Configuring the flip-flop 111, NAND game 1-1
04 and 105 constitute the RS flip-flop 112. The operation of each of the RS flip-flops 111 and 112 is similar to that of the RS flip-flop 111 shown in FIG.

The first input terminal of the four-power NAND gate 103 is connected to the pulse input terminal CI, the second input terminal is connected to the node Q of the RS flip-flop 111, and the third input terminal is connected to the transfer enable input terminals R1 and RS. It is connected to the node R of the flip-flop 112, and its fourth input terminal is connected to the pulse output terminal CO. The output terminal of gate 103 is connected to node S of RS flip-flop 112.

Node Q of RS flip-flop 112 is connected to pulse output terminal CO via two inverters 107 and 108.

Next, the operation of the transfer control circuit shown in FIG. 1 will be explained with reference to the timing chart shown in FIG.

First, when a negative pulse is applied to the mask reset input terminal MR, the transfer control circuit shown in FIG. 1 is initialized. As a result, "1" is output to the pulse output terminal CO1 node RQ and the transfer permission output terminal RO.

When the front section (not shown) inputs a negative pulse to the pulse input terminal CO in response to the pressure from the transfer permission output terminal RO being "1" (permission state), the transfer control responds to the falling edge of the pulse. Then, the RS flip-flop 111 is set, and the output from the note Q becomes "1°."As a result,
The output from the transfer permission output terminal RO becomes “0° (prohibited state).

In this way, the front stage is notified that a pulse has been received.

Is the transfer permission signal applied to the transfer permission input terminal R1 at the rising edge of the pulse applied to the pulse input terminal CI?
1" (permitted state), the output of the gate 103 (signal at node RQ) becomes "O". Therefore, the input to the node R of the RS flip-flop 111 becomes "0", and the RS flip-flop 111 will be reset.

As a result, the output from the node Q of the RS flip-flop 111 becomes "0", and the output from the transfer permission output terminal RO becomes "1". Further, the output of gate 103 (signal at node RQ) returns to "1".

At this point, the circuits around the RS flip-flop 111 have been initialized.

Due to the above operation, a negative pulse is generated at node RQ. The negative pulse sets the RS flip-flop 112, and the output from node Q is “
The output of "Oo" from each node is outputted to the pulse output terminal CO through the inverters 1.07 and 108. At the same time, its output is fed back to gate 103.

Thereby, the gate 103 is locked so as not to output "0" again.

When the subsequent stage section (not shown) detects "0" output from the pulse output terminal CO, it inputs a negative pulse to the transfer permission input terminal R1.As a result, the subsequent section outputs from the pulse output terminal CO. This transfer control circuit is notified that "0" has been detected.

The RS flip-flop 112 is reset at the falling edge of the pulse applied to the transfer permission input terminal R1.

As a result, the output from the pulse output terminal CO returns to "1°," the peripheral circuit is initialized, and the gate 103 is unlocked.In this way, the pulse output from the pulse output terminal CO is Output.

On the other hand, the gate 103 remains in the locked state due to the input to the transfer permission input terminal R1 until the pulse input to the transfer permission input terminal R1 rises to "1".

In this way, while the RS flip-flop 112 is performing the above-mentioned series of operations, the negative pulse applied to the pulse input terminal CI causes the RS flip-flop 111 to switch again.
is set, a negative pulse is not output from the gate 103 until the input to the transfer enable input terminal RI rises to "1". Therefore, the RS flip-flop 1
The transfer of pulses from 11 to RS flip-flop 112 is suspended.

Furthermore, even if the RS flip-flop 111 is set by inputting a negative pulse to the pulse input terminal CI, if the input to the transfer permission input terminal RI is in the "0" state (inhibited state), a negative pulse is applied to the node RQ. Pulse - is not output. Therefore, RS flip-flop 1 via node
The transfer of pulses to 12 and further to the pulse output terminal CO are suspended.

In this way, the pulse input to the pulse input terminal CI is autonomously transmitted to the pulse output terminal C according to the state of the transfer permission signal input from the subsequent stage to the transfer permission input terminal R1.
Transferred to O.

FIG. 3 is a timing chart showing the operation when a plurality of transfer control circuits having the configuration shown in FIG. 1 are connected in series as shown in FIG. 15.

In a data flow type system, a plurality of transfer control circuits having the configuration shown in FIG. 1 are connected in series to control pulse transfer in the system. In FIG. 3, Tt indicates a propagation delay time when a pulse passes through the transfer control circuit of FIG. 1, and Tr indicates a data input/output interval.

These times are determined by the circuit constants of the transfer control circuit shown in FIG.

FIG. 4 is a circuit diagram showing the configuration of a self-synchronous transfer control circuit according to a second embodiment of the present invention.

In the transfer control circuit shown in FIG. 4, a delay circuit 201 is connected between the output terminal (node CO') of the inverter 108 and the pulse output terminal CO. Let D be the amount of delay of the delay circuit 201.

The operation of the transfer control circuit shown in FIG. 4 will be explained with reference to the timing chart shown in FIG.

A transfer control circuit having a similar configuration is connected to the input side and output side of the transfer control circuit shown in FIG.

As is clear from FIG. 5, the output from the pulse output terminal CO always lags behind the output from the node CO by the amount of delay. Therefore, assuming that the widths of the pulses input to the pulse input terminals C and I are the same, the time it takes for a pulse to pass through this transfer control circuit becomes longer by the amount of delay. Furthermore, since the transfer permission signal applied from the output side transfer control circuit to the transfer permission input terminal R1 is also delayed by the amount of delay, the width of the pulse output from the pulse output terminal CO is also widened by D.

Furthermore, when the same pulse as the pulse output from the pulse output terminal CO is input to the pulse input terminal CI (the first pulse given to the pulse input terminal CI in FIG. 5), the pulse passes through the transfer control circuit. The propagation delay time Tt and the pulse input/output interval Tr are compared. Since a transfer control circuit with the same configuration is also connected to the input side, the width of the pulse input to the pulse input terminal CI is widened by D, and the falling edge of the pulse output from the pulse output terminal CO is delayed. I will be late by the time I weigh it. Therefore, the propagation delay time Tt becomes longer by 2×D. The rise of the output from the pulse output terminal CO is at the node CO'
Since the data input/output interval Tr is delayed by the amount of delay from the rise of the output, the data input/output interval Tr is lengthened by a time of 2XD.

In this way, even if the delay circuit 201 is inserted, the difference between the propagation delay time Tt and the data input/output interval Tr does not change.

Here, assuming that the width of the pulse input to the pulse input terminal CI is the same as the width of the pulse output from the pulse output terminal CO is because the transfer control circuit having the configuration shown in FIG. When connected in series, the width of the pulse input to the pulse input terminal CI is equal to the width of the pulse output terminal C.
This is because it is the width of the pulse output from O.

By inserting the delay circuit 201, the data input/output interval T
While r has increased by 2'XD, the output pulse width has increased by D. Therefore, by inserting the delay circuit 201, the magnitude of the change in pulse width and
The ratio of the change in the data input/output interval Tr is 1
It will be 2 vs. This is important because the duty ratio approaches the most suitable amount, 50%.

Further, even if the delay circuit 201 is inserted on the output right side, the operation of the circuits around the RS flip-flop 1110 is not affected, and the same operation as the transfer control circuit shown in FIG. 1 is performed.

FIG. 6 is a circuit diagram showing the configuration of a self-synchronous transfer control circuit with a transfer inhibiting function according to a third embodiment of the present invention.

In the transfer control circuit of FIG. 6, a five-man power NAND gate 202 is used in place of the four-man power NAND gate 1'03. A fifth input terminal of the gate 202 is connected to an inhibit signal input terminal INH that receives an inhibit signal. When the input to the inhibition signal input terminal INH is set to “0”,
Pulse propagation is forcibly blocked.

The operation of the transfer control circuit shown in FIG. 6 will be explained with reference to the timing chart shown in FIG.

During the period when the input to the inhibition signal input terminal INH is "0", the output of the gate 202 is locked to "]". Therefore, even if a pulse is input to the pulse input terminal CI, the gate 202 does not output the pulse, and the pulse is not transferred to the RS flip-flop 112.

On the other hand, the pulse input to the pulse input terminal CI is R
It is stored in the S flip-flop 111. Therefore, the pulse transfer is put on hold. When the input to the inhibition signal input terminal INB becomes “1@”, gate 2
02 is unlocked. This causes the pulse to RS
Flip-flop 111 to RS flip-flop 11
2, and the transferred pulse is output from the pulse output terminal CO.

2, according to the transfer control circuit of FIG. 6, by using the input to the inhibition signal input terminal INH, it is possible to control permission and inhibition of pulse transfer from the peripheral circuit.

FIG. 8 is a circuit diagram showing the configuration of a self-synchronous transfer control circuit with a transfer inhibiting function according to a fourth embodiment of the present invention.

In the transfer control circuit of FIG. 8, the output terminal (node CO') of inverter 108 is connected to one input terminal of AND gate 203, and the output terminal of gate 203 is connected to pulse output terminal CO. The other input terminal of gate 203 is connected to an inhibition signal input terminal INH that receives an inhibition signal. By setting the input to the inhibition signal input terminal INH to "1" by the peripheral circuit, propagation of the pulse is forcibly blocked.

The operation of the transfer control circuit shown in FIG. 8 will be explained with reference to the timing chart shown in FIG. 9.

If a negative pulse is input to the pulse input terminal CI during a period when the input to the inhibition signal input terminal INH is "1", this negative pulse is passed through the node RQ to the RS flip-flop 1.
Transferred to 12. However, the output of this negative pulse to the pulse output terminal CO is blocked by the gate 203.

Here, the pulse transferred from the RS flip-flop 111 to the RS flip-flop 112 is stored in the RS flip-flop 112, and the transfer is put on hold. In this state, since the RS flip-flop 111 has returned to its initial state, it is possible to manually input one more pulse to the pulse input terminal CI. And input to the inhibition signal input terminal INH?
0'', the signal at node CO' or the pulse output terminal C
Output to O.

When the first pulse is output from the pulse output terminal CO, the pulse held in the RS flip-flop 111 is transferred to the RS flip-flop 112, and the second pulse is output from the pulse output terminal CO.
The second pulse is output from the pulse output terminal CO. As described above, according to the transfer control circuit of FIG. 8, similarly to the transfer control circuit of FIG. 6, by using the input to the inhibition signal input terminal INH, transfer of pulses from the peripheral circuit is permitted and inhibited. It becomes possible to control the

FIG. 10 is a circuit diagram showing the configuration of a self-synchronous transfer control circuit with a transfer inhibiting function according to a fifth embodiment of the present invention.

In FIG. 10, a delay circuit 204 is connected between node Co' and one input terminal of AND gate 205, and an arbitration storage circuit 210 is connected between node CO' and the other input terminal of AND gate 205. Ru. The output terminal of gate 205 is connected to pulse output terminal CO. gate 2
．． 05 is a transfer inhibition gate. When the output of the node INHI is "1 degree", no pulse is output to the pulse output terminal CO.

The arbitration storage circuit 210 includes NAND gates 211 and 212.
．． 213, and gates 211 and 212 constitute an RS flip-flop. The node IN is a pulse input terminal, and the only node is a reset/pulse invalidation function input terminal. When the input to node L is “0”, node I
Regardless of the input to N, "0" is output from node INHI. Even if the input to node L is “1”, if the input to node IN is “0”, node ■N
HI continues to output "0". Human power to node L “1”
” When the input to the node IN becomes “1,” “1” is output from the node INHI. This state continues even if the input to node LN returns to "0".

Note that after this, no matter what chain the input to JN is,
When the input to node L falls to “0”, node INH
The output of I returns to "0" again.

Node L of arbitration storage circuit 210 is connected to a request signal input terminal REQ that receives a request signal for blocking pulse transfer from a peripheral circuit.

The operation of the transfer control circuit in FIG. 10 is shown in FIGS. 11a and 11b.
11c and 11d.

First, when a negative pulse is applied to the mask reset input terminal MR, this transfer control circuit is initialized. As a result, "1" is output from the pulse output terminal CO, the node RQ, and the transfer permission output terminal RO.

Referring to the timing chart of FIG. 11A, the operation when no transfer inhibition request is given from the peripheral circuit (when the request signal input terminal REQ is "O") will be described.

In this case, the operation of the arbitration storage circuit 210 causes the node I
“0” is output from NHI.

In response to the output from the transfer permission output terminal RO being "1" (permission state), a negative pulse is input to the previous stage section (not shown) or to the pulse input terminal CI.

In response to the falling of the negative pulse, the RS flip 70 knob 111 is set, and the output from the node Q becomes "1". Further, 0'' is output from the transfer permission output terminal RO, and the previous stage is notified that the pulse has been received.

If the input to the transfer permission input terminal R1 is "1" (permitted state) at the rising edge of the pulse input to the pulse input terminal CI, the output of the gate 103 (signal at node RQ) becomes "0". This resets the RS flip-flop 111. Therefore, the output from the node Q of the RS flip-flop 111 becomes "0", and the output from the transmission permission output terminal RO becomes "1° (
Permit! ! 3). Further, the output of the gate 103 (signal of the node RQ) returns to "1". At this point, the R
This means that the circuitry around the S flip-flop 111 has returned to its initial state.

Due to the above operation, a negative pulse is generated at node RQ. The negative pulse sets the RS flip-flop 112, and the output of the node CO' becomes "O". The output of node CO' is applied to gate 205 via delay circuit 204 after a certain delay time. Since the output of node INH1 is “0°,” node C
The output from O' passes through the gate 205, and "0°" is output to the pulse output terminal CO.

At the same time, the output of node CO' is fed back to gate 103. Thereby, the gate 103 is locked so that it does not become "0" again.

The latter part (not shown) is “0” from the pulse output terminal CO.
Upon detection of the output, a negative pulse is applied to the transfer permission input terminal R1. This notifies the transfer control circuit that the subsequent stage has detected a negative pulse.

In response to the fall of the negative pulse applied to the transfer permission input terminal R1, the RS flip-flop 112 is reset, and the outputs from the node CO' and the pulse output terminal CO return to "1". As a result, the peripheral circuits return to their initial states. Furthermore, the lock of gate 103 due to the output from node CO' is also released. In this way, a pulse is output from the pulse output terminal CO.

Referring to FIG. 11B, the operation when a transfer inhibition request is given when a pulse transfer operation is not in progress and the transfer restart operation will be described.

When the pulse transfer operation is not in progress (when the output of node CO' is "1"), the request signal input terminal REQ
When the input to the node INHI becomes "1" (peripheral circuit requests to suppress transfer!!3), the output from the node INHI becomes "1' due to the operation of the arbitration memory circuit 210. In this state, the pulse When a negative pulse is input to the input terminal CI, the RS flip-flop 111 is set, the output from the node Q becomes "1", and the transfer permission output terminal RO is set.
The output from is “0” (inhibited state).

As a result, as explained with reference to FIG. 11A, a negative pulse is generated from the node RQ, the RS flip-flop 111 is reset by the negative pulse, and the output from the transfer permission output terminal RO returns to "1". . Also,
The negative pulse sets the RS flip-flop 112 and outputs "0" to the node CO'. The output of node CO' is applied to gate 205 via delay circuit 204 after a certain delay time. However, node I
Since the output of NHI is "1", the output of node CO' is not output to pulse output terminal CO due to the action of gate 205.

When the input to the request signal input terminal REQ falls to "0", the output of the node INHI changes to "0" due to the operation of the arbitration storage circuit 210. Thereby, the output from the node CO' passes through the gate 205 to the pulse output terminal CO.
, and "0" is output to the subsequent stage.

Thereafter, the transfer operation is performed based on the procedure explained with reference to FIG. 11A, and the pulse stored and held in the RS flip-flop 112 is output from the pulse output terminal CO.

The operation when a transfer inhibition request is given during a pulse transfer operation will be described with reference to FIG. 11C.

When a negative pulse is input to the input terminal CI while the input to the request signal input terminal REQ is in the state of "0" (when the output of the node INHI is "0°"), the operation explained in FIG. 11A is performed. As a result, the output from the node CO' and the pulse output terminal CO becomes "0". When the output from the node CO' is "0" (during pulse transfer), the input to the request signal input terminal REQ becomes "0". 1'' (transfer inhibition request), the output from the node INHI does not immediately change to "1" due to the operation of the arbitration storage circuit 210.

Furthermore, in response to the output from the transfer permission output terminal RO being "1", a negative pulse is added to the pulse input terminal CI. However, if the output of node CO' is "0" or if gate 103 is locked based on the input to transfer enable input terminal R1 being "0", then the negative pulse to node Rσ is Generation is deferred and the negative pulse remains in the RS flip-flop 111.

On the other hand, in response to the output from the pulse output terminal CO being "0", the subsequent stage section (not shown) outputs the transfer permission input terminal R.
When "0" is given to 1, the RS flip-flop 112 is reset, and the output from node CO' becomes ".

At this point, the arbitration storage circuit 210 operates and the node IN
The output from HI becomes "1". As a result, gate 2
05, an instruction is given to block the pulse transfer.

When the input to the transfer permission input terminal R1 returns to "1", the gate 103 is unlocked and a negative pulse is output to the node RQ based on the additional pulse. The negative pulse resets RS flip-flop 111 and sets RS flip-flop 112.

As a result, the output from node CO' becomes "0".

However, even if the output from node CO' becomes "0" again, the output from node INHI does not return to "0" due to the operation of arbitration storage circuit 210, so the output from node CO' becomes "0" again. After passing, the gate 205 blocks output to the pulse output terminal CO.

The operation of resuming transfer after the transfer inhibition described above is similar to the operation described with reference to FIG. 11A.

In this way, the request signal input terminal R can be connected at any timing during the pulse transfer operation or even during continuous transfer operations.
When "1" is input to the EQ, the transfer inhibiting function starts working at the time when the transfer of one pulse during the transfer operation is completed, so as to intersect between the transfer operations of the pulses.

Referring to FIG. 11D, the operation in the most critical case of conflict between the pulse transfer operation and the transfer inhibition request will be described.

The most critical case is when the timing at which the pulse transfer is about to start and the timing at which the transfer inhibition request is issued are almost the same. Such a situation can easily occur if the pulse transfer operation and the transfer inhibition request are performed completely asynchronously.

In FIG. 11D, the timing at which pulse transfer is about to start is the fall of the output of node CO', and the timing at which the transfer inhibition request is given is the rise of the input to the request signal input terminal REQ. If the timings of both signals are very close to each other, especially if the input to the request signal input terminal REQ rises slightly earlier than the fall of the output of node CO', A thin negative pulse is generated. When an extremely thin pulse is manually applied to the RS flip-flop constituted by gates 211 and 212, R
Neither the set operation of the S flip-flop nor the maintenance of the current storage state can be guaranteed.

Therefore, whether the output from node INHI is “0” or “1”
However, although prediction is impossible, the output from the node INHI is always stable at either "0' or "1". In the transfer control circuit shown in FIG. 10, no matter what value the output from the node INHI takes, stable operation of the entire circuit thereafter is guaranteed.

Assuming that the RS flip-flop performs a set operation, the output from node INHI becomes "1". As a result, the gate 2
Transfer of the pulse arriving at 05 is blocked by its gate 205. Therefore, it means that the transfer suppression function worked normally.

On the other hand, assuming that the RS flip-flop retains its current storage state, the output from node INHI is “0”.
”.Thereby, the pulse that has arrived at the gate 205 via the delay circuit 204 is transmitted to the gate 205.
and is output from the pulse output terminal CO. This means that the pulse transfer operation was performed normally.

In the latter case, whether the transfer inhibition request is not satisfied immediately or the transfer inhibition function becomes effective as soon as the current pulse transfer is completed, as explained with reference to FIG. 11C.

Finally, the influence of the delay amount of the delay circuit 204 on the transfer control circuit shown in FIG. 10 will be explained.

First, if the delay amount of the delay circuit 204 is not set to a sufficiently long value, there is a risk of malfunction. As in the timing example shown in FIG. 11D, consider the case where the input signal to the request signal input terminal REQ rises immediately before the fall of the output from node CO', and this eventually becomes effective. In this case, the node INH1 instructs to block the transfer.
The output of the node CO' is input to the node IN of the arbitration storage circuit 210 from the falling edge of the output of the node CO' to the node IN.
, is determined after the delay time until the output from H1.

If the output from the node CO' passes through the delay circuit 204 until this determination, the output passes through the gate 205 as is, and the output from the pulse output terminal CO becomes "0".
”. Thereafter, the transfer inhibition function of the gate 205 is activated by the output from the node INHI.

As a result, a very narrow negative pulse (glitch) will occur at the pulse output terminal CO.

In this way, if a pulse that does not have a sufficient width is output to the pulse output terminal CO, there is a risk that an unexpected malfunction will occur in the subsequent stage. Therefore, it is necessary to set the amount of delay of delay circuit 204 to be sufficiently larger than the delay time from input to node IN of arbitration storage circuit 210 to output from node INH.

On the other hand, the operation when the delay amount of the delay circuit 204 is made too long will be explained. In normal pulse transfer operation,
As is clear from FIG. 11A, the pulse output terminal CO
The timing of the rise of the output from node CO' is approximately the delay amount of delay circuit 204 after the rise of the output of node CO'. Furthermore, when the transfer inhibit function 1F operates immediately after the pulse is transferred, as is clear from FIG. Before the rise of
The rising edge of the output of node CO' is input to node IN of arbitration storage circuit 210. As a result, the arbitration memory circuit 2
10 operates, and the output from the note INH1 becomes "0". As a result, Keto 205 operates and pulse output terminal C
The output from O returns to "1". Therefore, in this case, the timing of the rise of the output from the output terminal CO is after the delay time from the input to the node IN of the arbitration storage circuit 210 to the output from the node INHI, after the rise of the output of the note CO'. Become.

In this way, the delay amount of the delay circuit 204 or the arbitration storage circuit 2
If the delay amount is too large compared to the delay amount of 10, a large fluctuation will occur in the width of the pulse output from the pulse output terminal CO.

As mentioned above, considering the influence that the delay amount of the delay circuit 204 has on the transfer control circuit shown in FIG. Conceivable.

Note that the present invention is not limited to the circuits of the first to fifth embodiments described above. For example, positive logic or negative logic may be used for each part. Specifically, a circuit that gives a positive pulse to the pulse input terminal CI, a circuit that outputs a positive pulse from the pulse output terminal CO, and a circuit that outputs a positive pulse from the pulse output terminal CO, transfer when the output from the transfer permission output terminal RO is "O". A circuit that indicates a permission state for transfer, a circuit that indicates a transfer permission state when the input to the transfer permission input terminal R1 is "0", etc. are possible. A circuit in which the input of "0°" to the request signal input terminal REQ indicates a transfer inhibition request is also possible.

Further, NOR logic may be used for the RS flip-flops 111 and 112 or the arbitration storage circuit 210. RS flip-flops 111, 112 or arbitration storage circuit 21
0, a D flip-flop with a set/reset function may be used.

Furthermore, the transfer permission output terminal RO, the pulse output terminal CO, or the node INHI may be taken out from the other output node of the flip-flop.

As the gates 102 and 202, other logic gates that perform operations with the same polarity as the gates 102 and 202 may be used.

In a fifth embodiment, node INHI or gate 2
The output terminal 11 may be provided with an output terminal that outputs a signal indicating that the transfer inhibiting function is operating in the peripheral circuit.

The transfer control circuit of the present invention is applicable not only to data flow type systems but also to other systems or devices that require self-synchronized transfer.

According to the first to fifth embodiments described above, the problems in conventional transfer control circuits are solved as follows.

According to the transfer control circuits of the first to fifth embodiments, the pulse output terminal CO continues to output "0" unless a transfer permission signal of "O" is input to the transfer permission signal input terminal R1 from the subsequent stage. . Therefore, malfunctions due to pulse disappearance are prevented.

In addition, in response to the subsequent stage receiving the negative pulse output from the pulse output terminal CO, the transfer permission input terminal R
This transfer control circuit does not output the next pulse unless "0" is given to "1" and "1" is subsequently given to the transfer permission input terminal R1 to permit the transfer of the next pulse. Therefore, malfunctions due to excessive pulse transfer are prevented.

In this way, the first problem in the conventional transfer control circuit has been solved.

In the transfer control circuit of the first to fifth embodiments, even after the input to the pulse input terminal CI falls, the gates 103 and 202 are locked until the input returns to "1" again. The transfer is put on hold. Therefore, malfunction (oscillation) when the pulse width input to the pulse input terminal CI is sufficiently long is prevented. As a result, it is possible to input a pulse of any width to the pulse input terminal CI.

In this way, the second problem with the conventional transfer control circuit has been solved.

The difficulty in setting the output pulse width and pulse propagation delay time can be solved by using a delay circuit 20 in the output stage as in the embodiment shown in FIG.
This is solved by inserting 1. Here, the delay time of the delay circuit 201 can be set to a completely arbitrary value, and the output pulse width and propagation delay time can be set to optimal values according to the system specifications. .

Even by inserting the delay circuit 201, the operations of other gates are not affected at all.

Furthermore, even if the circuit constants are adjusted by inserting the delay circuit 201, the difference between the pulse propagation delay time Tt and the data input/output interval Tr remains constant. Therefore, no deterioration in timing performance is observed.

Further, there is a 1:2 relationship between the amount of change in the pulse width of the output pulse due to adjustment and the amount of change in the data input/output interval Tr. Therefore, in this respect as well, no deterioration in performance is observed due to adjustment.

In this way, the third problem with the conventional transfer control circuit is also solved.

[Effects of the Invention] As described above, according to the first to fifth inventions, since reliable transfer control is performed for each pulse, malfunctions due to pulse disappearance or excessive transfer are prevented. Ru.

Furthermore, since malfunctions such as oscillation do not occur, the width of the input pulse can be set arbitrarily.

Furthermore, the width of the output pulse and the pulse propagation delay time can be easily and arbitrarily adjusted. Furthermore, no matter what adjustment is performed, it is possible to set the propagation delay time to a value sufficiently close to the data input/output interval.

In particular, according to the fifth invention, no matter what timing a transfer inhibition request is given, there are two types of stable transfer inhibition: immediate transfer inhibition and transfer inhibition after a normal transfer operation of one pulse in progress. One of the actions is performed. Therefore, malfunctions such as pulse extinction or duplication are prevented.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing the configuration of a self-synchronous transfer control circuit according to a first embodiment of the second invention. Figures 2 and 3
FIG. 1 is a timing chart for explaining the operation of the transfer control circuit shown in FIG. FIG. 4 is a circuit diagram showing the configuration of a self-synchronous transfer control circuit according to a second embodiment of the present invention. FIG. 5 is a timing chart for explaining the operation of the transfer control circuit of FIG. 4. FIG. 6 is a circuit diagram showing the configuration of a self-synchronous transfer control circuit according to a third embodiment of the present invention. FIG. 7 is a timing chart for explaining the operation of the transfer control circuit of FIG. 6. FIG. 8 is a circuit diagram showing the configuration of a self-synchronous transfer control circuit according to a fourth embodiment of the present invention. FIG. 9 is a timing chart for explaining the operation of the transfer control circuit of FIG. 8. FIG. 10 is a circuit diagram showing the configuration of a self-synchronous transfer control circuit according to a fifth embodiment of the present invention. M11A
Figures 11B, 11C and 11D are 10
3 is a timing chart for explaining the operation of the transfer control circuit shown in the figure. FIG. 12 is a block diagram showing the configuration of the data transmission path. FIG. 13 is a circuit diagram showing the configuration of a conventional self-synchronous transfer control circuit. FIG. 14 is a timing chart for explaining the operation of the transfer control circuit of FIG. 13. FIG. 15 is a block diagram showing an example in which a plurality of transfer control circuits are connected in series. FIG. 16 is a timing chart for explaining the operation of the transfer control circuit connected as shown in FIG. 15. FIGS. 17, 18, and 19 are timing charts for explaining problems in the transfer control circuit of FIG. 13. In the figure, 111 and 112 are RS flip-flops, 1
02 is a 4-person NAND gate, CI is a pulse input terminal,
CO is the pulse output terminal, RO is the transfer permission output terminal, RI
indicates a transfer permission input terminal, and REQ indicates a request signal input terminal. Note that the same reference numerals in each figure indicate the same, - or corresponding parts. Figure 11D Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure T+ r

Claims (5)

[Claims] (1) A self-synchronized transfer control circuit that transfers the first pulse given from the front section as a second pulse to the rear section based on an instruction signal instructing permission or prohibition of transfer, and has a reset function. a first pulse having a first pulse and storing the first pulse;
a second memory having a reset function and being reset in response to the inhibited state of the instruction signal; the first memory storing the first pulse; logic means for outputting a pulse in response to the fact that the first pulse is not applied to the first storage means, that the second storage means is in the reset state, and that the instruction signal is in the permission state; The first storage means is reset by a pulse output from the logic means, and the second storage means stores the pulse output from the logic means to generate the second pulse. Self-synchronous transfer control circuit. (2) The self-synchronized transfer control circuit according to claim 1, further comprising delay means for delaying the second pulse output from the second storage means. 3. The self-synchronized transfer control circuit according to claim 1, further comprising blocking means for forcibly blocking the output of pulses from said logic means in response to a predetermined prohibition signal. (4) The self-synchronized transfer control circuit according to claim 1, further comprising blocking means for forcibly blocking output of the second pulse from the second storage means in response to a predetermined prohibition signal. (5) that a predetermined request signal has been given and that the second
prohibition signal generation means for generating a predetermined prohibition signal in response to the storage means being in the reset state; and a second prohibition signal generated from the second storage means in response to the prohibition signal.
2. The self-synchronized transfer control circuit according to claim 1, further comprising blocking means for blocking output of the pulse.