JPH04942A - Wind band digital switching device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention is applicable to wideband ISDN (Integrated S
The present invention relates to a wideband digital switching device that is applied to systems such as ervlces digital networks.

[Conventional technology]

Conventionally, this type of broadband digital switching equipment was [
Nikkei Electronics J 198g, 1.11 (No.

438), P, 128-P, 137 are known. In this switching device, in order to prevent collisions of data cells within a routing network such as a Banyan network, a sorting network such as a Ba-Sochar network is connected upstream of the routing network. A switching device having such a configuration is shown in FIG.

[Problem to be solved by the invention]

However, according to the above switching device, when data cells having the same destination address (destination data) arrive at different input channels of the sorting network, a collision occurs within the sorting network, and one of the cells is discarded. Ta.

For example, each input channel #0 to #7 of the switching device in FIG.
If a data cell arrives with the destination address as shown in the figure, and a data cell with the same destination address "3" arrives at input channel #2~#7, these data cells are indicated by bold lines. Proceed along the route and a collision will occur at the switch element marked with diagonal lines. In FIG. 4, circles indicate switch elements, and the numbers attached to the input terminals of each switch element indicate the destination address included in the incoming data cell. Also, an arrow within each switch element indicates the direction in which data cells with large destination addresses travel. However, if a valid data cell and an invalid data cell arrive at the same switch element, only the valid data cell is considered as the direction of travel, and if the destination data of the valid data cell is 0 to 3, the direction is opposite to the arrow. ,
If the destination data of the valid data cell is 4 to 7, the valid data cell is caused to advance in the direction of the arrow.

Either one of the data cells that arrive at the switch element marked with diagonal lines is discarded (actually, it is invalidated).

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a broadband digital switching device that reduces the data cell discard rate and enables appropriate data transmission.

[Means to solve the problem]

A broadband digital switching device according to the present invention includes a switch network in which a sorting network and a routing network are connected in cascade between a plurality of input channels and output channels;
A wideband digital switching device comprising an input buffer memory provided at the front stage of a plurality of input channels, and a buffer control unit that controls input/output of data cells to the input buffer memory, and a sorting network is provided with incoming destination data. and a multi-stage switch element that switches the route of the data cell to which identification data indicating whether the data is valid or invalid is added to the corresponding output terminal based on the destination data added to the data cell; A switch element detects the arrival of data cells aiming at the same output terminal, makes one of the data cells valid and sends it to a corresponding route, and makes the other data cell invalid and sends it to a different route from the corresponding route, and , a route control means for transmitting a cell collision signal, and a cell collision signal route creation means for creating a route for transmitting the cell collision signal to the buffer control unit by making the cell collision signal travel in the opposite direction through the same route as the corresponding data cell has passed. The present invention is characterized in that, upon receiving the cell collision signal, the buffer control section retransmits the same data cell as the invalidated data cell at the next cell transmission timing.

[Effect]

Since the wideband digital switching device according to the present invention is configured as described above, even if data cells collide in the switch elements in the sorting network, the cell collision signal will not allow the data cells invalidated by the collision to pass through. The invalidated data cells are retransmitted by being applied to the buffer control unit of the corresponding input channel in the opposite direction along the same route as the invalid data cell.

〔Example〕

DESCRIPTION OF THE PREFERRED EMBODIMENTS A broadband digital switching device according to an embodiment of the present invention will be described below with reference to FIGS. 1 to 3 of the accompanying drawings.

As shown in FIG. 1, a sorting network 101 such as a buncher network and a routing network 102 such as a banyan network are cascaded between the input channels 11 to 1 and the output channels n''Cf1 to U. The connected switch network 00 is connected.Input cover memories 1031 to 103 capable of storing a predetermined amount of data cells are provided in front of the sorting network 10, corresponding to each input channel 1 to Io.
n, and a buffer control unit 10 that performs input/output control of data cells to and from the input buffer memories 1031 to 103n.
41 to 104□ are provided.

FIG. 2 shows the data format of the data cell employed in this broadband digital switching device. As shown in the figure, the data cell consists of a fixed length cell of a predetermined number of bits, and an address, which is destination data, consisting of a 1-bit idle/busy identification bit is added at the beginning. The blockage identification bit and the address constitute a header part, and the part of the cell other than the header part is an information field in which information is arranged.

The routing network 102 is a network that guides data cells to output ports 01 to Oo in accordance with the addresses of the data cells, and is composed of, for example, a Banyan network consisting of multiple stages of switch elements. On the other hand, the sorting network 101 is a network that arranges data cells so that the data cells do not arrive at the same input terminal of the routing network 102.
In this embodiment, in addition to a switch element through which data cells are sent out, there is also a route control means S that detects data cell collisions and sends out a cell collision signal, and a route control means S that controls the sending route of this cell collision signal. Since there is a means for creating a cell collision signal route, this will be explained with reference to FIG.

FIG. 3 shows an example of a switch block 4 corresponding to one switch element in FIG. 4. This switch block 4 includes a first switch 41 that controls the passage route of data cells, and a second switch that serves as a path for cell collision signals from further downstream (the side where data cells flow is defined as downstream). 42 and these switch elements 41.4
2, a controller 43 that performs switching control, collision detection, and output of a cell collision signal; shift registers 44 and 45 that are used together with the controller 43 to control routes of data cells and cell collision signals; and a cell collision signal output from the controller 43. OR gates 46 and 47 that create a logical sum between the cell collision signal and the cell collision signal sent through the switch 42
is provided.

Switches 41 and 42 are switched in exactly the same manner by a switch control signal S output from controller 43. Assuming that the data cell reaches the switch block 41 via several switch blocks 4,
A second switch 4 in the same switch block 4 through which the data cell passed from this switch block 41
2 has been created, and the cell collision signal can be sent from the switch block 41 to the same input channel as the input channel to which the data cell is input.

The controller 43 detects the beginning of the data cell arriving from the two input channels based on the cell sending timing signal P and the bit clock CLK (these are generated by a clock generation circuit not shown), and starts from this beginning. The address of the predetermined bit (the bit used for route switching by the relevant switch 41.42) is transferred to the shift register 44.45.
The data cells are taken in from the switch 41 and the data cells are sent out from the switch 41 by switching the switches 41 and 42. Here, the two arriving data cells are both valid (if the blockage identification bit is set to "
1") and the address that is the destination data indicates the same output end of the switch 41, for example, the data cell proceeding diagonally is passed as valid, and the empty/busy identification bit of the other data cell is passed. is changed to a bit indicating invalidity (for example, "0") and passed. Furthermore, at this time, the controller 43 sends a cell collision signal (TA or TB),
When the data cell of input A is invalidated, it is assumed to be TA, and when the data cell of input B is invalidated, it is assumed to be TB. ) is sent.

As a result, the cell collision signal reaches the input channel to which the invalidated data cell was input via the switch block of the arrival route of the data cell, and is applied to the corresponding buffer control section 3. Note that if one of the two data cells arriving at the switch block 4 is invalid, the switch 41 .
42 switchings are performed.

In this way, when receiving a cell collision signal that is returned in the opposite direction that the invalidated data cell followed, the buffer control unit 3 reads out the corresponding data cell from the buffer memory 2 at the next cell sending timing and retransmits it. . This operation continues until the cell control signal is no longer applied. However, although the buffer control unit 3 controls the input buffer memory 4 on a first-in-first-out (F I FO) basis, if an overflow occurs while repeating the above-mentioned retransmission, the data cells related to this retransmission are discarded. When the cell collision signal is no longer applied, the buffer control unit 3 reads the next data cell from the input buffer memory 4 and sends it out at the cell sending timing.

The present invention is not limited to the above embodiments, and various modifications are possible.

For example, sorting network 101, routing network 102
is not limited to the Batcher network or Banyan network of the embodiment, but any network having similar functions may be used.

Further, the input buffer memory 4 and the buffer control unit 3 do not need to be provided for each channel, and for example, the data of all input channels may be stored and sent out at once.

〔Effect of the invention〕

As explained in detail above, according to the present invention, since the switching network is configured by cascading a sorting network and a routing network, data cells are basically aligned at the input of the routing network, and the routing network In addition to avoiding collisions within the sorting network, even if data cells collide in the switching elements in the preceding stage sorting network,
A cell collision signal is applied to the buffer control unit in the opposite direction along the same route as the data cell invalidated by the collision, and the corresponding data cell is retransmitted. It is possible that a collision will occur again during retransmission, but considering the high data transmission speed, for example, in the case of a voice call, the probability that valid data cells will be sent consecutively is small. , the data cell discard rate can be reduced and proper data transmission can be guaranteed.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a broadband digital switching device according to an embodiment of the present invention, FIG. 2 is a diagram showing the format of a data cell used in an embodiment of the present invention, and FIG. 3 is a diagram showing an embodiment of the present invention. FIG. 4 is a diagram illustrating the main part of the broadband digital switching device according to the example, and is a diagram showing collisions of data cells in a switch network in which a sorting network and a routing network are connected in cascade. 4... Switch block, 41.42... Switch, 43... Controller, 44.45... Shift register, 100... Switch network, 101... Sorting network, 102... Routing network , 1031-1
03...Input buffer memory, 1041-104
...Buffer control section. Group-1 Sat! --- To...dar--cell (fixed length) Figure 2

Claims (1)

[Scope of Claims] A switch network in which a sorting network and a routing network are connected in cascade between a plurality of input channels and output channels; an input buffer memory provided in a preceding stage of the plurality of input channels; A wideband digital switching device comprising a buffer control unit that controls input/output of data cells to and from a buffer memory, wherein the sorting network receives data cells to which incoming destination data and identification data indicating validity/invalidity of the data are added; A multi-stage switch element switches the route based on the destination data attached to the data cell and sends it to the corresponding output terminal, and each switch element detects the arrival of a data cell aiming at the same output terminal. one of the data cells is made valid and sent to a corresponding route, and the other data cell is made invalid and sent to a different route from the corresponding route;
and a route control means for transmitting a cell collision signal; and a cell collision signal route for creating a route for transmitting the cell collision signal to a buffer control unit by traveling the same route through which the corresponding data cell has passed in the opposite direction. creating means, and when the buffer control section receives a cell collision signal, it retransmits the same data cell as the invalidated data cell at the next cell transmission timing.