JPH0493065A - Structure of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent a title device from interfering with a wiring layer without increasing processes by simultaneously forming a barrier metal layer held between an electrode for holding a ferroelectric film and a wiring layer, a barrier metal layer held between a region other than said electrode and the wiring layer. CONSTITUTION:There are formed on a P type Si substrate an insulating film 102 for device isolation, and an N type diffusion layer 103, an N type diffusion layer 104, a gate electrode 105, a first interlayer insulating film 106, an electrode 108, a ferroelectric film 107, an electrode 109, and a second interlayer insulating film 110, and thereafter a connection hole is formed. Then, a barrier metal layer 111 is formed. A wiring layer 112 is formed and a metal layer 111 and a wiring layer 112 are formed simultaneously into a predetermined pattern by photoetching, to yield a semiconductor device. With this process, there can be formed simultaneously a metal layer 11 to be held between the electrode 109 and the wiring layer 112 and a metal layer 113 to be held between a region 104 other than said electrodes and a wiring layer 114, and hence an interaction between the electrode 109 and the wiring layer 112 and an interaction between the region 104 and the wiring layer 114 can be prevented without increasing additional processes.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention provides a memo! using ferroelectric material. The present invention particularly relates to the structure and manufacturing method of electrically rewritable nonvolatile memory.

[Summary of the Invention] The present invention provides a method for manufacturing a memory using a ferroelectric film, in which a ferroelectric film is sandwiched between electrodes formed to sandwich the ferroelectric film and a wiring layer connected to the electrodes. By simultaneously forming the barrier metal layer to be formed and the barrier metal layer to be sandwiched between the region other than the electrode and the wiring layer connected to the region, the process can be shortened.

F Prior Art] As a conventional semiconductor non-volatile memory, an MIS type transistor uses a phenomenon in which the surface potential of a silicon substrate is modulated by injecting charge from the silicon substrate into a trap or floating gate in an insulated gate. is commonly used and has been put into practical use as EPROM (ultraviolet erasable nonvolatile memory) and EEPROM (electrically rewritable nonvolatile memory).

[Problems to be Solved by the Invention] However, in these nonvolatile memories, the voltage for rewriting information is usually high, around 20 V, and the rewriting time is extremely long (for example, in the case of EEPROM, it takes several tens of msec).
c,), etc. Further, the number of times information is rewritten is about 102 times, which is very small, and there are many problems when using it repeatedly.

For nonvolatile memory that uses ferroelectric materials whose polarization can be electrically reversed, the write time and read time are basically the same, and the polarization is maintained even when the power is turned off. , has the potential to become an ideal nonvolatile memory. Regarding non-volatile memories using such ferroelectric materials, for example, there are structures in which ferroelectric capacitors are integrated on a silicon substrate as in U.S. Pat. No. 4,149,302, and M I S type transistors as in U.S. Pat. Proposals have been made for non-volatile memories in which a ferroelectric film is placed on the gate portion of the device. Recently, a non-volatile memory having a structure stacked on an MO3 type semiconductor device as shown in Fig. 2 has been published in IEDM' 87pp, 850-851.
has been proposed.

In FIG. 2, (201) is a P-type Si substrate,
(202,) is a LOCO3 oxide film for element isolation, (2
03) is an N-type diffusion layer that becomes a source, and (204) is an N-type diffusion layer that becomes a drain.

(205) is a gate electrode, and (206) is an interlayer insulating film. (, 207 is the ferroelectric film, and the electrode (2
08> and (209), forming a capacitor. (210) is the second interlayer insulating film, (21
1) is A] which becomes a wiring electrode.

In this structure stacked on top of the MO8 type semiconductor device, the wiring between the electrode of the ferroelectric film and the high concentration diffusion layer which becomes the source and drain on the semiconductor substrate is made using A1 etc. as shown in Figure 3. must be done. When a semiconductor device with such a structure is subjected to heat treatment, an interaction occurs between the wiring layer such as AI and the high concentration diffusion layer that becomes the source and drain, and at the same time, the wiring layer such as A1 and the ferroelectric film There is also a problem that mutual reactions occur between the electrodes and the electrodes that sandwich them, and both deteriorate the device characteristics. Therefore, the present invention is intended to solve these problems, and its purpose is to form a barrier metal layer that prevents the two-speed mutual reaction in the same process, thereby creating an excellent semiconductor using ferroelectric material. The purpose is to provide devices, especially nonvolatile memory, at low cost.

[Means for Solving the Problems] A semiconductor device of the present invention has a ferroelectric film integrated on the same semiconductor substrate on which active elements are formed via electrodes formed to sandwich the ferroelectric film. The semiconductor device includes a barrier metal layer sandwiched between electrodes formed to sandwich the ferroelectric film and a wiring layer connected to the electrodes, and the method for manufacturing the semiconductor device, further comprising: A barrier metal layer to be sandwiched between an electrode formed to sandwich a ferroelectric film and a wiring layer connected to the electrode, and between a region other than the electrode and a wiring layer connected to that region. The method is characterized in that it includes a step of simultaneously forming a barrier metal layer to be sandwiched between the two layers.

[Embodiment] FIGS. 1(a) to 1(d) are sectional views of main steps in an embodiment of the semiconductor device of the present invention. The semiconductor device of the present invention will be described below with reference to FIG. Here, for convenience of explanation, an example using a Si substrate and an N-channel transistor will be described.

(Figure 1(a)) (101) is a P-type Si substrate, for example, 2゜Ω・cm
A wafer with a specific resistance of (102) is an insulating film for element isolation, and for example, an oxide film with a thickness of 600 OA is formed by the conventional LOCO3 method. (103) is an N-type diffusion layer that becomes a source, and for example, phosphorus at 80keV5x
It is formed by implanting l○I5c m -2 ions. (104) is an N-type diffusion layer that becomes a drain,
(103) is formed simultaneously. <105,) is a gate electrode, for example, made of polysilicon doped with phosphorus. (, l 06 ) is the first interlayer insulating film, for example, 4000 phosphorus glass is formed by chemical vapor deposition.
Form A.

(108) is one electrode sandwiching the ferroelectric film, and is made of, for example, PT with a thickness of 100 OA by sputtering. (1
07) is a ferroelectric film, and 2000 layers of PbTiO3 are formed by sputtering, for example. (109) is the other electrode sandwiching the ferroelectric film, and is formed in the same manner as (108). (110) is the second interlayer insulating film, for example, 4000 phosphorus glass is formed by chemical vapor deposition.
After the formation, connection holes are formed by photo-etching, which is a conventional technique.

(FIG. 1(b)) (111) is a barrier metal layer according to the gist of the present invention, and 500 layers of TiN are formed by, for example, a sputtering method. At this time, it is desirable to cause TiN to contain oxygen by sputtering in an atmosphere containing oxygen.

(FIG. 1(C)) (112) is a wiring layer, and for example, 5000 layers A1 are formed by sputtering.

(Fig. 1 (d)) The barrier metal layer (111) and the wiring layer (112) are simultaneously formed into a predetermined pattern by photo-etching,
A semiconductor device according to an embodiment of the present invention is obtained.

By performing the process as shown in FIG. 1, the electrode (109) sandwiching the ferroelectric film and the wiring M (109) connected to the electrode are formed.
12) Barrier metal layer (111) to be sandwiched between
, and a region other than the electrode (here, the drain region (1
04)) and the barrier metal layer (113) to be sandwiched between the wiring layer (114) connected to the region can be formed simultaneously, and the ferroelectric film can be formed without increasing the number of steps. Interaction between the sandwiching electrode (109) and the wiring layer (112) connected to said electrode, and the drain region (10
4,) and the wiring layer (104) connected to the drain region (104).
114) can be prevented.

Now, in Figure 1, (' 111 ) and (11
If there is no barrier metal in 3), heat treatment at 500°C will destroy the PN junction in the source and drain regions, and further reduce the hysteresis of the ferroelectric capacitor consisting of (107), (108), and (109). Is it missing? )
(In other words, the ferroelectricity was lost), and the dielectric constant was 20, which was 500 before the heat treatment. On the contrary,
According to the example of the present invention, the above change did not occur even after heat treatment at 600'C.

Although the above description has mainly been about non-volatile memories, it goes without saying that the present invention can also be applied to memories (such as DRAM) that use ferroelectric materials having a high dielectric constant.

[Effect of the Invention J] The present invention provides a barrier metal layer to be sandwiched between electrodes sandwiching a ferroelectric film and a wiring layer connected to the iti, and a region other than the electrode and a region connected to the region. Since the barrier metal layer to be sandwiched between the wiring layer and the wiring layer to be connected is formed at the same time, the interconnection layer between the electrode sandwiching the ferroelectric film and the wiring layer connected to the electrode can be easily formed without increasing the number of steps. This makes it possible to prevent reactions and mutual reactions between the drain region and the wiring layer connected to the train region, and has the effect that a semiconductor device with excellent heat resistance can be manufactured at low cost.

[Brief explanation of drawings]

FIGS. 1(a) to 1(d) are cross-sectional views of main steps of a semiconductor device according to an embodiment of the present invention. FIG. 2 is a main cross-sectional view of a semiconductor memory device according to the prior art. 101・ 102・ 103・ 104・ 105・ 107・ 108・ 109・ 110・ 111.113・ 112.114・・ 201・ 202・ 203・ 204・ 205・ 206・ 207・・・Silicon substrate/element isolation Film, source region, drain region Gate electrode, first interlayer insulating film, ferroelectric film, lower electrode, upper electrode, second interlayer insulating film, barrier metal layer... wiring layer, silicon substrate, element isolation film, Source region, drain region, gate electrode, first interlayer insulating film, ferroelectric film

Claims (4)

[Claims] (1) In a semiconductor device in which a ferroelectric film is integrated on the same semiconductor substrate on which active elements are formed via electrodes formed to sandwich the ferroelectric film, 1. A structure of a semiconductor device comprising a barrier metal layer sandwiched between an electrode formed on the semiconductor device and a wiring layer connected to the electrode. (2) electrodes formed to sandwich the ferroelectric film;
simultaneously forming a barrier metal layer to be sandwiched between a wiring layer connected to the electrode and a barrier metal layer to be sandwiched between a region other than the electrode and a wiring layer connected to that region; 2. The method of manufacturing a semiconductor device according to claim 1, further comprising the step of: (3) The barrier metal layer is made of titanium nitride (hereinafter referred to as TiN).
Claim (1) characterized in that the main component is
Structure of the described semiconductor device. (4) The structure of the semiconductor device according to claim (1), wherein the barrier metal layer containing TiN as a main component contains oxygen.