JPH0488658A - Semiconductor device and its manufacturing method - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Summary] Regarding an isolation structure between elements of a semiconductor device, in particular, an isolation structure between elements that enables high integration and high breakdown voltage of a semiconductor device, an isolation region between elements is located inside an integrated circuit device. The purpose is to provide a highly integrated semiconductor device in which the area occupied by the semiconductor device can be minimized and the component elements can be brought close to the limit of photolithography. A semiconductor layer grown in a vapor phase from the semiconductor base substrate was formed as an element region in a region surrounded by an insulator side wall on an insulating film having an opening exposing the semiconductor layer.

Further, a step of forming a first insulating film on a semiconductor base substrate, a step of photo-notching the first insulating film to form an insulator side wall surrounding the element region, and a step of forming a side wall of the insulator surrounding the element region. forming a second insulating film on the surface of the etched region; opening a part of the second insulating film by photoetching to expose the surface of the semiconductor base substrate; The structure includes a step of forming an element region by vapor phase growth using the exposed surface of the element as a nucleus.

[Industrial Field of Application] The present invention relates to an isolation structure between elements of a semiconductor device, and particularly to an isolation structure between elements that allows for higher integration and higher breakdown voltage of a semiconductor device.

In recent years, semiconductor devices have become more highly integrated, and in addition to reducing the size of the elements that make up these devices, there is also a strong demand for improving the isolation structure between elements to shorten the distance between adjacent elements. There is.

[Prior art and its problems]

Conventionally, several structures for isolating elements constituting a semiconductor device have been put into practical use.

The main ones will be explained below.

(1) Element isolation structure using LOGO3 insulating film FIG. 5 shows a cross-sectional view of a conventional element isolation structure using LOGO3 insulating film.

In this figure, 41 is a semiconductor substrate, 42 is a source, and 4
3 is a drain, 44 is a gate insulating film, 45 is a gate electrode, 46 is a LOGO3 insulating film, and 47 is a channel cut.

According to this isolation structure, elements can be effectively isolated by the thick LOCO3 insulating film 46;
A lattice defect occurs at the so-called bird's beak at the tip of the O3 insulating film 46 due to the difference in thermal properties between the semiconductor substrate 41 and the LOCO3 insulating film 46, and LOCO3! Since a width comparable to that of a nickname is required to form the edge film 46, there is a problem in that it hinders high integration.

(2) Inter-element isolation structure using trenches FIG. 6 shows a cross-sectional view of a conventional element isolation structure using trenches.

In this figure, 48 is a trench filled with an insulator, and the other parts are the same as those described with the same reference numerals in FIG.

According to this isolation structure, it is possible to achieve high integration by reducing the width of the trench 48, but on the other hand,
When the aspect ratio is increased, there are problems in that it becomes difficult to clean the inside of the trench 48 during the manufacturing process, and that lattice defects due to thermal stress are likely to occur at the lower edge of the trench 4B. .

(3) Device isolation structure by epitaxially growing a semiconductor layer from a semiconductor base substrate through an opening in a LOGO3 insulating film Figure 7 shows a conventional device isolation structure by epitaxially growing a semiconductor layer from a semiconductor substrate through an opening in a LOCO3 insulating film. A cross-sectional view of the structure is shown.

In this figure, 49 is a LOCO3 insulating film, and 50 is an insulator side wall, and is the same as that described with the same reference numerals in FIG. 5.

According to this isolation structure, the source 42 and drain 43 can be formed above the LOCO3 insulating Wl 149, so the degree of integration can be increased, but a conventional LOGO3 insulating film using a thermal oxidation process is also used. Therefore, the manufacturing time is long, and lattice defects are likely to occur at the edges of the LOCO3 insulating film due to the difference in thermal expansion coefficient between the semiconductor and the insulating film, which may adversely affect the epitaxial layer. Furthermore, there is a problem in that the bird's beak becomes a hindrance to high integration.

[Problems to be Solved by the Invention] The present invention eliminates the problems of the above-mentioned prior art, minimizes the area ratio occupied by the element isolation region in the integrated circuit device, and forms the constituent elements within the limits of photolithography. It is an object of the present invention to provide a highly integrated semiconductor device that can be brought close to the conventional semiconductor device.

[Means for Solving the Problems] In a semiconductor device according to the present invention, an insulator sidewall on an insulating film formed on a semiconductor base substrate and having an opening partially exposing the surface of the semiconductor base substrate A structure was adopted in which a semiconductor layer grown in a vapor phase from the semiconductor base substrate was formed in the surrounded region as an element region.

The method for manufacturing a semiconductor device according to the present invention also includes a step of forming a first insulating film on a semiconductor base substrate, and photo-etching the first insulating film to form an insulator side wall surrounding an element region. forming a second insulating film on the surface of the region surrounded by the insulator sidewall; and opening a part of the second insulating film by photoetching to form a second insulating film on the surface of the semiconductor base substrate. A process of exposing the surface and a process of forming an element region by vapor phase growth using the exposed surface of the semiconductor base substrate as a nucleus were adopted.

(Function) When an element region is constituted by a semiconductor layer grown on an insulating film in a region surrounded by insulating side walls as in the present invention, each element has a structure floating in the insulating film. Since the sidewalls are formed by photo-etching the insulating layer, isolation between elements can be achieved with the minimum required separation layer area, which greatly contributes to higher integration of semiconductor devices.

Furthermore, if a semiconductor layer is grown after preliminary formation of insulator side walls for element isolation, the element region will not be damaged by the process for element isolation.

(Example〕 Embodiments of the present invention will be described below based on the drawings.

(First Embodiment) Figures 1 (1) to (6) are manufacturing process diagrams of the first embodiment of the present invention.

In the figure, ■ is a P-type Si base substrate, and 2 is S for thick side walls.
3 is a growth mask Sing, 4 is an opening, 5 is a Si vapor phase growth layer, 6 is a source, 7 is a drain, 8 is a gate insulating film, and 9 is a gate.

The manufacturing process will be explained with reference to FIG.

Figure 1 (1) (CVDS io□ growth) Specific resistance is 10Ω
- St0.cm for sidewalls is formed on the p-type Si base substrate 1 with the crystal plane (100) facing upward by the CVD method. membrane 2 to 3
Deposited to a thickness of 000 people.

FIG. 1(2) (Patterning of SiOx film) The SiOx film 2 is patterned by photoetching, and SiOx film 2 for sidewalls is placed in a position surrounding the future device region. A film 2 is formed.

Figure 1 (3) (Thermal oxidation) Thermal oxidation creates a thickness of 1000 mm in the area that will become the element area in the future.
A 5IOZ film 3 for a growth mask of approximately 0.05 cm is formed.

Note that it is preferable to inject B for channel cutting under the SiOz film.

FIG. 1 (4) (Anisotropic Etching) A part of the SiO□ film 3 is removed by anisotropic etching to form an opening 4, and the (100) single crystal of the semiconductor base substrate 1, which becomes the seed for epitaxial growth, is removed. Expose the plane.

FIG. 1(5) (Vapor phase growth of Si layer) A Si layer 5 having a thickness of approximately 3000 layers is grown in a vapor phase within the insulator side wall 2. As shown in FIG.

As a result of this growth, single crystal Si is formed on the single crystal exposed plane.
The polycrystalline Si layer grows on the SiO□ film 3.

The vapor phase growth of this Si layer is performed using 5 to 6 to of 5iHCj23.
This can be done by using a reduced pressure atmosphere of rr and maintaining the M plate temperature at 1000°C.

In addition, instead of directly growing a single crystal, the semiconductor substrate is maintained at 400 to 500 ''C and a low-pressure vapor phase growth method is used to thermally decompose Si HCj23 to form amorphous silicon. Or, the semiconductor substrate is 500~600'
After forming polycrystalline silicon while maintaining the temperature at C, a high temperature heat treatment of about 1150°C may be applied to form a single crystal.

FIG. 1 (6) (Device Formation) On this Si layer 5, a source 6, a drain 7, a gate insulating film 8, and a gate 9 are formed using a conventionally known manufacturing process, and wiring is performed to form an MO3FET integrated circuit. complete.

Incidentally, at this time, if the edge portions 3a and 3b are given a 90-degree angle, the effect will be great.

(2) Second Embodiment FIGS. 2(1) to 2(3) are manufacturing process diagrams of a second embodiment of the present invention.

In this figure, 11 is a P-type Si base substrate, 12 is a Si
o, ll*, 13 is Si3N, film, 14 is SiO for side wall
□Membrane 15 is an opening.

The manufacturing process will be explained with reference to FIG.

Figure 2 (1) (S i Oz @, S L3 Na
Formation of M, Si02 film) After forming SrOz W#12 to a thickness of 1000 mm on the p-type Si base substrate 11 by thermal oxidation or CVD, a Si, Na film 13 is formed by CVD to a thickness of 500 mm. Form to the thickness of a person.

Then, a sidewall SiO□ film 14 is formed thereon to a thickness of 3000 mm by the CVD method.

FIG. 2(2) (Battering of SiO□ film) The SiO□ film 14 is selectively patterned by etching to form isolation insulator side walls 14 so as to surround the device region.

At this time, S ia Na 11113 acts as an etching stopper.

Figure 2 (3) (Buttering of Si3N film and SiO□ film) Selectively etching a part of the Si3N film 13 and SiO□ film 12 to form a single crystal of the semiconductor substrate that will become the seed for epitaxial growth. An opening L5 is formed in which the plane surface is exposed.

Thereafter, a Si layer with a thickness of 3,000 wafers is grown in a vapor phase within the side wall 14, and a source, a drain, a gate insulating film, and a gate are formed thereon using appropriate conventional manufacturing processes to form an MO.
Completing the 3FET integrated circuit is the same as in the first embodiment.

(3) Third Embodiment FIGS. 3(1) to 3(3) are manufacturing process diagrams of a third embodiment of the present invention.

In this figure, 21 is a p-type Si base substrate, 22 is a thick SiO□ film, and 23 is an opening.

The manufacturing process will be explained with reference to FIG.

FIG. 3 (1) (Formation of 310! film) Thick SiO□y22 is deposited on P-type Si base substrate 21 by CVD
It is formed to a thickness of about 4,000 by the method.

Figure 3 (2) (First stage photoetching of SiO□ film) S i 02 M22 was etched by about 3000 people, leaving a thin 5in2 film, and an insulator for isolation was placed in a shape surrounding the element area. A side wall 22 is formed.

FIG. 3 (3) (Second-stage photoetching of SiO□ film) A part of the thin Sin film left by the first-stage photoetching described above is removed by anisotropic etching to form an opening 23. , the (100) single crystal plane of the semiconductor base substrate 1, which will become the seed for epitaxial growth, is exposed.

The subsequent steps are similar to those described in FIG.

(4) Fourth Embodiment FIGS. 4(1) to 4(6) are manufacturing process diagrams of a fourth embodiment of the present invention.

In this figure, 31 is a Si base substrate, 32 is a capacitor hole, 33 is a capacitor dielectric film, and 34 is a polycrystalline silicon substrate.
i layer, 35 is SiO□ film, 36 is Si3N4 film, 37 is Sin film, 3rd and 39 are both open, 40 is Si layer,
41 is a source, 42 is a drain, 43 is a gate insulating film,
44 is a gate.

The manufacturing process will be explained with reference to FIG.

Figure 4 (1) (Etching of capacitor hole) CC
A capacitor hole 32 having a diameter of 1.5 μm and a depth of 2 μm is formed by reactive ion etching (RIE) using a chlorine gas such as No. 1.

FIG. 4 (2) (Formation of capacitor dielectric film) The Si base substrate 31 is heated to 900°C to form a thermal oxide film (SiO□) with a thickness of 50 μm, and on top of that, by CVD method. S
x:=A 12 nm thick Na film is laminated, and on top of that, 90 nm
The surface is oxidized by annealing in an oxygen atmosphere for 30 minutes at 0'C to form a capacitor dielectric film 33.

Next, a polycrystalline Si layer 34 containing As, which will become a capacitor electrode, is deposited by CVD to fill the capacitor hole 32.

FIG. 4(3) (Formation of capacitor electrode) Impurity-containing polycrystalline Si existing in areas other than the buried layer is removed by plasma etching using CFa to form a capacitor electrode.

The etching stopper in this case is the capacitor dielectric film (SiO□/Si3N a /S
i O□)33 fulfills the role.

Figure 4 (4) (Formation of growth mask and sidewalls) CV on the entire surface
1000 SiO□ films 35 are stacked by the D method, a Si3N4 film 36 is formed on top of it by the CVD method, and a thick SiO2) 11 (
form 37.

Then, this SiO□ film 37 is patterned to form device side walls 37.

In this case, the Si3N4 film 36 serves as an etching stopper.

FIG. 4 (5) (Vapor phase growth of Si layer) An opening 38 on the Si base substrate 31 for use as a seed for single crystal growth, and an opening for drawing out the electrode from the polycrystalline Si that will become the electrode of the capacitor. After forming the Si layer 39, a Si layer 40 is grown in a vapor phase.

A single crystal grows above the opening 38, and a polycrystalline layer grows near the top of the opening 39.

FIG. 4(6) (Formation of device) A conventionally known manufacturing process is applied to the Si layer 40 to form a source 41.
, a drain 42, a gate insulating film 43, and a gate 44 are formed, and an electrode of a capacitor 45 is connected to the drain 42 to realize a DRAM memory cell.

In addition to what has been explained in the above embodiments, an 0MO3 structure can be realized by changing the conductivity type in adjacent device regions, and when a semiconductor layer is grown in a device region surrounded by insulator sidewalls. Since a single crystal grows in other parts, a bipolar transistor can also be formed in this part.

[Effects of the Invention] According to the configuration of the present invention, since the sidewalls of the insulator are patterned by photoetching, isolation between elements is possible with the minimum area of the sidewall for isolation, and the area near the opening of the growth mask is Since the growth layer of is epitaxially grown using the semiconductor base substrate as a seed, the crystallinity is good at least in the region where the channel region is formed, and there are no sharp edges where the semiconductor layer and the insulator layer contact. There is less risk of crystal defects occurring due to mismatching of thermal properties between layers and insulator layers, and crystals are not damaged during the process of forming isolation structures, making it possible to increase the integration of semiconductor devices. There is a lot to contribute.

[Brief explanation of drawings]

Figures 1 (1) to (6) are manufacturing process diagrams of the first embodiment of the present invention, Figures 2 (1) to (3) are manufacturing process diagrams of the second embodiment of the invention, and Figure 3 ( 1) to (3) are manufacturing process diagrams of the third embodiment of the present invention, Figures 4 (1) to (6) are manufacturing process diagrams of the fourth embodiment of the present invention, and Figure 5 is the conventional LOGO3 insulation FIG. 6 is a cross-sectional view of a conventional trench-based isolation structure, and FIG. 7 is a conventional LO
1 is a cross-sectional view of an element isolation structure formed by epitaxially growing a semiconductor layer from a semiconductor substrate through an opening in a CO8 insulating film. 1-P-type Si base substrate, 2-SiO□ film for thick sidewalls, 3
- SiO□ for growth mask, 4- Opening, 5 Si vapor phase growth layer, 6- Source, 7- Drain, 8- Gate insulating film, 9- Gate, l l-p type Si base Substrate, 12-・-3iO, WiI, 13-5i, N4
Membrane, 14--5iO7 membrane for side wall, 15... Opening, 2
1--p-type Si base substrate, 22--thick SiO□ film, 23 opening, 31--Si base substrate, 32--capacitor hole, 33--capacitor dielectric film, 34--polycrystalline Si, 35 -3 i OZ film, 36-'-3j 3 N
4 tli. 37-...SiO□ film, 38.39...Opening, 40-
- Si layer, 41...source, 42...drain,
43--Gate insulating film, 44--Gate patent applicant Fujitsu Ltd. Representative Patent Attorney Shoji Aiya

Claims (8)

[Claims] (1) Vapor phase growth from the semiconductor base substrate onto a region surrounded by an insulator side wall on an insulating film formed on a semiconductor base substrate and having an opening partially exposing the surface of the semiconductor base substrate. 1. A semiconductor device characterized in that an element region is formed by a semiconductor layer formed by applying a semiconductor layer. (2) The element region according to claim 1 has a source region and a drain region that are electrically insulated from the base substrate, and wiring connected to both regions, and further includes a layer on the growth layer above the opening. 1. A semiconductor device comprising a MOSFET comprising a gate insulating film in contact with a gate insulating film and a gate electrode formed on the gate insulating film. (3) MOSFET in the element region according to claim 1;
A semiconductor device characterized in that a charge storage capacitor connected to its drain is arranged. (4) A semiconductor device characterized in that a CMOS structure is constituted by MOSFETs formed in adjacent element regions according to claim 1. (5) The element formed in the element region according to claim 1 is
A semiconductor device characterized in that the semiconductor device is connected to a bipolar transistor formed outside an insulator side wall surrounding the element region. (6) a step of forming a first insulating film on a semiconductor base substrate; a step of photo-etching the first insulating film to form an insulator side wall surrounding the element region; forming a second insulating film on the surface of the surrounded region; opening a part of the second insulating film by photo-etching to expose the surface of the semiconductor base substrate; 1. A method of manufacturing a semiconductor device, comprising the step of forming an element region by vapor phase growth using an exposed surface of a substrate as a core. (7) a step of forming a first and a second insulating film in this order on a semiconductor base substrate; a step of photo-etching the second insulating film to form an insulator side wall surrounding the element region; opening a part of the first insulating film by photoetching to expose the surface of the semiconductor base substrate;
A method for manufacturing a semiconductor device, comprising the step of forming an element region by vapor phase growth using the exposed surface of the semiconductor base substrate as a nucleus. (8) a step of forming a thick insulating film on a semiconductor base substrate; a step of photo-etching the insulating film with a thin insulating film left at the bottom thereof to form an insulator side wall surrounding the element region; A step of opening a portion of the thin insulating film left in the process by photo-etching to expose the surface of the semiconductor base substrate, and forming an element region by vapor phase growth using the exposed surface of the semiconductor base substrate as a core. 1. A method for manufacturing a semiconductor device, comprising the step of: