JPH0488572A - Picture processor - Google Patents

Abstract

PURPOSE:To reproduce high-quality pictures by synthesizing a picture data, which is generated from a compressed picture data, and a picture data generated from a high frequency picture data, and editing the compressed picture data. CONSTITUTION:A PDL interpreter (PDLP) 2 decides a picture part to be changed by a PDL command and whether the picture to be changed is a character/drawing or not. In the case of the character/drawing, the relevant part of a character/drawing memory 10 is overwritten. In the other case, when the PDLP 2 receives the command, the data of a block raster including the picture part to be changed by the command are read from a compression memory 5 and decoded, and the decoded data are simultaneously outputted to a synthesizer 3. The PDLP 2 controls the synthesizer 3 and the decoded data are inputted and stored in a buffer. The PDLP 2 overwrites new data to be generated by the command in a certain area corresponding to the picture element position of the block raster completely fetching the decoded data. Afterwards, the relevant block raster area is compressed again, and the data are stored in the relevant position of the compression memory 5 again.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an image processing device that performs image compression processing on image data.

[Conventional technology]

Image recording devices include, for example, thermal printers and inkjet printers. Conventionally, laser beam printers have mainly been recording terminals, that is, white/white printers with bitmap memory.
It was used as a black printer. However, in recent years, with the increase in the capacity of semiconductor memories, the development of high-performance LSIs, and advances in computer technology, the use of full-color images for high-definition recording is increasing.

On the other hand, there is an increasing demand for capturing color natural image data into a computer and performing various processing and image communication. One of the encoding methods for this purpose is a variable length encoding method called the ADCT method,
．． 18 Na6 pp398-407.

When this ADCT method is used as the image memory of the above-mentioned image recording device, full-color natural images can be produced 1/10 to 1/20 times as much as normal original data (uncompressed data).
This is extremely beneficial as it only requires a memory capacity of 1,000 yen, making it possible to significantly reduce the overall cost of the recording device.

On the other hand, when used as a recording device connected to a computer, it is common to use a standardized page description language (PDL) to ensure data compatibility between different recording devices. This is intended to make printers or computers of different specifications from different companies compatible through a common language, and to eliminate the disadvantage that only specific computers and specific printers can be connected. Examples of such a description language include Po5t 5script.

[Problem that the invention is trying to solve]

When such a PDL is used on the compressed memory mentioned above, the PDL itself is created with the concept of override (that is, the concept of overwriting new data on old underlying data), There are problems with the following points.

1) The block in which images are combined within the 8×8 block of ADCT needs to be updated with new code data.

2) If the compression method is variable-length code algebra, and you try to overlap another image data on a certain part of the background image, the address for overlapping is not constant.

3) The total code length of the combined new image data changes depending on the image quality.

4) When decoding → composition (overwriting) → recompression is repeated, image quality deteriorates.

For these reasons, it has been considered difficult to use PDL on compressed memory.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide an image processing device that can eliminate the above drawbacks and perform various image processing using compressed data.

Another object of the present invention is to reproduce high-quality images.

Another object of the present invention is to provide an apparatus suitable for high-speed processing.

[Means and operations for solving the problems] In order to solve the above problems, the image processing device of the present invention includes a first storage unit that holds compressed image data, and a second storage unit that holds high-frequency image data. means for synthesizing image data generated from the data held in the first storage means and image data generated from the data held in the second storage means; and means for editing image data stored in the means.

〔Example〕

FIG. 1(a) is a drawing that best represents the features of the present invention. In the figure, 1 is a host computer that outputs a command string in the PDL language, and 2 is a command string output from the host computer 1. 3 is a synthesizer that combines the underlying data with the image data newly generated by the PDL interpreter 2; 4 is a compressor that performs compression by ADCT; 5 is a compressed data memory that is used by dividing it into blocks for each sufficient amount of memory, 6 is a decoder, and 7 is whether the output of the decoder 6 is output to the synthesizer 3 or the selector 1.
This is a multiplexer that switches output to 1.

8 is a compressed memory address controller that controls reading and writing of compressed data. Reference numeral 9 denotes an empty buffer area management circuit used by the address controller 8 to manage empty areas within the compressed memory 5. 10 is a memory that holds characters and line drawings. Reference numeral 11 denotes a selector that switches between outputting the image output from the decoder 6 via the selector 7 and the image output from the character/line drawing memory 10 to an image forming section or the like of a recording device (not shown). Reference numeral 12 denotes a character/line drawing memory address controller that controls reading/writing of the character/line drawing memory.

When the PDL interpreter 2 receives a Postscript PDL command from the host computer 1, the PDL interpreter 2 determines the part of the image that will be changed by the command and the text and text that will be changed in the image.
Determine whether it is a line drawing. If it is a character/line drawing, the corresponding part of the character/line drawing memory 10 is overwritten. Otherwise, upon receiving a PDL command from the host computer 1, the PDL interpreter 2 determines the image part to be changed by the command, sequentially reads data of the block rask including the relevant part from the compression memory 5,
The decoders of address controllers 8 and 6 are controlled to output decoded data. At the same time, the multiplexer 7 is controlled to output the data decoded by the decoder 6 to the synthesizer 3.

The PDL interpreter 2 also controls the synthesizer 3, inputs decoded data from the decoder 6, and sets the data to be stored in a buffer. The PDL interpreter 2 overwrites the area corresponding to the pixel position of the block rask for which the decoded data has been taken in with new data generated by the above-mentioned command. After writing the data corresponding to the block rask area, the synthesizer 3, compressor 4, and address controller 8 compress the block rask area again in the compressor 4 and store it in the corresponding position of the compression memory 5. control. The above procedure is repeated over all necessary block rusks.

FIG. 1(b) is a diagram showing the configuration of the entire system including the interface section shown in FIG. 1(a) above, where 1 is a host computer, 101 is an interface section shown in FIG. 1(a), and 102 is an output. an output controller that controls signals, 103 a display that displays output images;
4 is a transmitting device for transmitting an output image through a public line or a local area network, 105 is a laser beam printer that irradiates a laser beam onto a photoreceptor to form a latent image, and forms a visible image from this latent image; This is an operation unit through which an operator sets output light and the like in order to output a desired image.

FIG. 2 shows an example of the configuration of the synthesizer shown at 3 in FIG. 1. 21, 22, and 23 each consist of eight raster buffers, each having a capacity to hold decoder data for a block rask. 24 is a selector, which outputs data 27 from the PDL interpreter 2 and signal data 28 decoded by the decoder 6 and input via the selector 7, by a selector controller 26 controlled by the PDL interpreter 2. Based on the output signal 29, each of the 8-line buffers of 21, 22, and 23 mentioned above is independently connected to different 8-line buffers. Similarly, 25 is a selector, which selects and outputs one of the aforementioned 8 line buffers 21, 22, and 23. The selector controller 26 communicates buffer switching timing with the PDL interpreter 2. That is, PDL interpreter 2
When the selector controller 26 sends a request signal indicating that it wants to write data to a new buffer, the selector controller 26 writes 21, 22, and 23 of the 8-line buffer every time a request signal is received.
→22→23→21→... and connect to the signal line group 27 by switching in this order. At the same time 22 → 23 → 21 → 22 →...
・Connect to the signal line group 28 in this order, and then connect the PDL
The data underlying the block rask to be overwritten by the interpreter 2 is decoded and stored. At the same time, the selector 25 is controlled to switch in the order of 23→21→22→23→... to output the data that has been overwritten from the PDL ink interpreter onto the base data to the encoder (compressor) 4. 30 is an address controller, which controls the scanning line synchronization signal (HSYNC) from the decoder and the pixel synchronization signal (PXCLK).
, inputs the data output address from the PDL interpreter, the scanning line synchronization signal from the encoder, and the pixel synchronization signal, and outputs the output address on the corresponding 8-line buffer of the pixel data decoded from the decoder and the data from the PDL interpreter, respectively. An output address on the 8-line buffer of the pixel data to be overwritten and an output address on the 8-line buffer of the pixel data to be output to the encoder are generated, and three sets of each are generated according to the select signal from the selector controller 26. Each of the 8-line buffers is outputted to one of the different 8-line buffers. FIG. 3 shows an example of the configuration of the address controller 30. 31 is a counter that counts the scanning synchronization signal (HSYNC) from the decoder, and 32 is a counter that counts the pixel synchronization signal (PXCL) from the decoder.
K). 32 outputs the count as an address corresponding to the position in the main scanning direction within one scanning line, 31 outputs the count as the upper bit of the address of the first pixel of each scanning line in the raster block, and 31 By using the output of 32 as the upper bit and the output of 32 as the address signal line for the subsequent lower bit, a storage address for the output data from the decoder on the 8-line buffer is generated. Further, the counter 32 is set by a scanning synchronization signal (H3YNC). Similarly, 33 and 34 receive the synchronization signal from the encoder.

The counter 33 receives a scanning synchronization signal (H3YNC) from the encoder.
), the counter 34 counts the pixel synchronization signal (PXCLK) from the encoder, and generates the storage address on the corresponding 8-line buffer for the data to be output to the encoder, as in 31.32. Selector 35.36.3
7 selects an 8-line buffer from 21, 22, and 23 to store the data decoded from the decoder by a select signal from the selector controller 26, and outputs the address generated by the counters 31 and 32. Selector and encoder A selector and an encoder that select from among the 8-line buffers 21, 22, and 23 to output the data held therein by a select signal from the selector controller 26, and output the address generated by the counter 33, 34. This is a selector that selects and outputs an 8-line buffer from 21, 22, and 23 according to a select signal from the selector controller 26, which holds the underlying data to be overwritten with the address signal output from the PDL interpreter.

(The data that has been overwritten on the underlying data is
is transferred to the encoder and compressed. The compressed data is output from the encoder 4 to the compression memory 5 and stored therein.

FIG. 4 shows the storage location of compressed data corresponding to each block rask on the compression memory. For example up to 40
96x4096 pixels, 1 pixel 3 bytes (1 byte/color)
We will be dealing with an image consisting of . This maximum image is 48M
It has a capacity of Byte. Assume that the compression ratio by the encoder 4 is set to 1/12. The block rask is compressed so that each block is composed of 8×8 pixels. Therefore, the maximum size image is composed of 512×512 blocks. The maximum size image is approximately 4MBy
The data is compressed to a capacity of te, and the average code length for each block rask is 8 KB.

In this embodiment, the data amount of the average code length is assumed as the memory capacity for each block rask, and the compressed memory area for each block rask is set for each block rask as shown in FIG.

FIG. 5 expresses the state of data actually held in the compressed memory shown in FIG. 4. Each block in FIG. 5 is the same as the data area of each block rask in FIG. 4, and it is clearly expressed that the compressed memory area for each block rask is set for each average code length. The shaded area indicates the area that actually stores the code for each block rask. In FIG. 5, the 2nd block class, the 4th block class, the 7th block class, the 10th block class, etc. of the original image are shown.
- Regarding the 506th block class and 510th block class, the code amount is longer than the average code length,
The data cannot be stored in one block rask compression memory area set for each data amount of average code length, but is stored using a plurality of areas. In particular, regarding the seventh block class, it cannot be stored even if the second area is used, so three areas are used to store it.

FIG. 6 shows the configuration of the address controller and empty buffer area management circuit 9 shown in FIG. 1. Reference numeral 61 denotes a counter for counting synchronization signals of block rusks, and indicates by a count value whether the area of the second block rusk in the compressed memory is to be accessed. The value corresponding to the block address to be rewritten by the PDL interpreter 62 is sent to the signal line 62.
is set as the initial value of the counter 61, and counts the block rask synchronization signal 63 from the encoder 4. 64 is a counter for counting transfer locks of block data, which counts transfer locks 65 for each byte from the encoder 4, and indicates in which position in the block rask data the block data is stored by the count value. . 64 is reset by the block rask synchronization signal of the encoder. Further, when the data cannot be stored in the memory area for the block rask in the compressed memory, the counter 64 generates a count up (carry) signal 76 and resets itself. In this case, the count-up signal 76 activates the empty buffer area management circuit shown in FIG. 1 to obtain the location of the block rask memory area on the compression memory in which the remaining data is to be subsequently stored. Similar to 61, 66 is a counter for counting synchronization signals of the block raster, and is set by initially counting the first block raster code in the block raster that includes the pixel position to be overwritten by the PDL interpreter 62, and is thereafter set by the decoder. The block raster synchronization signal 67 is counted, and the count value indicates which block raster area in the compressed memory is to be accessed.

Like 64, 68 is a counter for counting data transfer locks, which counts transfer locks for each byte from the decoder, and the count value indicates which position in the block raster data is to be read. 68 is reset by the decoder's Lascue synchronization signal. Further, even if the data is read out all at once from the memory area for the corresponding block raster in the compressed memory, if the data of the block raster is not all read out, the 68 generates a count up (carry) signal 73 and outputs a count-up (carry) signal 73. Reset yourself.

In this case, the empty buffer management circuit shown in FIG. 1 is activated by the count-up signal 73 to obtain the location of the block rask memory area on the compressed memory from which the remaining data should be read out. The free buffer area management circuit 9 includes a counter 6 that counts block data transfer locks.
When activated by the count up (carry) signal 76 from 4, the address of the expansion block raster memory area in the image memory of the block raster being written is output to the signal line 80. At the same time, a selection switching signal 74 of the selector 78 and a latch timing signal 75 of the latch 79 are output. The expansion area block raster memory location output to the signal line 80 is selected and output by the selector 78 at the timing of the signal 74, is held in the latch 79 at the timing of the signal line 75, and is used as the upper address of the storage address of subsequent image data. used. Similarly, when the free buffer management circuit 9 is activated by a count-up (carry) signal 73 from the counter 68 that counts clock data transfer locks, the block raster memory for expansion in the image memory of the block raster being read is activated. The address of the area is output to the signal line 81. At the same time, a selection switching signal 87 for the selector 83 and a latch timing signal 88 for the latch 84 are output. The expansion area block raster memory location output to the signal line 81 is selected and output by the selector 83 at the timing according to the signal 87, and is output to the signal line 88.
It is held in the latch 84 at the timing of , and is used as the upper address of the read address for subsequent image data.

FIG. 7 shows a detailed configuration of the image memory empty buffer area management circuit 9. The buffer read/write control circuit 90 uses the signal 76
When input, the signal 102 is output to the flag buffer 91. The flag buffer 91 is a buffer corresponding to the number of extended free area block rasters as shown in FIG. 8, and is composed of 512 cells each consisting of 1 bit. Each cell corresponds to the 0th expansion (block raster) area to the 511th expansion (block raster) area of the image memory shown in FIG. 4, and "1" indicates that the corresponding expansion area is a free area. , and "0" indicates that it is a medium area for several flights. Buffer 91 receives signal 1
02, each of the 512 bits of information held is
It outputs to a signal 98 consisting of 8-0 to 98-511. The sorter 92 inputs 98, selects the one with the lowest order among the signal lines that are "l" from 98-O to 98 to 511, sets only the signal in that order as "l", and sets the others as "l".
This is a circuit with 512 human-powered outputs that outputs 0''. An example of the configuration of the sorter 92 is shown in FIG. The signal is encoded into a binary number and output as a signal 80 consisting of 9 bits.

A signal 80 outputted by the encoder 93 indicates the position of the extension area in binary representation, and is taken into an extension block address buffer 94.

The buffer table 94 is configured as a table as shown in FIG. 11, and receives the block address before expansion input by the signal 86 from the signal 101 as the access position of the buffer table 94 from the signal 90, and inputs the signal 80 to the corresponding position.
It incorporates the contents of

When the buffer read/write control circuit 90 receives the signal 73, it inputs the block number being read at that time as the signal 82, and outputs the block number as the signal 101 to the extended block address buffer 94. The extended block address buffer 98 outputs the contents of the position specified by the signal 101 to the signal line 81.

The signal line 81 outputs the number of the block rask buffer in which the data subsequent to the block rask being read, inputted by the signal 82, is stored. This signal 81 is also output to the decoder 96 at the same time. The decoder 96 sends the signal 81 expressed as a 9-bit binary number to 512 signal lines 100 by setting only the signals in the order of the numbers representing the 9-bit binary number as "1" and setting the other signals as "O". 100～
Output as 0 to 100-511. The flag buffer update circuit of 95 outputs the signal 98.99.100, and the flag at the position of the extended block used for writing is “0”.
and the flag at the position of the extended block to be read is “1”.
" is used to update the usage status of the empty buffer area of the image memory, the details of which are shown in FIG.

The latch 79 and counter 64 use the output of the latch 79 as an upper address signal, and the count value of 64 as a lower address signal, which is combined and used as a write data address for the compressed memory. The upper address signal, the count value of 68, is combined as the lower address signal and used as the read data address from the compressed memory. A read/write control circuit 70 inputs the write data address, read data address, data transfer lock 65 from the encoder, and data transfer lock 69 from the decoder, and controls data read and write from the compressed memory. It controls addresses and timing.

The character/line drawing memory 10 has a capacity to hold pixel bone data corresponding to the image size to be handled. That is, in this embodiment, each pixel has a capacity of 1 bit for 4096×4096=16,777.216 pixels. Therefore, the 16M address space becomes a memory space with a data capacity of one hit for each address. This memory space is a continuous address space, and for each scanning line, the 0th to 409th
The address space is taken consecutively in the order of the 5th pixel, and these 4096 addresses are taken as a unit from the 0th to the 40th pixel.
The address space for the 95th scanning line is continuously taken. PDL interpreter 2 has character/line drawing memory 10
access the desired address along the above address map.

If the data is a black line drawing, "1" is written in this character/line drawing memory, and when drawing an image other than that, in addition to drawing the data on the compressed memory using the procedure described above, this character/line drawing memory is written as "1". "0" is also written to the address of the corresponding pixel position in the line drawing memory. When the data in the character/line drawing memory 10 is output as an image via the selector 11, it is read out in synchronization with the timing of the image data output from the decoder 6. Reading control from this character/line drawing memory is performed by a character/line drawing memory address control section 12 in response to a scanning synchronization signal and a pixel synchronization signal from the decoder 6. Like the counters 31 and 32 in the address controller in the synthesizer 3 described earlier in FIG. can be configured. The image signal output from the character/line drawing memory is used as the image data of the character/line drawing, and is also used as a selection signal between the character/line drawing data in the selector 11 and the image output from the decoder 6.

When the character/line drawing data is “1”, the selector 11 selects the character/line drawing data.
Line drawing data is selectively outputted, and when it is "0", the output signal of the decoder 6 is selectively outputted.

The encoder and decoder are, for example, CL manufactured by C-Cube, USA.
If an LSI such as 550 is used, the structure can be easily configured by adding a circuit for adjusting a synchronization signal or the like as necessary.

The division of the block rasks is controlled using a marker code, and each block rusk is independently encoded and decoded using this marker code.

[Embodiment 2] In the embodiment described above, when the PDL interpreter 2 receives a PDL command from the host computer 1, it sequentially determines the part of the image that will be changed by the command, and decodes, rewrites, and rewrites the corresponding part. However, the present invention is not limited to this, and as shown in FIG. Once held, the parts to be changed by each command are determined for each command, and rewriting regarding the same block rask is performed at once. That is, the process may be performed as follows: decoding -> executing all rewriting regarding the block rask -> re-encoding.

[Embodiment 3] In the above embodiment, the character/line drawing memory was explained as a bitmap memory, but it is not limited to this (for example, one pixel with a bitmap for each color of cyan, machining, yellow and black) is used. It may be of several bits/pixel, such as a 4-bit configuration.In this case, the first
The selection signal in FIG. 11 may be a logical sum of several bits for the same pixel.

[Embodiment 4] Furthermore, it goes without saying that the character/line drawing memory may also be a compressed memory. In this case, the character/line drawing memory can be treated in exactly the same way as the explanation of decoding → overwriting → recompression in the image compression memory in the above embodiment.

According to the embodiment of the present invention described above, characters and line drawings, which tend to have relatively high spatial frequency components, and other images are stored in separate memory areas, and each is edited separately. It is possible to prevent the image quality of line drawings from deteriorating, and also to suppress drastic changes in the amount of image data coded due to image quality, making it easier to use PDL on a compression memory.

That is, by editing image data using a compressed memory, there is the effect of significantly reducing costs compared to the case where a memory having a data capacity sufficient to hold the actual data is used.

In addition, it is divided into fixed-length blocks with a capacity approximately equal to the average code length of the block rask, and is reproduced, changed, and re-encoded in units of block rusks, and when encoding, the code length exceeding the fixed block length is used. A means for detecting whether or not the length of the block has exceeded the fixed length block and a means for managing free fixed length blocks in the compressed memory are provided. This has the effect of making it easier to edit images using a compression method that uses a variable length code format.

In addition, text and line drawings, which tend to have relatively high spatial frequency components, and other images are stored in separate memory areas,
Editing them separately prevents deterioration in the image quality of characters and line drawings, and also suppresses drastic changes in the amount of image data coded due to image quality, making it easier to use PDL on compressed memory. .

In the above-mentioned embodiment, PS (Postscript) was used as an example of the PDL, but it goes without saying that other PDLs may be used.

Furthermore, the compression format is not limited to ADCT, and may be other orthogonal transform encoding, predictive encoding, run-length encoding, or the like.

Furthermore, editing is not limited to overwriting, but may also include calculations (for example, multiplication, AND, OR, etc.) using previous data and subsequent data. That is, processing such as overlay and modulation can be performed.

In addition to displaying the decoded output signal on a display or other display means, it can also be hard-copied using a racer hem printer, an inkjet printer, a thermal transfer printer, or the like.

〔Effect of the invention〕

As described above, according to the present invention, various image processing can be performed using compressed data.

[Brief explanation of the drawing]

Fig. 1 is a diagram that best represents the features of the present invention, Fig. 2 is a block diagram of the synthesizer, Fig. 3 is a block diagram of the address controller in the synthesizer, and Fig. 4 is a block diagram of each block rask on the compressed memory. Figure 5 shows the data stored in the compressed memory. Figure 6 shows the configuration of the compressed memory address controller. Figure 7 shows the image memory empty buffer area management. 8 is an explanatory diagram of the flag buffer; FIG. 9 is an explanatory diagram of the sorter; FIG. 10 is a diagram of the flag buffer update circuit; FIG. 11 is a diagram of the extended block address buffer; The figure shows a second embodiment. 1... Host computer 2... PDL interpreter 3... Synthesizer 4... Encoder 5... Compression memory 6... Decoder 7... Selector 8... Compressed memory address controller 9...Configuration diagram of image memory empty buffer area management circuit 10...Character/line drawing memory 11...Selector sq diagram

Claims (4)

[Claims] (1) a first storage means for holding compressed image data; a second storage means for holding high-frequency image data; and image data generated from the data held in the first storage means; It is characterized by comprising: means for synthesizing image data generated from data held in the second storage means; and means for editing the image data stored in the first storage means. Image processing device. (2) The editing is performed according to a command written in a page description language.
). (3) The compressed image data is compressed by variable length encoding.
The image processing device described in section 1). (4) The image processing apparatus according to claim (2), wherein the command is sent from a host computer.