JPH0478211B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a semiconductor relay circuit, and more particularly to a semiconductor relay circuit that utilizes isolation by optical coupling.

(Background Art) Conventionally, semiconductor relay circuits that combine a photocoupler and a MOSFET have been proposed. In this conventional example, for example, the input terminal of the relay
An LED is connected, the light from this LED is received by a photodiode array, and the voltage generated across the photodiode array is applied between the gate and source of the MOSFET, and a relay is applied between the source and drain of the MOSFET. It was used as an output terminal.

However, in order to achieve high-speed switching characteristics in this type of semiconductor relay circuit, when an optical signal is output, the switching element must be controlled by an electrical signal generated in the light receiving element that receives this optical signal. In addition to quickly increasing the terminal voltage, when the optical signal is interrupted, it is necessary to quickly discharge the charge accumulated in the control terminal of the switching element and quickly lower the control terminal voltage. For this reason, various control circuits have been added to this type of semiconductor relay circuit to achieve the above operations, but the circuit configuration has become complicated and expensive, or conversely, the circuit configuration has been too simple. There were many cases where we could not expect sufficient effects.

Therefore, the present inventors recognized that a necessary condition for a control circuit is to quickly charge and discharge the charge accumulated in the control terminal of the element that switches between the output terminals of the relay. As a result of examining various elements suitable as components of such control circuits, and after much trial and error, we finally decided on the recently developed insulated-gate planar thyristor (IGT).
Planar Thyristor was found to be an extremely effective device.

(Object of the Invention) The present invention has been made based on the above-mentioned knowledge, and its object is to provide a control circuit for quickly charging and discharging the control voltage of a switching element, and to provide a high-speed switching device. The object of this invention is to realize a semiconductor relay circuit that enables switching with a simple circuit configuration using an insulated gate planar thyristor.

(Disclosure of the Invention) Basic Configuration As shown in FIG. 1, the semiconductor relay circuit according to the present invention includes a pair of input terminals 8 and 9, a light emitting element 1 connected to the input terminals 8 and 9, and A light-receiving element 2 that receives an optical signal from the light-emitting element 1 and outputs an electric signal, a resistor 4 connected to both ends of the light-receiving element 2, a diode 3 whose anode is connected to the anode of the light-receiving element 2, and the diode. P-channel MOSFET connected to the cathode of 3 and the light receiving element 2
A CMOS inverter 5 has the gate terminal of each MOSFET connected to the anode of the light receiving element 2, and a CMOS inverter 5 whose anode terminal is connected to the diode 3.
an insulated gate planar thyristor 6 whose cathode terminal is connected to the cathode of the light receiving element 2 and whose gate terminal is connected to the series connection point of each MOSFET in the CMOS inverter 5; the cathode of the diode 3 and the light receiving element; a switching element 7 with a control terminal connected between the cathode of the switching element 2 and the cathode of the switching element 7, and whose impedance between the current-carrying terminals changes depending on the voltage applied between the control terminals; and a pair of outputs connected to the current-carrying terminals of the switching element 7. Terminals 10 and 11 are provided.

Examples of the present invention will be described below.

Embodiment 1 FIG. 1 is a circuit diagram of an embodiment of the present invention. In this embodiment, as the switching element 7,
N channel enhancement mode
DMOSFET is used. In the embodiment circuit, the anode of the light receiving element 2 is connected to the gate terminal of the switching element 7 via the diode 3, and the cathode is connected to the source terminal of the switching element 7. The switching element 7 has a drain terminal used as the output terminal 10 of the relay, and a source terminal used as the output terminal 11 of the relay, and when the switching element 7 is in the off state, the output terminal 10 is used.
is used while being kept at a positive potential with respect to the output terminal 11, and when it is in the on state, one of the output terminals 1
0 to the other output terminal 11. Furthermore, the substrate of the switching element 7 is connected to the source terminal.

Insulated gate planar thyristor 6 (hereinafter simply referred to as
Regarding the structure and basic operation of IGT6),
For example, IEEE TRANSACTIONS ON
ELECTRON DEVICES VOL.ED−27, NO.2,
FEBRUARY 1980, etc., but I will briefly explain it here. The IGT 6 has a structure as shown in FIG. 2, and its equivalent circuit is shown in FIG. 3. In Figures 2 and 3, A
is an anode terminal, K is a cathode terminal, and G is a gate terminal. As shown in FIG. 2, one side of the N-type semiconductor bulk is heavily doped with P-type;
An anode terminal A is connected to this P-type region. In addition, on the other side of the N-type semiconductor bulk, a pair of weakly doped P-type regions are formed, the center of which is strongly doped with P-type, and a region strongly doped with P-type and a region weakly doped with P-type. The portion extending over the doped region is strongly doped with N type, and an aluminum electrode is deposited on this region which is heavily doped with N type to form a cathode terminal K. A gate electrode is arranged on the surface of the portion extending between the weakly doped P-type region and the N-type semiconductor bulk via a thin insulating layer, and this gate electrode is connected to the gate terminal G.

The equivalent circuit of the structure shown in FIG.
As shown in the figure, a PNP transistor and
The circuit consists of an NPN transistor connected to form a thyristor structure, and an N-channel MOSFET connected in parallel between both ends of the NPN transistor.
That is, the base and collector of the PNP transistor are connected to the collector and base of the NPN transistor, respectively, the emitter of the PNP transistor is connected to the anode terminal A of IGT6, and the emitter of the NPN transistor is connected to the cathode terminal K of IGT6. be done. The collector and emitter of the NPN transistor are connected to the drain and source of the N-channel MOSFET, respectively. The source of the N-channel MOSFET is commonly connected to the substrate terminal, and the gate is connected to the gate terminal G of the IGT6. In addition, R1, R
2 is a parasitic resistance.

The operation of this embodiment will be explained below.

First, the operation of the IGT 6 will be explained. When a voltage is applied so that the anode terminal A has a positive potential with respect to the cathode terminal K, and the gate terminal G has the same potential as the cathode terminal K, the N-channel MOSFET does not conduct. Since the PNP transistor is also in a zero bias state, it does not conduct, so no base current flows through the NPN transistor. Therefore, IGT6
There is no conduction between the anode and cathode. Next, when the gate terminal G reaches a positive voltage level higher than a predetermined threshold voltage with respect to the cathode terminal K and the N-channel MOSFET becomes conductive, a current flows between the emitter and base of the PNP transistor in the IGT 6. By this,
When the PNP transistor becomes conductive, the base current flows through the NPN transistor, and the NPN transistor also becomes conductive. When the NPN transistor becomes conductive, the base current path of the PNP transistor is secured, and due to the thyristor phenomenon, the anode and
A conductive state is established between the cathodes.

Next, the overall operation of the circuit shown in FIG. 1 will be explained. In the circuit shown in FIG. 1, when a voltage is applied between input terminals 8 and 9 by an external circuit, light emitting element 1 outputs an optical signal. The light receiving element 2 receives this optical signal, generates an electric signal, and generates a voltage signal across the resistor 4. This voltage signal is applied via the anode and cathode of the diode 3 to the control terminal of the switching element 7, which is an N-channel enhancement mode DMOSFET. At this time, since the diode 3 is biased in the forward direction, the gate and source of the P-channel MOSFET in the CMOS inverter 5 are reverse biased, and the P-channel MOSFET is not conductive. On the other hand, the gate and source of the N-channel MOSFET in the CMOS inverter 5 are forward biased, and the N-channel MOSFET is conductive. Therefore, the gate terminal G of the IGT 6 is at the same potential as the cathode terminal K. Therefore, there is a high impedance between the gate and source of the switching element 7, and the voltage between the gate and source of the switching element 7 rapidly increases due to the output from the light receiving element 2. At this time, since the gate-source voltage exceeds the threshold voltage of the switching element 7 made of a DMOSFET, the drain-source of the switching element 7 enters a low impedance state.

Next, the voltage between input terminals 8 and 9 is removed,
When the optical signal of the light emitting element 1 is interrupted, the light receiving element 2
generation of electrical signals is stopped. At this time,
The charge in the light receiving element 2 is discharged through the resistor 4, and the voltage across the light receiving element 2 rapidly decreases. On the other hand, the charge accumulated in the control terminal of the switching element 7 is prevented from flowing backward by the diode 3, so that it is not discharged through the path via the diode 3. Therefore, the source potential of the P-channel MOSFET in the CMOS inverter 5 becomes higher than the gate potential, and the P-channel MOSFET
The source-drain impedance of the MOSFET decreases. On the other hand, since the gate potential of the N-channel MOSFET in CMOS inverter 5 has decreased to the same level as the source potential, this N-channel MOSFET
The source-drain impedance of the channel MOSFET increases. As a result, the voltage at the gate terminal G of the IGT 6 increases. This voltage is IGT
When the voltage becomes higher than the threshold voltage of the N-channel MOSFET in 6, this N-channel MOSFET
MOSFET becomes conductive. As a result, a part of the charge accumulated between the gate and source of the switching element 7 is transferred from the anode terminal A of the IGT 6 shown in the equivalent circuit of FIG. It flows to the cathode terminal K. When the voltage generated across the parasitic resistor R1 due to this current exceeds the conduction voltage of the PNP transistor shown in the equivalent circuit of FIG. 3, the PNP transistor becomes conductive.
When the collector current of the PNP transistor flows to the cathode terminal K through the parasitic resistor R2, and the voltage generated across the parasitic resistor R2 exceeds the conduction voltage of the NPN transistor shown in FIG. Becomes conductive.
When both the PNP and NPN transistors shown in FIG. 3 become conductive, these two transistors form a thyristor structure, and the anode and cathode of the IGT 6 become conductive. Therefore, the charges accumulated in the control terminal of the switching element 7 are rapidly discharged. If the threshold voltage of the switching element 7 is set to be equal to or higher than the voltage drop between the anode and cathode when the IGT 6 is conductive, the discharge of the accumulated charge at the control terminal of the switching element 7 will cause the voltage between the drain and source of the switching element 7 to decrease. It quickly becomes a high impedance state.

In this embodiment, since the gate terminal of the enhancement mode switching element 7 can be quickly charged and the accumulated charge can be rapidly discharged, the normally open type ( A normally-off type semiconductor relay circuit can be realized.

Embodiment 2 FIG. 4 is a circuit diagram of another embodiment of the present invention, FIG. 5 is a sectional view of an insulated gate planar thyristor used in the same, and FIG. 6 is a circuit diagram showing an equivalent circuit of the same. In this embodiment, the IGT 6 is equipped with an N-type semiconductor bulk terminal B1. That is, as shown in the cross-sectional structure of FIG. 5, a part of the N-type semiconductor bulk is strongly doped with N-type, an aluminum electrode is deposited thereon, and the bulk terminal B1 is connected. This bulk terminal B1 is connected to the collector of the NPN transistor, as shown in the equivalent circuit of FIG. As shown in FIG. 4, a second resistor 12 is connected between the bulk terminal B1 and the anode terminal A of the IGT 6.
By connecting the N-channel MOSFET shown in the equivalent circuit of Figure 6, the
The drain current of the MOSFET can be controlled without using the parasitic resistance R1 shown in FIG. The other configurations and operations are the same as in the first embodiment.

Embodiment 3 FIG. 7 is a circuit diagram of still another embodiment of the present invention,
FIG. 8 is a sectional view of an insulated gate planar thyristor used in the above, and FIG. 9 is a circuit diagram showing an equivalent circuit of the same. In this embodiment, the IGT 6 is equipped with a P-type semiconductor terminal B2. That is, as shown in the cross-sectional structure of FIG. 8, an aluminum electrode is deposited on the heavily P-type doped portion and connected to the P-type semiconductor terminal B2. As shown in the equivalent circuit of FIG. 9, this P-type semiconductor terminal B2 is a PNP
Connected to the collector of the transistor. 7th
As shown in the figure, by connecting the second resistor 12 between the P-type semiconductor terminal B2 and the cathode terminal K of the IGT 6, the N-channel MOSFET and the PNP transistor shown in the equivalent circuit of Fig. 9 are brought into conduction. Later, when the NPN transistor is turned on, the collector current of the PNP transistor can be controlled without using the parasitic resistance R2 shown in FIG. The other configurations and operations are the same as in the first embodiment.

Note that the output switching element 7 is not limited to an N-channel, but a P-channel switching element may be used by reversing the connection of the gate and source. Similarly, the switching element 7 is not limited to the enhancement mode, but may also be in the depletion mode.
In this case, a normally-closed (normally-on) semiconductor relay circuit can be realized.

Furthermore, in each of the above embodiments, only the case where a DC relay is configured has been described, but it is also possible to configure an AC relay. For example, a pair of MOSFETs may have a common gate and source as the switching element 7. By connecting this to the control terminal of the switching element 7 and using the drain of each MOSFET as the current-carrying terminal, a relay for switching alternating current can be realized.

(Effects of the Invention) As described above, in the present invention, the insulated gate planar thyristor is connected between the control terminals of the switching element, so that once the thyristor is turned on, the self-holding action prevents the switching element from being controlled. The gate of the P-channel MOSFET in the CMOS inverter allows the charge between the terminals to be almost completely discharged, thus allowing rapid discharge of the accumulated charge, and also to provide a trigger voltage to the gate terminal of the thyristor. - A diode is connected between the sources, and when an electrical signal is generated in the light receiving element by an optical signal from the light emitting element, the P channel MOSFET becomes reverse biased, so the thyristor does not conduct. In this state, the gate terminal of the thyristor is pulled down to the same voltage level as the cathode terminal by the N-channel MOSFET in the CMOS inverter, so the thyristor is not turned on inadvertently, and the connection between the control terminals of the switching element is ensured. It is possible to quickly charge the control terminal by setting the impedance to high, and therefore, it has the effect of realizing extremely high-speed switching with a simple configuration.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of an embodiment of the present invention, FIG. 2 is a cross-sectional view of an insulated gate planar thyristor used in the above, FIG. 3 is a circuit diagram showing an equivalent circuit of the same, and FIG. 4 is a circuit diagram of an embodiment of the present invention. FIG. 5 is a cross-sectional view of an insulated gate planar thyristor used in the same example, FIG. 6 is a circuit diagram showing an equivalent circuit of the same example, and FIG.
The figure is a circuit diagram of still another embodiment of the present invention, FIG. 8 is a sectional view of an insulated gate planar thyristor used in the same, and FIG. 9 is a circuit diagram showing an equivalent circuit of the same. 1 is a light emitting element, 2 is a light receiving element, 3 is a diode, 4 is a resistor, 5 is a CMOS inverter, 6 is a
IGT, 7 is a switching element, 8 and 9 are input terminals, and 10 and 11 are output terminals.

Claims (1)

[Claims] 1 A pair of input terminals, a light emitting element connected to the input terminal, a light receiving element that receives an optical signal from the light emitting element and outputs an electrical signal, a resistor connected to both ends of the light receiving element, and the light receiving element. a diode whose anode is connected to the anode of the diode, a P-channel MOSFET connected to the cathode of the diode, and an N-channel MOSFET connected to the cathode of the light receiving element.
are connected in series, and the gate terminal of each MOSFET is connected to the anode of the light receiving element.
an inverter, an anode terminal serving as the cathode of the diode, and a cathode terminal serving as the cathode of the light receiving element;
an insulated gate planar thyristor whose gate terminal is connected to the series connection point of each of the MOSFETs in the CMOS inverter, a control terminal connected between the cathode of the diode and the cathode of the light receiving element, and a voltage applied between the control terminals. 1. A semiconductor relay circuit comprising: a switching element whose impedance between current-carrying terminals changes according to a voltage; and a pair of output terminals connected to the current-carrying terminals of the switching element.