JPH0478031B2 - - Google Patents
Info
- Publication number
- JPH0478031B2 JPH0478031B2 JP58232341A JP23234183A JPH0478031B2 JP H0478031 B2 JPH0478031 B2 JP H0478031B2 JP 58232341 A JP58232341 A JP 58232341A JP 23234183 A JP23234183 A JP 23234183A JP H0478031 B2 JPH0478031 B2 JP H0478031B2
- Authority
- JP
- Japan
- Prior art keywords
- light
- ring
- light receiving
- substrate
- solder layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
- H10F77/00—Constructional details of devices covered by this subclass
- H10F77/93—Interconnections
- H10F77/933—Interconnections for devices having potential barriers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
- H10F30/00—Individual radiation-sensitive semiconductor devices in which radiation controls the flow of current through the devices, e.g. photodetectors
- H10F30/20—Individual radiation-sensitive semiconductor devices in which radiation controls the flow of current through the devices, e.g. photodetectors the devices having potential barriers, e.g. phototransistors
-
- G—PHYSICS
- G02—OPTICS
- G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
- G02B6/24—Coupling light guides
- G02B6/42—Coupling light guides with opto-electronic elements
- G02B6/4201—Packages, e.g. shape, construction, internal or external details
- G02B6/4202—Packages, e.g. shape, construction, internal or external details for coupling an active element with fibres without intermediate optical elements, e.g. fibres with plane ends, fibres with shaped ends, bundles
-
- G—PHYSICS
- G02—OPTICS
- G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
- G02B6/24—Coupling light guides
- G02B6/42—Coupling light guides with opto-electronic elements
- G02B6/4201—Packages, e.g. shape, construction, internal or external details
- G02B6/4204—Packages, e.g. shape, construction, internal or external details the coupling comprising intermediate optical elements, e.g. lenses, holograms
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
- H10F77/00—Constructional details of devices covered by this subclass
- H10F77/50—Encapsulations or containers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
- H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
- H10H20/80—Constructional details
- H10H20/85—Packages
- H10H20/855—Optical field-shaping means, e.g. lenses
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
- H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
- H10H20/80—Constructional details
- H10H20/85—Packages
- H10H20/857—Interconnections, e.g. lead-frames, bond wires or solder balls
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Optics & Photonics (AREA)
- Light Receiving Elements (AREA)
Description
【発明の詳細な説明】 (ア) 技術分野 この発明は受光ダイオードに関する。[Detailed description of the invention] (a) Technical field The present invention relates to a light receiving diode.
受光ダイオードは、pinホトダイオード、アバ
ランシエホトダイオードなどがある。メサ型、プ
レーナ型などの形状がある。 Photodiodes include pin photodiodes and avalanche photodiodes. There are shapes such as mesa type and planar type.
受光ダイオードには、高速応答性が要求され
る。この場合、静電容量を減らすため、メサ型に
して、pn接合部の面積を狭くするのが有効であ
る。 Light-receiving diodes are required to have high-speed response. In this case, in order to reduce capacitance, it is effective to use a mesa type to reduce the area of the pn junction.
光フアイバと結合されて使用される場合、高い
結合効率が望まれる。 When used in conjunction with optical fibers, high coupling efficiency is desired.
(イ) 従来技術とその欠点
受光ダイオードは、従来上方に窓のあるハーメ
チツクシールタイプのパツケージに収容される事
が多かつた。この構造では、受光素子チツプの基
板底部に電極があり、パツケージに全面ハンダ付
けされる。(a) Prior Art and its Disadvantages Conventionally, light receiving diodes have often been housed in hermetic seal type package cages with windows at the top. In this structure, an electrode is provided at the bottom of the substrate of the photodetector chip, and the entire surface is soldered to the package.
チツプの上面に光の入る受光面と、これを囲む
リング電極がある。リング電極と、パツケージの
リードピンの間をワイヤボンデイングしてある。
ワイヤは上方へ彎曲しているから、ワイヤに接触
しないよう、パツケージキヤツプはある程度の高
さが必要である。このため光フアイバ端と、受光
素子チツプの間隔が離れてしまう。 There is a light-receiving surface on the top surface of the chip, into which light enters, and a ring electrode surrounding this surface. Wire bonding is performed between the ring electrode and the lead pin of the package.
Since the wires are curved upwards, the package cap needs to be a certain height to avoid contacting the wires. Therefore, the distance between the end of the optical fiber and the light receiving element chip becomes large.
そこで、底面に受光面を持つような構造の受光
ダイオードも作製されるようになつた。 Therefore, light-receiving diodes with a structure having a light-receiving surface on the bottom surface have also been manufactured.
底面の中央部を受光面として残し、周辺にリン
グ電極を設ける。上面には単なる（非リング）電
極をつけて、ワイヤボンデイングするようにな
る。 The central part of the bottom is left as a light-receiving surface, and a ring electrode is provided around the periphery. A simple (non-ring) electrode is attached to the top surface and wire bonding is performed.
pn接合部は、基板上方のエピタキシヤル層に
あるから、メサ型にすることが可能になる。 Since the pn junction is in the epitaxial layer above the substrate, it is possible to make it mesa-shaped.
メサ型ホトダイオードは、例えば次のような構
造をしている。ｎ−InP基板の上にノンドープの
InGaAsのエピタキシヤル成長層を作り、上面か
らZnを拡散して、pn接合を作る。上方を台形状
にエツチングするとメサ型となる。 For example, a mesa photodiode has the following structure. Non-doped on n-InP substrate
Create an epitaxial growth layer of InGaAs and diffuse Zn from the top surface to create a pn junction. If the upper part is etched into a trapezoidal shape, it will become a mesa shape.
チツプの上面にはｐ型電極（Au−Zn）、底面
にはリング状のｎ型電極（AuGeNi）を設ける。 A p-type electrode (Au-Zn) is provided on the top surface of the chip, and a ring-shaped n-type electrode (AuGeNi) is provided on the bottom surface.
このようなチツプはウエハプロセスで作製され
る。多数の素子が作られた後、スクライブして、
チツプに分離する。 Such chips are manufactured using a wafer process. After a large number of elements are made, scribe and
Separate into chips.
これをパツケージの実装しなければならない。 This must be implemented in the package.
第４図は従来の受光ダイオードチツプ９をサフ
アイヤ基板１の上にハンダ付けする例を示す。サ
フアイヤ基板１は透明であるから、光を通す。サ
フアイヤ基板１の上に、開口部４を有する導電性
のダイボンデイング用パツド３をメタライズす
る。 FIG. 4 shows an example in which a conventional light receiving diode chip 9 is soldered onto a sapphire substrate 1. As shown in FIG. Since the sapphire substrate 1 is transparent, light passes through it. A conductive die bonding pad 3 having an opening 4 is metallized on a sapphire substrate 1.
ダイボンデイング用パツド３はAu系の材料が
主に用いられるがこれは、塗布すべき部分の穴の
ある薄いスクリーンを基板に重ねペーストを塗り
込むスクリーン印刷によつて塗布する。塗布時に
は平坦である。 The die bonding pad 3 is mainly made of Au-based material, which is applied by screen printing in which a thin screen with holes in the areas to be applied is placed on the substrate and the paste is applied. It is flat when applied.
しかし、焼成すると、ペーストは端部で表面張
力のために隆起することがある。このままの形状
に保つて固化すると、ペースト表面には第４図に
示すような不規則な凹凸が生ずる。これをパツド
として用いる。受光ダイオードチツプ９をダイボ
ンデイング用パツド３の上においてボンデイング
する。 However, upon firing, the paste may bulge at the edges due to surface tension. If the paste is kept in the same shape and solidified, irregular irregularities as shown in FIG. 4 will be formed on the surface of the paste. Use this as a pad. A photodiode chip 9 is bonded onto the die bonding pad 3.
パツド３に凹凸があると、チツプ９が傾いたま
ま固定される。 If the pad 3 is uneven, the chip 9 will be fixed in an inclined position.
第５図は透明でない基板に取り付ける例を示
す。セラミツク基板２０の上に、導電性ボンデイ
ングパツド２１を蒸着などによつて付け、光導入
用穴２３が穿たれている。 FIG. 5 shows an example of attachment to a non-transparent substrate. A conductive bonding pad 21 is attached on the ceramic substrate 20 by vapor deposition or the like, and a hole 23 for introducing light is bored.
この上に、リングハンダ２４を載せ、受光ダイ
オードチツプ９をハンダ付けする。 A ring solder 24 is placed on top of this, and a light receiving diode chip 9 is soldered thereon.
この際、次のような困難がある。 In this case, there are the following difficulties.
ひとつは、リングハンダ２４と光導入用穴２３
との位置合わせが難しい、という事である。この
ため、ハンダ２４が光導入用穴２３の中へはみ出
す２５ことがある。 One is the ring solder 24 and the light introduction hole 23.
This means that alignment is difficult. Therefore, the solder 24 may protrude 25 into the light introduction hole 23.
たとえ、ハンダ２４が正しい位置に載つていた
としても、チツプ９を置いて圧力をかけてハンダ
付けすると、ハンダ２４がはみ出す２５こともあ
る。 Even if the solder 24 is placed in the correct position, the solder 24 may protrude 25 when the chip 9 is placed and soldered under pressure.
ハンダ厚みを少なくすればムラを減ずることが
できるが、ハンドリングのため、ハンダ厚みは20
〜30μｍ以上必要である。 The unevenness can be reduced by reducing the solder thickness, but for handling purposes, the solder thickness should be 20
~30 μm or more is required.
このようなわけで、ハンダ２４がチツプ底面の
受光面積を狭少化し、受光ダイオードの感度を減
殺することがあつた。 For this reason, the solder 24 sometimes narrows the light-receiving area on the bottom surface of the chip and reduces the sensitivity of the light-receiving diode.
さらに、固着強度の問題もある。リングハンダ
プリフオーム（例えば、外径500μｍ、内径250μ
ｍ、30μｍｔのAuSn合金）を用いて、ダイボン
ドを行うとプリフオームが溶けてから受光ダイオ
ードをダイボンドするまでのタイムラグがあるた
め、受光ダイオード底面とハンダが一様に接触せ
ず、ダイボンド感度にバラつきが生ずる等の問題
がある。 Furthermore, there is also the problem of adhesion strength. Ring solder preform (e.g. outer diameter 500μm, inner diameter 250μm)
When die-bonding is performed using a 30μm AuSn alloy), there is a time lag from the time the preform melts until the photodiode is die-bonded, so the bottom surface of the photodiode and the solder do not come into uniform contact, resulting in variations in die-bonding sensitivity. There are problems such as the occurrence of
(ウ) 発明の構成
本発明は、パツケージの基板の方にハンダ付け
するのではなく、チツプの側にハンダ層を予め付
けておくようにする。(C) Structure of the Invention In the present invention, a solder layer is preliminarily applied to the chip side, rather than soldering to the substrate of the package.
第１図はメサホトダイオードチツプに本発明を
適用した例を示す断面図である。 FIG. 1 is a sectional view showing an example in which the present invention is applied to a mesa photodiode chip.
SnドープInP基板１０の上に、液相エピタキシ
ヤル法により、ノンドープInGaAsエピタキシヤ
ル層１１を、InP基板１０に格子整合する条件下
で成長させる。 A non-doped InGaAs epitaxial layer 11 is grown on the Sn-doped InP substrate 10 by a liquid phase epitaxial method under conditions of lattice matching to the InP substrate 10.
次に、Zn拡散により、ｐ型領域１２を作る。
これによつてpn接合が形成される。 Next, a p-type region 12 is formed by Zn diffusion.
This forms a pn junction.
この後、AuZnを用いてｐ側電極１３を形成す
る。AuGeNiを用いてリング状のｎ側電極１４を
形成する。 After this, the p-side electrode 13 is formed using AuZn. A ring-shaped n-side electrode 14 is formed using AuGeNi.
さらに、静電容量を減ずるため、pn接合部の
近傍を両側からエツチングする。 Furthermore, in order to reduce capacitance, the vicinity of the pn junction is etched from both sides.
次に、アルカノールスルホン酸系のメツキ液で
Snメツキパターンをｎ側電極１４の下側にリン
グ状に形成した。メツキパターンの横断面形状は
電極１４のパターンのそれに等しくする。 Next, use alkanol sulfonic acid-based plating solution.
A ring-shaped Sn plating pattern was formed on the lower side of the n-side electrode 14. The cross-sectional shape of the plating pattern is made equal to that of the pattern of the electrode 14.
Snメツキ部はハンダとして作用するので、以
後ハンダ層１５と呼ぶ。 Since the Sn plating portion acts as a solder, it will be referred to as a solder layer 15 hereinafter.
ハンダ層１５とｎ側電極１４が内外径の寸法が
同一のリング状になり、チツプ下面中央部が露出
する。これが受光面１６となる。 The solder layer 15 and the n-side electrode 14 have a ring shape with the same inner and outer diameters, and the center portion of the lower surface of the chip is exposed. This becomes the light receiving surface 16.
ハンダ層の厚みは１〜10μｍとする。 The thickness of the solder layer is 1 to 10 μm.
以上の工程は全てウエハプロセスによつて行
う。この後、スクライブして個々のチツプに分割
する。 All of the above steps are performed by a wafer process. After this, it is scribed and divided into individual chips.
ハンダ層１５の形成方法は、メツキ法、蒸着法
などが有効である。 Effective methods for forming the solder layer 15 include a plating method and a vapor deposition method.
ハンダ層１５の素材としては、Snの他、Au−
Sn共晶合金、Au−Si共晶合金などを用いる事が
できる。 In addition to Sn, the material for the solder layer 15 is Au-
Sn eutectic alloy, Au-Si eutectic alloy, etc. can be used.
以上主たる製造工程について述べた。 The main manufacturing process has been described above.
このような受光素子チツプを、実際にダイボン
ドするには、ハンダ材としてSnを用いた時、ボ
ンドすべきパツケージを250℃に熱しておき、予
めハンダ層１５をつけたチツプを、パツドに対し
位置合わせしながらダイボンドする。 To actually die-bond such a photodetector chip, when Sn is used as the solder material, heat the package to be bonded to 250°C, and position the chip to which the solder layer 15 has been applied in advance against the pad. Die bond while matching.
この際、他のハンダは用いなくても良い。チツ
プ下底のハンダ層１５が一時的に融けて固化し、
ハンダ付けができる。 At this time, it is not necessary to use any other solder. The solder layer 15 at the bottom of the chip temporarily melts and solidifies.
Can be soldered.
この受光素子チツプをダイボンデイングする
と、Snのメツキ厚みが５〜10μｍの場合、最も良
好にボンデイングされた。薄いハンダであるから
融けても、流れ出したり変形したりする事はな
い。ハンダがそのままの形状を保ちながら融け受
光素子チツプに接触した後そのまま固化するから
である。 When this photodetector chip was die-bonded, bonding was best achieved when the Sn plating thickness was 5 to 10 μm. Since the solder is thin, it will not flow or deform even if it melts. This is because the solder melts while maintaining its shape and solidifies after coming into contact with the light receiving element chip.
メツキ厚みが5μｍ以下では、ボンデイング強
度にバラつきがあつた。 When the plating thickness was 5 μm or less, there was variation in bonding strength.
メツキ厚みが10μｍ以上では、Snハンダしみ出
しがあり、しかも、これがバラつくという欠点が
あつた。厚みが大きすぎるので融けたハンダが変
形流動しやすくなり、受光素子チツプを押し付け
るとハンダが両側に流動してしみ出すためであ
る。厚みの最適範囲はハンダ素材の種類により異
なるが、一般に５〜10μｍが良いようである。 When the plating thickness was 10 μm or more, Sn solder seeped out, and this had the disadvantage of being uneven. This is because if the thickness is too large, the melted solder will easily deform and flow, and when the light-receiving element chip is pressed, the solder will flow to both sides and seep out. The optimum range of thickness varies depending on the type of solder material, but generally 5 to 10 μm seems to be good.
(エ) パツケージング
本発明は、ハンダ層をチツプ側に設ける。パツ
ケージの基板には、このハンダ層を利用して、ダ
イボンドする。(d) Packaging In the present invention, a solder layer is provided on the chip side. This solder layer is used to die-bond the package substrate.
基板、パツケージの材質、形状は任意である。 The material and shape of the substrate and package are arbitrary.
第２図にサフアイヤ基板を用いたフラツトタイ
プのパツケージに取り付けた状態を示している。
このパツケージ自体は本出願人が先に出願（特願
昭58−97628号S58.5.31出願、特開昭59−220982
号S59.12.12公開）したものである。 Figure 2 shows the state in which it is attached to a flat type package using a sapphire substrate.
This package itself was first filed by the applicant (Japanese Patent Application No. 58-97628 S58.5.31, Japanese Patent Application No. 59-220982)
No. S59.12.12).
サフアイヤ基板１の上に四角形の受光素子チツ
プを収容する空間を有する下枠２が接着（ろう付
け）してある。サフアイヤ基板１の中央には、開
口部４を有する導電性のダイボンデイング用パツ
ド３がメタライズしてある。パツド３の一端は下
枠の受光素子チツプ収容空間の側面を通り下枠２
の上面に至り下枠２の外周端まで延びている。 A lower frame 2 having a space for accommodating a rectangular light-receiving element chip is bonded (brazed) onto a sapphire substrate 1. In the center of the sapphire substrate 1, a conductive die bonding pad 3 having an opening 4 is metalized. One end of the pad 3 passes through the side of the light-receiving element chip housing space in the lower frame 2.
It reaches the upper surface of the lower frame 2 and extends to the outer peripheral edge of the lower frame 2.
下枠２の上に、中央に広い開口を有する四角形
の上枠５が接着される。ダイボンデイング用パツ
ド３の延長辺にリード６をハンダ付けしてある。 A rectangular upper frame 5 having a wide opening in the center is glued onto the lower frame 2. A lead 6 is soldered to the extended side of the die bonding pad 3.
下枠２の対向辺には、受光素子チツプ収容空間
のある内端から外端に至るように、ワイヤボンデ
イング用パツド８がメタライズしてある。この延
長辺に、リード７がハンダ付けしてある。 Wire bonding pads 8 are metallized on opposite sides of the lower frame 2 from the inner end where the light receiving element chip accommodation space is located to the outer end. Leads 7 are soldered to this extended side.
ダイボンデイング用パツド３の上へ、直接（新
たにハンダを付けず）第１図の受光素子チツプを
置く。そしてダイボンドし、ｎ側電極３４とパツ
ド３を固着する。 Place the light-receiving element chip shown in FIG. 1 directly (without adding any new solder) onto the die bonding pad 3. Then, die bonding is performed to fix the n-side electrode 34 and pad 3.
ｐ側電極１３は、ワイヤボンデイング１０′し
てパツド８に接続する。上枠５の上には後に蓋板
（図示せず）が固着され、内部空間が密閉される。 The p-side electrode 13 is connected to the pad 8 by wire bonding 10'. A cover plate (not shown) is later fixed on top of the upper frame 5 to seal the internal space.
光は、サフアイヤ基板１、パツド３の開口部４
を通つて受光面１６に達する。 The light comes from the opening 4 of the sapphire substrate 1 and pad 3.
It reaches the light-receiving surface 16 through.
ここに示すように、ハンダ層１５のしみ出し、
ずれなどが起こらない。 As shown here, the solder layer 15 seeps out,
No misalignment will occur.
第３図にセラミツク基板パツケージに適用した
例を示す。第５図のパツケージと同様の構造であ
るが、セラミツク基板のダイボンデイング用パツ
ド２１の開口部１５の周囲上面にはハンダを付け
ておかない。 FIG. 3 shows an example of application to a ceramic substrate package. Although the structure is similar to that of the package shown in FIG. 5, no solder is applied to the upper surface around the opening 15 of the die bonding pad 21 of the ceramic substrate.
チツプ側のハンダ層１５がパツド２１にハンダ
付け作用する。 The solder layer 15 on the chip side acts to solder the pad 21.
ワイヤボンデイング、リード、パツケージ外形
などは図示を省略した。 Wire bonding, leads, package outline, etc. are omitted from illustration.
(オ) 適用範囲 受光ダイオード全般に適用できる発明である。(e) Scope of application This invention is applicable to all light receiving diodes.
メサ型ホトダイオードの他にプレーナ型ホトダ
イオードにも適用できる。 It can be applied to planar photodiodes as well as mesa photodiodes.
アバランシエホトダイオード（APD）にも適
用する事ができる。 It can also be applied to avalanche photodiodes (APDs).
(カ) 効果
(1) ダイボンデイング時に、受光用窓が汚染され
ない。ホトダイオードの感度が損なわれない。
組立歩留りが向上する。(f) Effects (1) The light receiving window is not contaminated during die bonding. The sensitivity of the photodiode is not compromised.
Assembly yield is improved.
受光ダイオードのダイボンド部の受光用窓以
外の部分にSn等のメタライズ層をつくりつけ
で形成しているためである。 This is because a metallized layer of Sn or the like is formed on the die-bonded part of the light-receiving diode other than the light-receiving window.
Sn等のメタライズ層の厚みは、±0.2μｍの精
度で自由に制御できるから、ハンダはみ出しな
どが起こらない。 The thickness of the metallized layer, such as Sn, can be freely controlled with an accuracy of ±0.2 μm, so solder does not ooze out.
(2) ダイボンド時にハンダ又はエポキシ樹脂など
のダイボンド材を特別に用意する必要がない。(2) There is no need to specially prepare die bonding materials such as solder or epoxy resin during die bonding.
工程が簡単になり、生産性が向上する。 The process becomes simpler and productivity improves.
第１図は本発明を実施するために使われるメサ
型受光ダイオードの縦断面図。第２図は第１図の
受光ダイオードをサフアイヤ基板フラツトパツケ
ージの中へ収容した状態を示す縦断面図。第３図
は第１図の受光ダイオードをアルミナ基板の上へ
ダイボンドした状態を示す縦断面図。第４図は従
来のサフアイヤ基板への受光ダイオードのダイボ
ンデイングの状態を示す縦断面図。第５図は従来
例に係るアルミナ基板への受光ダイオードのボン
デイング例を示す縦断面図。
１……サフアイヤ基板、２……下枠、３……ダ
イボンデイング用パツド、４……開口部、５……
上枠、６，７……リード、９……受光素子チツ
プ、１０……ｎ−InP基板、１１……InGaAsエ
ピタキシヤル層、１２……Zn拡散領域、１３…
…ｐ側電極、１４……ｎ側電極、１５……ハンダ
層、１６……受光面。
FIG. 1 is a longitudinal cross-sectional view of a mesa-type light receiving diode used to implement the present invention. FIG. 2 is a longitudinal sectional view showing the light receiving diode shown in FIG. 1 housed in a sapphire substrate flat package. FIG. 3 is a longitudinal cross-sectional view showing a state in which the light receiving diode shown in FIG. 1 is die-bonded onto an alumina substrate. FIG. 4 is a vertical sectional view showing the state of die bonding of a light receiving diode to a conventional sapphire substrate. FIG. 5 is a longitudinal sectional view showing an example of bonding a light receiving diode to an alumina substrate according to a conventional example. 1...Sapphire substrate, 2...Bottom frame, 3...Die bonding pad, 4...Opening, 5...
Upper frame, 6, 7...Lead, 9...Photodetector chip, 10...n-InP substrate, 11...InGaAs epitaxial layer, 12...Zn diffusion region, 13...
... p-side electrode, 14 ... n-side electrode, 15 ... solder layer, 16 ... light-receiving surface.
Claims (1)
光導入用穴を有する基板と、基板の上に固着され
受光素子チツプを収容する空間を有する下枠と、
該下枠の上面の外端から内端に至り前記受光素子
チツプ収容空間の側面を通り基板の中央に至るよ
うに延びており基板中央の位置で光を通すための
開口部を有するダイボンデイング用パツドと、下
枠の上面において受光素子チツプ収容空間のある
内端から外端に至るようメタライズされたワイヤ
ボンデイング用パツドと、中央に広い開口を有し
下枠の上に固着されるべき上枠と、ダイボンデイ
ング用パツドとワイヤボンデイング用パツドとの
外方端部に於いてこれに接着されるリードとより
なる受光素子用パツケージに、ウエハプロセスに
よつて単結晶ウエハの上にウエハと同導電型のエ
ピタキシヤル層を形成し、前記エピタキシヤル層
上に異導電型のエピタキシヤル層を形成した後エ
ツチングによりpn接合部を終端させるか、又は
前記エピタキシヤル層内に拡散又はイオン注入等
によりエピタキシヤル層内に異導電型の領域を部
分的に形成し部分的にpn接合部を形成すること
により、エピタキシヤル層内に該接合部に近い面
上で終端させる様にpn接合部を形成し、pn接合
部に近い方の面にワイヤボンド用の電極を設け、
pn接合部から遠い方の面は光が通るべき中央の
部分を残してリング状のダイボンド用電極を形成
しリング状のダイボンド用電極の下にこれと横断
面形状が同一のリング状のハンダ層を５〜10μｍ
の厚みでメタライズしておき、この後ウエハをス
クライブして個々の受光素子チツプに分割する事
とした受光素子チツプを取り付ける方法であつ
て、受光素子用パツケージのダイボンデイング用
パツドには予めハンダを付けず、予め加熱された
受光素子用パツケージのダイボンデイング用パツ
ドの開口部の周囲に合致するよう、受光素子チツ
プ下面のリングハンダ層を押し当てる事によつ
て、受光素子チツプを受光素子用パツケージにダ
イボンデイングし、ワイヤボンド用電極とワイヤ
ボンデイング用パツドとをワイヤで接続する事を
特徴とする受光ダイオードの製造方法。 ２ リングハンダ層がsnである特許請求の範囲第
１項記載の受光ダイオードの製造方法。 ３ リングハンダ層がAu−Sn共晶合金である特
許請求の範囲第１項記載の受光ダイオードの製造
方法。 ４ リングハンダ層がAu−Si共晶合金である特
許請求の範囲第１項記載の受光ダイオードの製造
方法。 ５ リングハンダ層がメツキ法により形成される
特許請求の範囲第１項記載の受光ダイオードの製
造方法。 ６ リングハンダ層が蒸着法により形成されてい
る特許請求の範囲第１項記載の受光ダイオードの
製造方法。[Scope of Claims] 1. A transparent substrate or a substrate having a light introduction hole that takes in light from the outside from below; a lower frame fixed on the substrate and having a space for accommodating a light receiving element chip;
For die bonding, the lower frame extends from the outer edge of the upper surface to the inner edge, passes through the side surface of the light-receiving element chip housing space, and reaches the center of the substrate, and has an opening for passing light at the center of the substrate. A pad for wire bonding, which is metallized on the upper surface of the lower frame from the inner end where the light receiving element chip is accommodated to the outer end, and the upper frame which has a wide opening in the center and is to be fixed onto the lower frame. Then, a photodetector package consisting of a lead bonded to the outer end of the die bonding pad and the wire bonding pad is placed on a single crystal wafer by a wafer process and is conductive in the same manner as the wafer. After forming a type epitaxial layer and forming an epitaxial layer of a different conductivity type on the epitaxial layer, the p-n junction is terminated by etching, or epitaxial layer is formed by diffusion or ion implantation into the epitaxial layer. By partially forming regions of different conductivity types in the epitaxial layer and partially forming pn junctions, a pn junction is formed in the epitaxial layer so as to terminate on a surface close to the junction. , an electrode for wire bonding is provided on the side closer to the p-n junction,
A ring-shaped die-bonding electrode is formed on the surface far from the p-n junction, leaving a central part through which light should pass, and a ring-shaped solder layer with the same cross-sectional shape as the ring-shaped die-bonding electrode is formed below the ring-shaped die-bonding electrode. 5~10μm
This is a method of attaching photodetector chips in which the wafer is metalized to a thickness of The photodetector chip is attached to the photodetector package by pressing the ring solder layer on the underside of the photodetector chip so that it matches the circumference of the opening of the die bonding pad of the photodetector package which has been heated in advance. A method of manufacturing a light receiving diode, which comprises performing die bonding on the diode and connecting a wire bonding electrode and a wire bonding pad with a wire. 2. The method for manufacturing a light receiving diode according to claim 1, wherein the ring solder layer is SN. 3. The method for manufacturing a light receiving diode according to claim 1, wherein the ring solder layer is an Au-Sn eutectic alloy. 4. The method for manufacturing a light receiving diode according to claim 1, wherein the ring solder layer is an Au-Si eutectic alloy. 5. The method of manufacturing a light receiving diode according to claim 1, wherein the ring solder layer is formed by a plating method. 6. The method for manufacturing a light receiving diode according to claim 1, wherein the ring solder layer is formed by a vapor deposition method.
Priority Applications (16)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58232341A JPS60124885A (en) | 1983-12-08 | 1983-12-08 | Manufacturing method of photodiode |
| CA000467175A CA1267468A (en) | 1983-11-21 | 1984-11-06 | Optical device package |
| DE88202641T DE3486214T2 (en) | 1983-11-21 | 1984-11-14 | Manufacturing process of optical assemblies and brackets. |
| DE8484307870T DE3481571D1 (en) | 1983-11-21 | 1984-11-14 | OPTICAL DEVICE AND HOUSING FOR OPTICAL DEVICE. |
| EP84307870A EP0145316B1 (en) | 1983-11-21 | 1984-11-14 | Optical device and package for optical device |
| FI844473A FI82999C (en) | 1983-11-21 | 1984-11-14 | OPTICAL ANGLE FARING FOR FOUNDATION. |
| EP88202641A EP0313174B1 (en) | 1983-11-21 | 1984-11-14 | Method for producing optical devices and packages |
| US06/671,783 US4663652A (en) | 1983-11-21 | 1984-11-15 | Package for optical device |
| DK547384A DK163761C (en) | 1983-11-21 | 1984-11-16 | OPTICAL COMPONENT AND HOUSE FOR SUCH A COMPONENT. |
| NO844596A NO169684C (en) | 1983-11-21 | 1984-11-19 | OPTICAL ELEMENT HOLDER AND DEVICE INCLUDING THE HOLDER. |
| KR1019840007563A KR890003384B1 (en) | 1983-12-08 | 1984-11-30 | Light-receiving diode and its manufacturing method |
| US06/905,231 US4727649A (en) | 1983-11-21 | 1986-09-09 | Method for producing an optical device |
| FI880867A FI91574C (en) | 1983-11-21 | 1988-02-24 | Housing for an optical device and a method of manufacturing the optical device |
| AU13197/88A AU592256B2 (en) | 1983-11-21 | 1988-03-16 | Optical device and method |
| CA000603408A CA1273091A (en) | 1983-11-21 | 1989-06-20 | Method for producing an optical device |
| DK033291A DK33291A (en) | 1983-11-21 | 1991-02-26 | PROCEDURE FOR MANUFACTURING AN OPTICAL COMPONENT |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58232341A JPS60124885A (en) | 1983-12-08 | 1983-12-08 | Manufacturing method of photodiode |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60124885A JPS60124885A (en) | 1985-07-03 |
| JPH0478031B2 true JPH0478031B2 (en) | 1992-12-10 |
Family
ID=16937681
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58232341A Granted JPS60124885A (en) | 1983-11-21 | 1983-12-08 | Manufacturing method of photodiode |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JPS60124885A (en) |
| KR (1) | KR890003384B1 (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01296676A (en) * | 1988-05-24 | 1989-11-30 | Nec Corp | Semiconductor photodetecting device |
| JP5576094B2 (en) * | 2009-11-11 | 2014-08-20 | 旭化成エレクトロニクス株式会社 | Optical device manufacturing method and optical device |
| CN104697556B (en) * | 2015-02-28 | 2017-09-12 | 武汉联钧科技有限公司 | A kind of two waveband photoelectric sensor |
| TWI598653B (en) * | 2016-03-16 | 2017-09-11 | 峰川光電股份有限公司 | Photoelectric conversion assembly |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5157174A (en) * | 1974-11-14 | 1976-05-19 | Hamamatsu Tv Co Ltd | Kodenhenkansoshino seisakuho |
| JPS5337383A (en) * | 1976-09-20 | 1978-04-06 | Hitachi Ltd | Semiconductor integrated circuit |
-
1983
- 1983-12-08 JP JP58232341A patent/JPS60124885A/en active Granted
-
1984
- 1984-11-30 KR KR1019840007563A patent/KR890003384B1/en not_active IP Right Cessation
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5157174A (en) * | 1974-11-14 | 1976-05-19 | Hamamatsu Tv Co Ltd | Kodenhenkansoshino seisakuho |
| JPS5337383A (en) * | 1976-09-20 | 1978-04-06 | Hitachi Ltd | Semiconductor integrated circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS60124885A (en) | 1985-07-03 |
| KR890003384B1 (en) | 1989-09-19 |
| KR850005175A (en) | 1985-08-21 |
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