JPH0476598A - Display controller - Google Patents

Abstract

PURPOSE:To reduce the load on a CPU when a specific part of a display memory is updated by writing address information which is held in a memory write address register in the register as it is when the value of the memory write address register needs to be reset. CONSTITUTION:The address of the display memory 2 corresponding to the character 9c at the head to be blinked first is set in the memory write address register 5 through a CPU interface 4. At the same time, the value of the address is written in a memory write address storage register 10. Then character codes corresponding to display characters 9c and 9d are written in the memory 2. Then the address value of the display character 9c at the head to be blinked is reset in the register 5 to make a turn-off display, but the contents of a storage register 10 are transferred to a register 5 through a selector 7. Namely, once the value is written in the register 5 by the CPU, the same value is reset in the display controller without being set in the register 5.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] This BA relates to a display control device that sends display signals to five display devices based on data written in a display memory.

[Conventional technology]

FIG. 2 is a block diagram showing the configuration of a display control device using a conventional display memo IJ. In the figure, [1) l
d ff indicator address counter f2) Iri display memory, (3) is display interface 14) idcPU interface 15H-t memory write address register, (
6) is the 1 addition circuit, and (7) is the CPU interface (4
) Shows a selector that switches between the address information of L and 9 and the output of the 1 addition circuit (6).

Next, the operation will be explained. Indication 7)”L
The /scanter (1) supplies a display address to the display memory (2) while sequentially updating the address value. Display the data for the address given in January 2).
p-y ace (31K feed 1 display interface (3)
A display signal suitable for the display device is generated and sent to the display device.

Data is written by specifying the CPU address in the content to be displayed, and this is done in the following steps.

Maf, CPU engineer! 1) The initial value of the memory write address register 1511c is set through the CPU interface (4) 1, , 7).

After that, in the display memo January 2), writing to the address held in the memory write address register (5) is
This is done via the P interface (4).

Generally, writing of data to one display memory (2) is often performed successively to consecutive addresses. In this case, each time the memory write address register (
Therefore, the output of the memory write address register (5) is actually performed immediately after the write operation to the display memo 1/2) is performed. It is assumed that 1 is added to the address value through the arithmetic circuit (6), and this n is passed through the selector (7) to be reset to the memory write address register (5).

If you do this, every time you write to the memory write address register (
It is possible to write to the display memo 2) to consecutive addresses without updating the CPU 5).

An example of one result during this control will be shown below according to the diagram. In FIG. 3, (8) the display surface of the u display device, (9a), (9b
).

(9c) and (9d) respectively indicate display characters displayed on the n display surface (8). FIGS. 4(a) to 4(d) are memory maps showing the allocation of display memos (January 2) when display characters (9a) to (9d) are displayed.

First, the procedure for displaying four characters as shown in Figure 3 is as follows.

The address n of the first display memo (January 2) corresponding to a predetermined position on the display surface (8) is first set in the memory write address register (5). Thereafter, the character code corresponding to the CPU 1 display character (9a) is written into the display memory (2) via the CPU interface (4).

Figure 4 fa) shows the state of the display memo January 2) at this time. Next, set the contents of the memory write address register (5) to 1.
Add only. This is the memory write address register (
5) Contents of 217Jo! Circuit (6) and selector (η
Resetting the memory write address register (5) through the VCL can be performed without CPU intervention.

At this time, the character code corresponding to the CPUL5 display character (9b): 1 is written in the display memo (January 2) via the CPU interface (4).

FIG. 4(b) shows the state of the display memory (2) at this time. After writing, the contents l of the memory write address register (5) are added in the same manner as above.

After that, the same collection is repeated to display the characters (9c).

1%) is written into the display memory (2), and the contents of the display memory (2) are shown in Figure 4 (d).
), the display will be as shown in Figure 3.

In recent years, display devices have become more than just computer terminals.

As they are used in a variety of fields, display methods are also becoming more diverse.An example is partial blinking. This is to flash a certain area of the display at regular intervals, and is performed by the following method @VC.

Consider the case where 1 display characters (9c) and (9d) are displayed blinking in the display of FIG. Figure 5 (a), (b)
is a memory map showing the allocation of the display memo 2) in this case.

The address of the display memory (2) corresponding to the first character (9c) to be blinked is set in the memory write address register (5) via the CPU interface (4).

Next, 1 display memory + 21 K display characters (9c1. r
Write the character code corresponding to 9d) into the memory for full display (2).

Figure 5 (a) shows the state of the display memory (2) at this time. After a period of time, the address of the first character to be blinked is set again in the memory write address register (5), and this time Display characters (9C1 (9) in display memory (2)
Write the blank character code to the address set in d).

FIG. 5(b) shows the state of the display memory (2) at this time. By repeating the above-mentioned sampling, a blinking display can be made.

FIG. 6 is a front view showing the display surface (8) when the display characters (9c) and (9d) are turned off when the display characters (9c) and (9d) are blinked.

Since the above display is repeated alternately, a blinking display is realized.

[Problems that the invention aims to solve]

Since the conventional display control device has the above-mentioned configuration, when performing a production in which the same part of the memory for one display is repeatedly updated, such as when one display character is made to blink,
There is a problem in that it is necessary for the CPU to reset the memory write address register each time, which places a heavy burden on the CPU.

The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a display control device that can reduce the CPU load when updating a specific portion of one display memory.

[Means to solve the problem]

The display control device according to the present invention VC writes the contents of the memory write address save register and the memory write address save register to the memory when settings are made to the CPU EX memory write address register. A means for transferring data to an address register is added.

[Effect] When it is necessary to reset the value of the memory write address register in the display control device according to the present invention, the address information stored in the memory write address register vc and the memory write address storage register is directly transferred to the memory write address register. O written in 〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, fil-(7) is the same as that shown in the conventional example of FIG. 2, so the explanation will be omitted.

αI is a memory write address storage register that stores the contents when writing is performed to the memory write address register (5) via the CPU pcPU interface (4). Selector (7) is CPU interface f4)! The output of the adder circuit (6) and the memory write address storage register (Ql) is switched between the new address information and the output of the l adder circuit (6) and the memory write address storage register (Ql).

Next, the operation will be explained. Display character (9c) among display characters (9a) to (9d) shown in the conventional example of FIG.

When performing the blinking display of (9d), it can be realized by the following adaptation.0 Display memo corresponding to the first character (9c) to be blinked first January 2) Address 2 CPU Ex CPU interface (4) k Memory via Write address register (5
).

At this time, the value of that address is simultaneously written into memory write address storage register αGK.

Next, display characters (9c), (9
Write the character code corresponding to d) into the display memory (2). The procedure up to this point is the same as in the conventional example.

Next, in order to turn off the light, the address value of the first display character (9C) to be blinked is reset in the memory write address register (5), but at this time, the contents of the memory write address save register OO are set in the selector. (7), it can be transferred to the memory write address register (5).

That is, when the p-degree CPU EX memory write address register [51iC value is written, which is different from the conventional method shown in FIG.
When resetting, the resetting process can be performed within the display control device without setting a value in the CPU memory write address register (5), and the processing load on the CPU side is reduced.

Various methods can be used to control the selector (7) that changes the settings for the memory write address register (5).

For example, the CPU interface (4
), when setting a value to the memory write address register (5), the CPU interface (4
) When setting the data of F in the memory write address register (5) and setting the character code in the display memo 2) via the CPU interface (4), the value of the most significant bit of the character code. After writing the character code, the input to the memory write address register (5) is added to the 1 addition circuit (6) or the memory write address storage register (I
There is a way to switch to either G.

〔Effect of the invention〕

As described above, according to the present invention, one display control device Kj? By providing a write address storage register that stores the value set by the CPU as it is in the write address register, and a means for transferring the contents of the write address storage register to the write address register, This has the advantage that various display methods can be realized without significantly increasing the load on the CPU.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a display control device according to an embodiment of the present invention, FIG. 2 is a block diagram showing the configuration of a conventional display control device, and FIG. 3 is a front view showing a conventional display surface. 4(a) to 4(d) are memory maps showing the display memory allocation when displaying the display characters shown in FIG. 3, and FIGS. 5(a) and 5(b) are the display in FIG. 3. FIG. 6 is a memory map showing the allocation of display memory when characters are blinked. FIG. 6 is a front view showing the display surface when the lights are turned off when characters are blinked. In the figure, 11) #: Displays address counter, (
2) is the display memory, (3) is the display interface, (
4) CPU interface, f5) ri memory write address register h (6) riJ 21D arithmetic circuit,
171rj-t=tz vector, 01ri, +Z memory write address storage register. In addition, in Figure 1, the same symbols are the same, or 7? : indicates the corresponding part.

Claims (1)

[Claims] In a display control device that writes data to a display memory from a CPU and performs display based on that data, the CPU
A memory write address register that specifies the address to be written to the display memory from U, and a memory write address storage register that stores the value set by the CPU for the memory write address register as it is. ,
A display control device comprising means for transferring the contents of the memory write address storage register to the memory write address register.