JPH0472937A - Fault diagnostic device - Google Patents

Abstract

PURPOSE:To attain accurate fault diagnosis even when signal collision takes place by monitoring a data sent through a signal transmission line, fetching the signal at a latter half of a frame and comparing the amplitude of the signal with a reference threshold level of the signal amplitude. CONSTITUTION:When a timing generating circuit 61 detects an SOM of a data frame on a bus 11, a pulse of a prescribed pulse width is outputted to a switch circuit 62 in a prescribed timing at a latter half of one frame and the switch circuit 62 is closed for a time of the pulse width only. A sample-and-hold circuit 64 samples and holds the signal amplitude and comparator circuits 66, 67 compare the signal amplitude subject to sampling and holding as above with reference voltages Vref1, Vref2 and outputs the result of comparison to a CPU 70. The CPU 70 applies fault diagnosis based on a signal inputted from the comparator circuits 66, 67.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a data transmission system that transmits data between nodes connected to a common signal transmission path, and particularly relates to a fault diagnosis for detecting a failure in a data transmission system. Regarding equipment.

(Prior Art) Conventionally, data transmission systems using this type of failure diagnosis device include C3MA/CD (Carrier 5ence).
Multi-ple Access/Co11isi
LAN (Loca on Detection)
l Area Network). For example, a typical example is PAL, which is used for data transmission in cars.
MNET (Protocol for Automotive)
tive Low and Medium speed
The above-mentioned data transmission system transmits data by time division multiplex communication between a plurality of nodes via a common signal transmission path (data bus) such as twisted pair electric wires.

By the way, in such a system, if the transmission function of the source node fails or if one or more of the bias circuits installed on the network that set the potential of the data bus is defective, one of the bias circuits that sets the potential of the data bus The amplitude of the signals on the data bus may be larger or smaller than the normal signal amplitude range.

In view of this, conventional fault diagnosis devices capture signals on the data bus, detect their amplitudes, and diagnose the occurrence of faults based on the signal amplitudes.

(Problem to be Solved by the Invention) However, in the above-described system, when a signal collision occurs, a signal with a high priority set in advance in the network is used, for example as shown in FIG. 9(a). and the ninth
When there is a collision with a low-priority signal as shown in Figure 9(b), the signal current on the signal transmission path increases, resulting in a collision with a low-priority signal as shown in Figure 9(C). The signal amplitude will also increase until the transmission of the low signal ceases.
The fault diagnosis device has a problem in that unless the position at which the signal amplitude is detected is specified, a fault is diagnosed based on the increased signal amplitude, even though normal data transmission is possible.

The present invention has been made in view of the above-mentioned problems, and an object of the present invention is to provide a fault diagnosis device that can perform accurate fault diagnosis even when signal collision occurs on a data bus.

(Means for Solving the Problems) In order to achieve the above object, in the present invention, at least two nodes are connected to a signal transmission line that performs data transmission, and the amplitude of a signal input from the signal transmission line is The fault diagnosis device detects a failure according to the signal transmission path, and the signal acquisition means monitors the data transmission of the signal transmission path and takes in the signal of the signal transmission path at a predetermined timing according to the monitoring result; A fault diagnosis device is provided, wherein a threshold value is set, and includes an amplitude comparison means for comparing the threshold value and the amplitude of the captured signal, and a fault detection means for detecting a fault according to a comparison result of the amplitude comparison means. provided.

(Operation) The data transmitted through the signal transmission path is monitored, a signal is captured in the latter half of the frame, and the amplitude of the signal is compared with a reference signal amplitude threshold.

Therefore, even if a signal collision occurs, it is possible to diagnose a failure by detecting the amplitude of the signal after the conflict area in the frame.

(Example) Hereinafter, an example of the present invention will be described in detail based on the drawings of FIGS. 1 to 8.

FIG. 1 shows a fault diagnosis apparatus for a multiplex transmission system as an embodiment of the present invention. In this embodiment, the failure diagnosis apparatus of the present invention is used as a failure diagnosis apparatus for a multiplex transmission system for a vehicle. This multiplex transmission system is a distributed automotive LAN in the form of a bus, and employs asynchronous time division multiplexing such as a contention method that allocates the right to use the transmission path only when there is a message to be sent to each node. The C3MA/CD method is adopted as the access control method (multiplex method). In addition, as shown in Figure 2, PWM codes and bit-fuzz arbitration are used, so if a data collision occurs, only the data with the highest priority will survive and be sent, as shown in Figure 9. continues.

In Figure 1, ■ indicates two signal lines 11 (or bus)
It is a balanced bus transmission line consisting of 11 and 12 buses, and each bus 11.
12 are biased to a predetermined voltage level by bias resistor circuits Rtl and R22, and R23 and R24, respectively. 2 is a failure diagnosis device, 3 to 5 are communication nodes, and 3 to 5 are bus interface units 31 and 4, respectively.
1.51 to access the transmission signal to the transmission line 1.

FIG. 3 shows an example of the configuration of the bus interface section 21. As shown in the figure, the transmitter includes buses 11 and 1 of transmission line 1.
A differential driver circuit 211 that sends a transmission signal using 2
The differential driver circuit 211 performs transmission so that the polarity of the transmitted signal is inverted between the buses 11 and 12.

That is, the differential driver circuit 211 transmits a PWM digital signal to the bus 11 using a constant bias voltage determined by the bias resistor circuits L+ and R22 and a reference voltage V11. A signal obtained by inverting the above-mentioned PWM digital signal is transmitted using a constant bias voltage determined by bias resistor circuits R23 and R24 and a signal V12 as a reference.

The receiving section includes an AC coupling section 212 that cuts the DC pipe portion of the received signal from the transmission path 1, a differential amplifier 213 that amplifies the output of the AC coupling section 212, and a predetermined threshold voltage V.
+ h, and a comparator 215 that outputs an output signal to the communication IC 24.

Even if the signal amplitude of the received signal received from the transmission line l by the differential amplifier 213 becomes small due to a failure or the like, as will be described later, the comparator 215 is configured to detect this if the signal amplitude is greater than or equal to a predetermined value Vlh. The signal is converted back into a digital signal at a constant voltage level and sent to the CPU 23, thereby allowing the CPU 23 to read the received signal without error.

FIG. 4 shows a more detailed example of the configuration of the electric circuit of the receiving section of the bus interface section 21. As shown in the figure, this embodiment is a bus interface circuit of a balanced transmission system using an A/C coupling circuit 212 with capacitors Ca and C4. Even if there is no other bus, data can be received using only the other bus signal.

In the figure, resistor R11, capacitor Cs, and resistor R+
2 and capacitor C6 each constitute a filter that cuts high frequency components of the bus signal.

Diode D8 prevents fluctuations in the DC component due to the duty ratio of the bus signal pulse, and also reduces the forward voltage VDF.
The differential reception sensitivity of the receiving circuit is set. The diode D9 protects the input terminal of the comparator 215 by absorbing positive surges and negative surges of the bus signal. Resistors R+3, R+4, R+5, Rha, and Rha set the differential reception sensitivity and hysteresis of the comparator 215.

The base voltage and emitter voltage of the transistor T r are always shifted by approximately the pace emitter voltage vBE, and since it is connected to the emitter follower circuit, the input impedance on the base side of the transistor T r is high, and the signal transmission speed is also sufficient. It is fast. Therefore, even if the transistor T r s is inserted into only one of the balanced transmission lines, neither the time balance of the received signal nor the impedance balance of the bus interface receiving circuit is lost.

The emitter follower circuit of the transistor Tra also serves to prevent the inverting input terminal (-) of the comparator 215 from going negative. This is the transistor Tra
By inserting this into the bus interface receiving circuit, even if a negative voltage lower than the pace-emitter voltage VBE when the collector of the transistor Trs is open is input to the base, the transistor T r a will be in the off state, and the inverting input terminal of the comparator 215 will be turned off. This is because the voltage does not fall below ground. The diode D1° is for preventing the positive surge voltage that enters from the base of the transistor Trs from passing through to the collector and being applied to the power supply.

That is, FIG. 5 shows the signal waveform on the bus 11, and FIG. 6 shows the signal waveform on the bus 12. In each figure, (a) is normal, (b) and (C)
is the signal waveform when the bus interface section of the source node fails. The relationship between the signal amplitude values at the time of failure is as follows.

Vl >V2 >V3 V4 >VB >Vl FIG. 7 is a block diagram showing the configuration of the failure diagnosis device according to the present invention. In the figure, the timing generation circuit 61 connected to the data bus IO is connected to the buses 11 and 1.
2, and detects the SOM (see Figure 9), which is the start bit of the signal frame on buses 11 and 12, and as shown in Figure 8(b), Pulses are output to switch circuits 62 and 63.

The switch circuits 62 and 63 are on/off controlled by the timing generation circuit 61, and when the timing generation circuit 61 outputs the above pulse, the switch circuits 62 and 63 are turned on and off.
．． 63 is turned on according to the control of the timing generation circuit 61 and connects the bus 11, the sample hold circuit 64, and the bus 1.
2 and the sample hold circuit 65 are connected. for example,
When the timing generation circuit 61 detects the SOM of the signal frame on the bus 11, the switch circuit 62 is turned on, and when the timing generation circuit 61 detects the SOM of the signal frame on the bus 12, the switch circuit 63 is turned on. Ru.

The sample and hold circuits 64 and 65 are switch circuits 62
．． When 63 is turned on, it takes in signals from buses 11 and 12, samples and holds the signal amplitudes of the signals, and outputs them to comparison circuits 66 to 69 such as comparators.

The comparison circuits 66 to 69 compare the signal amplitude of each signal with the reference voltage, and the comparison circuits 66.68 and 67.69
A reference voltage Vref 1 indicating the upper limit of the signal amplitude and a reference voltage Vref 2 indicating the lower limit of the signal amplitude from a reference voltage generating section (not shown) are input to one input terminal of the signal amplitude (
voltage) and outputs the result to the control circuit (CPU) 70. In the embodiment, the comparator circuits 66, 68 include:
If the signal amplitude of the signal sampled and held is input to the + side input terminal, and the reference voltage Vref 1 is input to the − side input terminal, and the signal amplitude is lower than the reference voltage Vref '1, for example, the signal amplitude is low level. outputs a signal. Further, the comparison circuits 67 and 69 have the reference voltage Vref 2 inputted to the + side input terminal and the signal amplitude of the sampled and held signal inputted to the − side input terminal, and the signal amplitude is inputted to the reference voltage Vref 2 If it is higher, for example, a low level signal is output.

The CPU 70 performs failure diagnosis based on output signals that are the comparison results input from the comparison circuits 66 to 69, and detects the occurrence of a failure.

The display device 71 performs display operations under the control of the CPU 70, and displays data such as diagnosis results from the CPU 70 on the display screen.

Next, the operation of fault diagnosis by the fault diagnosis device according to the present invention will be explained.

First, when the timing generation circuit 61 detects the SOM of the data frame on the bus 11, as shown in FIG. A pulse with a predetermined pulse width is outputted to the switch circuit 62 at a predetermined timing in the second half of the one frame, and the switch circuit 62 is turned on for a time corresponding to the pulse width.

When the switch circuit 62 is turned on, the sample and hold circuit 64 samples and holds the signal amplitude, and the comparison circuit 6
6.67 compares the sampled and held signal amplitude with the reference voltages Vref 1 and Vref 2, and outputs the comparison result to the CPU 70. The CPU 70 is a comparison circuit 6
Fault diagnosis is performed based on the signals input from the bus 11, and in the embodiment, when the signals input from both the comparison circuits 66 and 67 are both low level, the amplitude of the signal from the bus 11 is Reference voltage Vrefl, Vr which is a threshold value
Since it is within the range of ef2, it is diagnosed that the data transmission is normal without any failure, and if either of the signals input from both comparison circuits 66 and 67 is at a high level, the signal from bus 11 is Reference voltage Vref whose amplitude is a threshold value
1. Since it is outside the range of Vref 2, it is diagnosed that a failure has occurred, and the diagnosis result is displayed on the display device 71. Also, when the SOM of the data frame on bus 12 is detected, the same fault diagnosis operation as above is performed, and
Reference voltage Vref 1 whose threshold is the amplitude of the signal from 2
, Vref 2, the failure is diagnosed.

Therefore, in this embodiment, as shown in FIG. 8, the timing generation circuit 61 captures the signal on the signal transmission path in accordance with the pulse output in the latter half of one frame of the signal and compares it with the reference voltage. Even if signals are output from different nodes to the signal transmission paths 11 and 12 at the same time and a collision occurs between the signals, the amplitude of the signal can be detected after the contention area in the frame and the failure can be diagnosed. transmission failures can be detected accurately.

(Effects of the Invention) As explained above, in the present invention, at least two nodes are connected to a signal transmission path that performs data transmission, and a failure occurs depending on the amplitude of a signal input from the signal transmission path. The fault diagnosis device for detecting includes a signal acquisition means for monitoring data transmission on the signal transmission line and acquiring a signal on the signal transmission line at a predetermined timing according to the monitoring result, and a signal amplitude threshold that is different from each other by 4 degrees. The present invention includes an amplitude comparing means for comparing the set threshold value with the amplitude of the captured signal, and a failure detecting means for detecting a failure according to the comparison result of the amplitude comparing means. Accurate fault diagnosis can be performed no matter what state the signal is in.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a multiplex transmission system using a fault diagnosis device according to the present invention, FIG. 2 is a diagram showing bit-fiz arbitration adopted in the multiplex transmission system according to the present invention, and FIG. 3 is a bus interface. FIG. 4 is a more detailed circuit diagram of the receiving section of the bus interface section shown in FIG. 3, FIGS. 5 and 6 are diagrams showing signal waveforms on each bus, and FIG. 8 is a block diagram showing the configuration of the fault diagnosis device according to the present invention, FIG. 8 is a diagram showing the relationship between signals in various states on the data bus and output pulses, and FIG. 9 is a diagram showing the relationship between signals in various states on the data bus and output pulses. FIG. FIG. 3 is a diagram showing signal waveforms when 11.12...Signal transmission path (bus), 61...Timing generation circuit, 62.63...Switch circuit, 64
゜65...Sample hold circuit, 66-69...
Comparison circuit, 70... Control circuit (CPU), 71...
・Display circuit.

Claims (1)

[Claims] A fault diagnosis device that is connected to a signal transmission line that is interposed between at least two nodes and that performs data transmission, and that detects a failure according to the amplitude of a signal input from the signal transmission line, A signal capturing means monitors and captures the signal of the signal transmission line at a predetermined timing according to the monitoring result, and a signal amplitude threshold that is different from each other is set, and the threshold value and the amplitude of the captured signal are compared. A failure diagnosis device comprising: amplitude comparison means; and failure detection means for detecting a failure according to a comparison result of the amplitude comparison means.