JPH0469900A - RAM with diagnostic function - Google Patents

Abstract

PURPOSE:To shorten the diagnosis time of a RAM by incorporating a means which writes the same data in all addresses with one write operation and a means which reads out the identity of data in all addresses with one read operation in a RAM as the diagnostic function. CONSTITUTION:Data from a column input/output controller 5 is transmitted to an external data signal at the time of read, and the external data signal is transmitted to the controller 5 at the time of write. A row test decoder 7 and a column test decoder 8 permit the signal values from a row address decoder 2 and a column address decoder 3 to pass through, and one memory cell of a memory matrix 6 is selected. At the time of test, all memory matrix 6 are selected independently of signal values of decoders 2 and 3 by decoders 7 and 8. A read/write controller 1 subjects all selected memory cells to the processing corresponding to a read/write control signal and a chip select signal; and at the time of read, the identity of data is verified by an EOR tester 40 in a data input/output buffer 4. Thus, the diagnosis time of the RAM is shortened.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to diagnostic functions in RAM.

[Background Art] In recent years, computer systems have been widely applied in various fields. In this computer system, data necessary for processing is stored in the RAM.

Therefore, RAM needs to be highly reliable to prevent improper processing, and at the same time, RAM needs to be highly reliable to prevent RAM failures.
Diagnosis of M is necessary.

However, conventional RAM is manufactured by Hitachi, Ltd.
No consideration was given to one diagnosis as shown in the block diagram on page 199 of Memory Data Book (1989). Therefore, in a computer system,
A microcomputer etc. can write/write to all addresses in RAM.
Diagnosis of RAM was performed by after-read.

[Problems to be Solved by the Invention] However, in recent years, as the performance of computer systems has improved, memory capacity has increased, and there has been a problem that the time required for diagnosis thereof has increased.

An object of the present invention is to provide a RAM with a diagnostic function that allows RAM to be diagnosed in a short time.

[Means for Solving the Problems] In order to achieve the above object, the present invention provides a means for writing the same data to all addresses in one write operation, and a means for reading the sameness of data in all addresses in one read operation. This means is built into the RAM as a diagnostic function.

[Function] Since the present invention has a diagnostic function built into the RAM, all addresses in the RAM can be diagnosed with a single write-after-read process.

[Example] An example of the present invention will be described below with reference to FIGS. 1 and 2.

FIG. 1 shows a block diagram of a RAM according to an embodiment of the present invention.

Block 1 is read/write controller, block 2
is a row address decoder, block 3 is a column address decoder, block 4 is a data input/output cover sofa, block 5 is a column input/output controller, and block 6 is a memory matrix.

Further, block 7 is a row test decoder, block 8 is a column test decoder, and block 40 is an E○R tester.

In a normal read/write sequence, the row address decoder 2 and column address decoder 3 select one memory cell in the memory matrix 6 corresponding to the input value of the address signal. Further, the read/write controller 1 creates a read control signal and a write control signal from the chip select signal, read signal, and write signal, and the data input/output cover sofa 4 receives these signals.

Controls the direction of data flow between the external data signal and the column input/output controller 5. Specifically, at the time of reading, data of a selected memory cell in the memory matrix 6 is read out to the outside.

The data from the column input/output controller 5 is transmitted to an external data signal. On the other hand, at the time of writing, in order to write external data into a selected memory cell in the memory matrix G, an external data signal is transmitted to the column input/output controller 5.

In this sequence, the test signal is set to “0”, so
Row test decoder 7 and column test decoder 8 select one memory cell of memory matrix 6 by passing signal values from row address decoder 2 and column address decoder 3, respectively.

Next, in the read/write sequence during testing, the test signal is 1n, so the row test decoder 7 and column test decoder 8 perform memory Select all memory cells in matrix 6. In addition, the read/write controller 1 performs processing corresponding to read/write control signals and chip select signals.
Perform this on all selected memory cells.

When reading this sequence, the EOR tester 40 in the data input/output buffer 4 also verifies the identity of the data.

Next, the principle of data identity verification by the EOR tester 40 will be explained with reference to FIG.

FIG. 2 shows the identity verification principle of one embodiment of the present invention.
Here, a diagnosis of RAM by writing/after-reading data value "1" to a memory of 4 words x 1 bit (2 x 2 memory matrix) will be explained.

In addition, along with the write sequence and read sequence,
Select all memory cells. Specifically, the row word lines (RW□, RW,) and column word lines (cwl, cw
, ) to the signal value “High”, that is, the transistors (Q L 1- Q −, Q-□.

Q 41y Q+a+ Qxxv Qsz+ Q<x+
T□□, T2Ll'rtx, Txx) are turned on.

First, the flow of data during a write sequence will be explained.

Since the data value to be written is “1”, the D line is ttHigh.
”, the D line becomes “Low”, thereby “L o
The transistor on the D line side (Q4゜Q z
x t Q s x s Q 4 x ) is on, so the contact (N x , N z −N
a , N 4 ) are “Low”, so the transistor (Q t s + Q 1 s g Q s t ).

Q48) becomes off, the contacts (N, N, N3゜N4) become "High h", and the contacts (N□
.

Since Ns, Na-N4) is "High", the transistors (Q, , Q, , Q, Q, 4) are turned on, and writing of the data value "1" is completed.

Next, the flow of data during a read sequence will be explained.

The data value to be read is “1”, that is, the contact (N x,
Since N z , Na −N *) is “High”, the transistors (Q 14.Q −4IQ −4,
Q-4) is on. In addition, a transistor (Q
txtQxxIQ,,,Q4. ) is also on. Therefore, the D registers (Q, , , Q, , , Q, , , Q,
, ), Transistor (Q, ,,Q,4.Q, ,,Q
4. ), the D line becomes "High" and the D line becomes "Low".

Furthermore, the EOR tester 40 in the data input/output buffer 4 extracts the identity of these signal values, and outputs the resulting data value "1" as a read data value.

Specifically, in F/F, DIIA is “High” and D
Since the line is "Low", "High" is output as the original data. - On the other hand, in ENOR, the D line is “High”
”, the D line is “Low”, so “Low”’ is output as a fault signal. Then, in FOR OR, the fault signal is L
0w", the original data "Hi g )]" is passed through, and the data value "1" is output as the read data value.

However, if the data value of (memory cell 1) becomes "0" due to a failure in the RAM, the signal value "High" is set in advance.
The charge on the D line side precharged to DIIA,
Transistor (Q, L), Transistor (Q, I)
Discharge via. Therefore, of course the D line,
Even the D line becomes "Low".However, between the D line and the D line, the D line has more transistors connected in parallel, which is the discharge resistance of the charge, so the total discharge resistance of the D line is higher. The time constant RC (R', resistance value, C:
The capacitance value) is also smaller for the D line. Therefore, in terms of time, the D line is smaller.
The line goes “Low” and after a delay, Di goes “L”.

w”.

Furthermore, the EOR tester 40 in the data input/output buffer 4 extracts the identity of these signal values, and outputs the resulting data value "0" as a read data value.

Specifically, in the F/F, the D line becomes "Low", and after a delay, the D line becomes 50wH, so "High" is output as the original data. On the other hand, in ENOR, the D line and Di are "Low", so II High
Outputs hII as a failure signal. Then, in FOR, the fault signal is “High”, so 1 original data “H”
i gh 17 is inverted and the data value 110'' is output as the read data value.

In this embodiment, the data on the D line and the D line are checked for identity (ENOR matching circuit in Figure 2), and this is reflected in the data and taken out to the outside, but the data on the D line and the D line are identical. You can directly take out the items that have been checked for gender.

In addition, in this embodiment, RAM diagnosis by write-after-read of data value 11111 was explained.
The same applies to RAM diagnosis by write-after-read of data value 110 II.

Further, in the second embodiment, a single RAM has been described, but the present invention can of course be similarly applied to a memory system using a plurality of RAMs. At this time, whether to perform RAM diagnosis by writing/after-reading all RAM cells at the same time on all RAM cells at once or dividing it into individual blocks depends on the method of creating the chip select signal. Can be controlled.

According to this embodiment, all addresses of the RAM can be diagnosed with one write-after-read process.

[Effect of the invention] According to the present invention, RAM diagnosis time can be shortened.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a RAM according to an embodiment of the present invention, and FIG. 2 is an explanatory diagram showing the identity verification principle of an embodiment of the present invention. 1... Read/write controller, 2... Row address decoder, 3... Column address decoder. 4...Data input/output buffer, 5...Column input/output controller, 6...Memory matrix, 7...
Row test decoder, 8... Column test decoder,
40...EOR tester. Figure 1 Figure 2

Claims (1)

[Claims] 1. A RAM capable of random access, characterized by including means for writing the same data to all addresses in one write operation, and means for verifying the identity of data at all the addresses in one read operation. RAM with diagnostic function.