JPH0469428B2 - - Google Patents
Info
- Publication number
- JPH0469428B2 JPH0469428B2 JP58119329A JP11932983A JPH0469428B2 JP H0469428 B2 JPH0469428 B2 JP H0469428B2 JP 58119329 A JP58119329 A JP 58119329A JP 11932983 A JP11932983 A JP 11932983A JP H0469428 B2 JPH0469428 B2 JP H0469428B2
- Authority
- JP
- Japan
- Prior art keywords
- conductor pattern
- transparent
- wiring board
- layer
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004020 conductor Substances 0.000 claims description 43
- 239000004065 semiconductor Substances 0.000 claims description 32
- 239000000758 substrate Substances 0.000 claims description 12
- 238000010030 laminating Methods 0.000 claims 1
- 239000010410 layer Substances 0.000 description 27
- 238000000034 method Methods 0.000 description 6
- 239000011521 glass Substances 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 239000012212 insulator Substances 0.000 description 4
- 239000012780 transparent material Substances 0.000 description 4
- 239000004593 Epoxy Substances 0.000 description 3
- NIXOWILDQLNWCW-UHFFFAOYSA-N acrylic acid group Chemical group C(C=C)(=O)O NIXOWILDQLNWCW-UHFFFAOYSA-N 0.000 description 3
- 229910000679 solder Inorganic materials 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- 229910006404 SnO 2 Inorganic materials 0.000 description 1
- 239000012790 adhesive layer Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 230000003064 anti-oxidating effect Effects 0.000 description 1
- 229910010293 ceramic material Inorganic materials 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 238000012790 confirmation Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/818—Bonding techniques
- H01L2224/81801—Soldering or alloying
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/303—Surface mounted components, e.g. affixing before soldering, aligning means, spacing means
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4673—Application methods or materials of intermediate insulating layers not specially adapted to any one of the previous methods of adding a circuit layer
- H05K3/4676—Single layer compositions
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
- Led Device Packages (AREA)
- Light Receiving Elements (AREA)
Description
【発明の詳細な説明】
〔発明の技術分野〕
この発明は、フエイスダウンボンデイングを用
いた半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor device using face-down bonding.
半導体素子を搭載し、素子相互間を接続する方
法の一つとして、フリツプチツプボンデイングに
代表されるフエイスダウンボンデイングが知られ
ている。これは素子の電極端子を半田バンプを用
いて配線基板上の導体パターンに直接接続する方
法であり、ワイヤボンデイング等に比べ電極端子
と導体パターンとの間がワイヤの如き熱圧着接続
ではなく、半田の溶解により接続されるため、信
頼性にすぐれ、また一つの素子と配線基板上の導
体パターンとの接続が電極端子の数に関係なく一
度でできる等の特長がある。
Face-down bonding, typified by flip-chip bonding, is known as one of the methods for mounting semiconductor elements and connecting the elements to each other. This is a method in which the electrode terminals of the element are directly connected to the conductor pattern on the wiring board using solder bumps. Compared to wire bonding, etc., the electrode terminal and the conductor pattern are not connected by thermocompression bonding like wires, but by soldering. Since the connection is made by melting, it has excellent reliability, and has the advantage of being able to connect one element to the conductor pattern on the wiring board in one go, regardless of the number of electrode terminals.
しかしながら、フエイスダウンボンデイングで
はボンデイング時に素子の電極端子形成面が基板
側を向くため、電極端子およびこれが接続される
導体パターン上の接続部がよく見えない。そこで
従来では半透鏡を用いて接続部を確認しながら、
素子と導体パターンとの位置合せを行なつてい
た。従つて位置合せを含めたボンデイング工程に
長時間を要するという問題があつた。 However, in face-down bonding, the electrode terminal forming surface of the element faces the substrate side during bonding, so that the electrode terminal and the connection portion on the conductor pattern to which it is connected cannot be clearly seen. Therefore, in the past, while checking the connection using a semi-transparent mirror,
The elements and conductor patterns were aligned. Therefore, there was a problem in that the bonding process including alignment required a long time.
この発明の目的は、フエイスダウンボンデイン
グに際し半導体素子と配線基板上の導体パターン
との位置合せが容易で、量産性にすぐれた半導体
装置を提供することにある。
An object of the present invention is to provide a semiconductor device that allows easy alignment of a semiconductor element and a conductor pattern on a wiring board during face-down bonding and is highly suitable for mass production.
この発明は、配線基板の絶縁性基体およびその
上に被着形成される導体パターンをいずれも透明
材料により形成することによつて、基板の裏面側
から半導体素子の電極端子と導体パターンとの接
続部が確認できるようにしたものである。
In this invention, the insulating base of the wiring board and the conductive pattern formed on the insulating base are both made of a transparent material, so that the electrode terminal of the semiconductor element and the conductive pattern can be connected from the back side of the board. This information has been made available for confirmation by the department.
この発明によれば、半導体素子と配線基板上の
導体パターンとの位置合せを半透鏡等を用いるこ
となく極めて容易、確実に行なうことができる。
すなわち、この発明では透明材料からなる絶縁性
基体および導体パターンを通して半導体素子の電
極端子を光学的に観察でき、また導体パターンの
厚さによる導体パターン表面と下地（絶縁性基体
や絶縁層）表面との段差により、導体パターンの
輪郭（端面）を光学的に認識できることから、半
導体素子の電極端子と導体パターンとの接続個所
を確認しつつ、位置合わせを行うことが可能とな
る。従つてフエイスダウンボンデイング本来の特
長と相まつて、非常に量産性がよく製造コストの
低い半導体装置を提供することが可能である。
According to the present invention, it is possible to extremely easily and reliably align the semiconductor element and the conductor pattern on the wiring board without using a semi-transparent mirror or the like.
That is, in this invention, it is possible to optically observe the electrode terminals of a semiconductor element through an insulating substrate made of a transparent material and a conductor pattern, and also to distinguish between the surface of the conductor pattern and the surface of the base (insulating substrate or insulating layer) depending on the thickness of the conductor pattern. Because the contour (end surface) of the conductor pattern can be optically recognized by the step, it is possible to perform alignment while confirming the connection point between the electrode terminal of the semiconductor element and the conductor pattern. Therefore, in combination with the inherent features of face-down bonding, it is possible to provide a semiconductor device that is highly mass-producible and has low manufacturing costs.
また、半導体素子の電極端子を導体パターンの
最適な位置に精度よく位置合わせすることが可能
となるために、半導体素子の接続不良をなくし、
歩留りを高くすることができる。 In addition, since it is possible to accurately align the electrode terminals of the semiconductor element to the optimal position of the conductor pattern, connection failures of the semiconductor element can be eliminated, and
Yield can be increased.
さらに、この発明によれば半導体素子が発光素
子や受光素子の場合、基板側に発光面や受光面を
向けることができるという利点がある。すなわ
ち、従来では発光または受光素子に関してはフエ
イスダウンボンデイングによる実装は不可能とさ
れていたが、この発明では基板および導体パター
ンがいずれも透明材料であることにより光の通過
を妨げないので、基板側から発光させたり受光す
ることが可能となる。 Further, according to the present invention, when the semiconductor element is a light emitting element or a light receiving element, there is an advantage that the light emitting surface or the light receiving surface can be oriented toward the substrate side. In other words, in the past, it was considered impossible to mount light-emitting or light-receiving elements by face-down bonding, but in this invention, since both the substrate and the conductor pattern are made of transparent materials, the passage of light is not obstructed. It becomes possible to emit light from and receive light from it.
第１図はこの発明の一実施例に係る半導体装置
の断面図である。
FIG. 1 is a sectional view of a semiconductor device according to an embodiment of the present invention.
図において、配線基板１はこの例では絶縁性基
体２上に第１層導体パターン３、絶縁体層４およ
び第２層導体パターン５を順次形成した２層の配
線基板である。第１層、第２層の導体パターン
３，５は、絶縁体層４に形成したスルーホールを
通して適宜接続されている。ここで、絶縁性基体
２はポリマーガラス、プラスチツク、サフアイヤ
等の透明セラミツク材料によつて形成されてい
る。また、導体パターン３，５はITO、SnO2等
の透明良導体により形成されている。さらに、絶
縁体層４もアクリル、エポキシ、シリコン等から
なる透明絶縁材料から形成されている。 In the figure, a wiring board 1 in this example is a two-layer wiring board in which a first layer conductor pattern 3, an insulator layer 4, and a second layer conductor pattern 5 are sequentially formed on an insulating base 2. The conductive patterns 3 and 5 of the first layer and the second layer are appropriately connected through through holes formed in the insulating layer 4. Here, the insulating substrate 2 is made of a transparent ceramic material such as polymer glass, plastic, or sapphire. Further, the conductor patterns 3 and 5 are formed of a transparent good conductor such as ITO or SnO 2 . Furthermore, the insulator layer 4 is also formed from a transparent insulating material such as acrylic, epoxy, silicon, or the like.
そして、第２層導体パターン１５上に、半田バ
ンプを形成した電極端子７を有するフリツプチツ
プ半導体素子６、例えばICチツプが電極端子７
の形成面を配線基板１側に向けて、すなわちフエ
イスダウンボンデイングにより接続固定されてい
る。この場合、半導体素子６は電極端子７が導体
パターン５の所定位置に接続されるように、導体
パターン５に対し正確に位置合せする必要がある
が、電極端子７と導体パターン５との接続個所を
基体２、導体パターン３、絶縁体層４および導体
パターン５を通して例えば肉眼等で確認できるた
め、この位置合せは容易である。 A flip-chip semiconductor element 6, for example, an IC chip, has an electrode terminal 7 formed with a solder bump on the second layer conductor pattern 15.
are connected and fixed with the formed surface facing the wiring board 1 side, that is, by face-down bonding. In this case, the semiconductor element 6 needs to be accurately aligned with the conductor pattern 5 so that the electrode terminal 7 is connected to a predetermined position of the conductor pattern 5. This alignment is easy because it can be confirmed, for example, with the naked eye through the base 2, the conductor pattern 3, the insulator layer 4, and the conductor pattern 5.
また、このように導体パターン３，５を透明材
料で形成した場合でも、導体パターン３，５の厚
さ（例えば2000オングストローム程度）による下
地表面との段差により、導体パターン３，５の輪
郭を例えば肉眼やカメラで光学的に認識すること
ができる。この場合、導体パターン３，５の輪郭
をやや斜めの方向から観察すると、より容易に認
識ができる。このようにして、半導体素子６の電
極端子７と導体パターン５との接続部を容易、確
実に確認できることになる。 Furthermore, even when the conductor patterns 3 and 5 are formed of a transparent material in this way, the contours of the conductor patterns 3 and 5 may be distorted, for example, due to the difference in level from the base surface due to the thickness of the conductor patterns 3 and 5 (for example, about 2000 angstroms). It can be recognized optically with the naked eye or with a camera. In this case, the contours of the conductive patterns 3 and 5 can be more easily recognized when observed from a slightly oblique direction. In this way, the connection between the electrode terminal 7 of the semiconductor element 6 and the conductive pattern 5 can be easily and reliably confirmed.
なお、第２層導体パターン５上の電極端子７の
接続部には、必要に応じて電極端子７の接続を良
好にするためのメタライズが施される。具体的に
は、Cr，Ti，Ｗ等からなる接着層、Pd，Ni等か
らなる拡散防止層、熱圧着のためのCu，Au，Al
等の層、耐ハンダ性の良好なNi，Cu等の層およ
びAu等の酸化防止層を適宜形成する。 Note that the connection portions of the electrode terminals 7 on the second layer conductor pattern 5 are subjected to metallization to improve the connection of the electrode terminals 7 as necessary. Specifically, adhesive layers made of Cr, Ti, W, etc., diffusion prevention layers made of Pd, Ni, etc., Cu, Au, Al for thermocompression bonding.
A layer of Ni, Cu, etc. having good solder resistance, and an anti-oxidation layer of Au etc. are formed as appropriate.
このようにすると、接続部にメタライズした材
料が不透明であるため、導体パターン５上の電極
端子７の接続部をより容易に確認できる。 In this case, since the material metallized on the connection part is opaque, the connection part of the electrode terminal 7 on the conductor pattern 5 can be more easily confirmed.
また、第１図には示していないが、配線基板１
上に必要に応じ保護層がモールドされる。第２層
導体パターン５上の半導体素子６の接続部以上の
表面を予めアクリル、エポキシ等からなる透明絶
縁材料で被覆することも可能である。 Although not shown in FIG. 1, the wiring board 1
A protective layer is molded on top if necessary. It is also possible to cover the surface of the second layer conductor pattern 5 above the connection portion of the semiconductor element 6 with a transparent insulating material made of acrylic, epoxy, etc. in advance.
次に、配線基板１の製造工程の一例を第２図を
参照して説明する。 Next, an example of the manufacturing process of the wiring board 1 will be described with reference to FIG. 2.
まず、第２図ａに示すように透明絶縁性基体
２、例えばガラス基板上に、ポジ型フオトレジス
ト１１を塗布し乾燥させた後、第１層透明導体パ
ターン３と反転関係にある不透明パターン１２を
選択的に形成したガラスマスク１３を用いて露光
を行ない、次いで第２図ｂのように現像する。次
に第２図ｃに示すように、透明導体膜１４、例え
ばITO膜を低温スパツタにより1μ程度着膜し、
その後第２図ｄに示すようにフオトレジスト１１
上の透明導体をリフトオフにより除去して、第１
層の透明導体パターン３を形成する。配線基板が
単層のものの場合は、これで基板製造工程は終了
し、以後は半導体素子のボンデイング工程へと進
むことになる。 First, as shown in FIG. 2a, a positive type photoresist 11 is coated on a transparent insulating substrate 2, for example a glass substrate, and dried. After that, an opaque pattern 12 which is in an inverted relationship with the first layer transparent conductor pattern 3 is coated and dried. Exposure is carried out using a glass mask 13 on which is selectively formed, and then development is carried out as shown in FIG. 2b. Next, as shown in FIG. 2c, a transparent conductor film 14, for example, an ITO film, is deposited by a low-temperature sputtering process to approximately 1 μm.
Thereafter, as shown in FIG. 2d, a photoresist 11 is applied.
The upper transparent conductor is removed by lift-off, and the first
A layer of transparent conductor pattern 3 is formed. If the wiring board is a single-layer one, this completes the board manufacturing process, and the next step is to proceed to the bonding process for semiconductor elements.
次に、第２図ｅに示すように透明絶縁体層１
５、例えば紫外線硬化型樹脂（アクリル、エポキ
シ等）をスクリーン印刷、スピンコート等により
塗布し、スルーホールに対応する不透明パターン
１６を選択的に形成したガラスマスク１７を介し
て紫外線により露光、現像する。これにより第２
図ｆに示すように、所定位置にスルーホール１８
を有する透明絶縁体層４が形成される。 Next, as shown in FIG. 2e, the transparent insulating layer 1
5. For example, an ultraviolet curable resin (acrylic, epoxy, etc.) is applied by screen printing, spin coating, etc., and exposed to ultraviolet light and developed through a glass mask 17 in which an opaque pattern 16 corresponding to the through hole is selectively formed. . This allows the second
As shown in Figure f, the through hole 18 is in place.
A transparent insulating layer 4 is formed.
そして、次に第２図ｇに示すように再びポジ型
フオトレジスト１９を塗布し乾燥させ、第２層の
透明導体パターン５と反転関係にある不透明パタ
ーン２０を選択的に形成したガラスマスク２１を
用いて露光した後、第２図ｂ〜ｄと同様の工程を
経て、第２図ｈに示すように第２層の透明導体パ
ターン５を形成する。こうして第１図中に示した
２層の配線基板１が得られる。 Then, as shown in FIG. 2g, a positive type photoresist 19 is again applied and dried to form a glass mask 21 with an opaque pattern 20 selectively formed in an inverted relationship with the transparent conductor pattern 5 of the second layer. After exposure using the same method, the same steps as shown in FIGS. 2b to 2d are performed to form a second layer of transparent conductor pattern 5 as shown in FIG. 2h. In this way, the two-layer wiring board 1 shown in FIG. 1 is obtained.
なお、第２図ａ〜ｄの工程ではリフトオフを用
いたが、まず透明導体層を形成し、その後フオト
レジストを形成し、露光、現像後、エツチングを
行なつて透明導体パターン３を形成し、フオトレ
ジストを除去してもよい。 Although lift-off was used in the steps shown in FIGS. 2a to 2d, first a transparent conductor layer was formed, then a photoresist was formed, and after exposure and development, etching was performed to form a transparent conductor pattern 3. The photoresist may be removed.
また、上記実施例では配線基板として２層のも
のを示したが、単層、あるいは３層以上の場合で
もこの発明は有効である。 Furthermore, although the above embodiments have shown a two-layer wiring board, the present invention is also effective in the case of a single layer or three or more layers.
この発明に係る半導体装置において、配線基板
上に搭載する半導体素子は何でもよいが、特に発
光または受光素子の場合、基板側に発光または受
光面を向けることができる利点がある。すなわ
ち、従来では発光または受光素子はフリツプチツ
プ等のフエイスダウンボンデイングは不可能とさ
れていたが、この発明によればそれが可能とな
る。 In the semiconductor device according to the present invention, any semiconductor element may be mounted on the wiring board, but especially in the case of a light-emitting or light-receiving element, there is an advantage that the light-emitting or light-receiving surface can face the substrate side. That is, conventionally, face-down bonding of a light emitting or light receiving element such as a flip chip was impossible, but according to the present invention, it is now possible.
第１図はこの発明の一実施例に係る半導体装置
の断面図、第２図ａ〜ｈはこの発明で用いる配線
基板の製造工程を示す図である。
１……配線基板、２……透明絶縁性基体、３，
５……透明導体パターン、４……透明絶縁体層、
６……半導体素子、７……電極端子。
FIG. 1 is a sectional view of a semiconductor device according to an embodiment of the invention, and FIGS. 2a to 2h are diagrams showing manufacturing steps of a wiring board used in the invention. 1 ...Wiring board, 2...Transparent insulating substrate, 3,
5...Transparent conductor pattern, 4...Transparent insulator layer,
6... Semiconductor element, 7... Electrode terminal.
Claims (1)
電極端子をその電極端子形成面を配線基板側に向
けて接続してなる半導体装置において、前記配線
基板は透明絶縁性基体上に透明導体パターンを被
着形成して構成されていることを特徴とする半導
体装置。 ２ 配線基板は透明絶縁性基体上に複数層の透明
導体パターンを層間に透明絶縁体層を介して積層
形成したものであることを特徴とする特許請求の
範囲第１項記載の半導体装置。 ３ 透明導体パターンの半導体素子接続部に、半
導体素子の電極端子を接続するためのメタライズ
が施されていることを特徴とする特許請求の範囲
第１項記載の半導体装置。 ４ 半導体素子が発光または受光素子であること
を特徴とする特許請求の範囲第１項記載の半導体
装置。[Scope of Claims] 1. A semiconductor device in which electrode terminals of a semiconductor element are connected to a conductor pattern on a wiring board with the electrode terminal forming surface thereof facing the wiring board, wherein the wiring board is connected to a conductor pattern on a transparent insulating substrate. 1. A semiconductor device comprising a transparent conductor pattern deposited on a semiconductor device. 2. The semiconductor device according to claim 1, wherein the wiring board is formed by laminating a plurality of layers of transparent conductor patterns on a transparent insulating substrate with a transparent insulating layer interposed between the layers. 3. The semiconductor device according to claim 1, wherein the semiconductor element connecting portion of the transparent conductor pattern is metallized for connecting an electrode terminal of the semiconductor element. 4. The semiconductor device according to claim 1, wherein the semiconductor element is a light emitting or light receiving element.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58119329A JPS6010735A (en) | 1983-06-30 | 1983-06-30 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58119329A JPS6010735A (en) | 1983-06-30 | 1983-06-30 | Semiconductor device |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5254357A Division JP2597809B2 (en) | 1993-10-12 | 1993-10-12 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6010735A JPS6010735A (en) | 1985-01-19 |
| JPH0469428B2 true JPH0469428B2 (en) | 1992-11-06 |
Family
ID=14758775
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58119329A Granted JPS6010735A (en) | 1983-06-30 | 1983-06-30 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6010735A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB0224689D0 (en) | 2002-10-23 | 2002-12-04 | Simage Oy | Formation of contacts on semiconductor substrates |
| JP2005202382A (en) * | 2003-12-18 | 2005-07-28 | Sumitomo Bakelite Co Ltd | Optical printed circuit board, surface mounting type semiconductor package, and mother board |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5269646A (en) * | 1975-12-08 | 1977-06-09 | Seiko Epson Corp | Liquid crystal display device |
| JPS5273693A (en) * | 1975-12-16 | 1977-06-20 | Seiko Epson Corp | Display device |
| JPS5276051A (en) * | 1975-12-22 | 1977-06-25 | Seiko Epson Corp | Liquid crystal indicating device |
| JPS5276877A (en) * | 1975-12-22 | 1977-06-28 | Seiko Epson Corp | Semiconductor device |
| JPS5359398A (en) * | 1976-11-09 | 1978-05-29 | Seiko Epson Corp | Liquid crystal display panel |
| JPS53104198A (en) * | 1977-02-23 | 1978-09-11 | Takagi Kogyo Kk | Liquid crystal panel |
| JPS5552229A (en) * | 1978-10-11 | 1980-04-16 | Nec Corp | Manufacture of semiconductor device |
| JPS5691491A (en) * | 1979-12-25 | 1981-07-24 | Alps Electric Co Ltd | Method of manufacturing transparent laminated circuit board |
-
1983
- 1983-06-30 JP JP58119329A patent/JPS6010735A/en active Granted
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5269646A (en) * | 1975-12-08 | 1977-06-09 | Seiko Epson Corp | Liquid crystal display device |
| JPS5273693A (en) * | 1975-12-16 | 1977-06-20 | Seiko Epson Corp | Display device |
| JPS5276051A (en) * | 1975-12-22 | 1977-06-25 | Seiko Epson Corp | Liquid crystal indicating device |
| JPS5276877A (en) * | 1975-12-22 | 1977-06-28 | Seiko Epson Corp | Semiconductor device |
| JPS5359398A (en) * | 1976-11-09 | 1978-05-29 | Seiko Epson Corp | Liquid crystal display panel |
| JPS53104198A (en) * | 1977-02-23 | 1978-09-11 | Takagi Kogyo Kk | Liquid crystal panel |
| JPS5552229A (en) * | 1978-10-11 | 1980-04-16 | Nec Corp | Manufacture of semiconductor device |
| JPS5691491A (en) * | 1979-12-25 | 1981-07-24 | Alps Electric Co Ltd | Method of manufacturing transparent laminated circuit board |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6010735A (en) | 1985-01-19 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP4476381B2 (en) | Semiconductor chip package and manufacturing method thereof | |
| KR950012658B1 (en) | Semiconductor chip mounting method and substrate structure | |
| KR100676493B1 (en) | Manufacturing Method of Wafer Level Chip Scale Package Using Redistribution Substrate | |
| JP3142723B2 (en) | Semiconductor device and manufacturing method thereof | |
| US20010040285A1 (en) | Semiconductor device and method of manufacturing same | |
| US20030128442A1 (en) | Image pickup device and process for producing the same | |
| JP2002246535A (en) | Semiconductor integrated circuit | |
| KR980006157A (en) | Structure and Manufacturing Method of Semiconductor Package | |
| JP2001156203A (en) | Printed wiring board for mounting semiconductor chip | |
| JP2003007902A (en) | Electronic component mounting substrate and mounting structure | |
| US8053281B2 (en) | Method of forming a wafer level package | |
| US6784528B2 (en) | Semiconductor device with plating wiring connecting IC electrode pad to terminal | |
| JPH0469428B2 (en) | ||
| JP2597809B2 (en) | Method for manufacturing semiconductor device | |
| KR20030069321A (en) | Fabrication and assembly method of image sensor using by flip chip packaging process | |
| JPH04199723A (en) | Semiconductor device and manufacture thereof | |
| JPH0363813B2 (en) | ||
| JPS58164255A (en) | Semiconductor device | |
| JPH09307019A (en) | Manufacture of semiconductor package and semiconductor package | |
| JPH04242939A (en) | Packaging structure of semiconductor device and its manufacture | |
| JP2841822B2 (en) | Manufacturing method of hybrid integrated circuit | |
| KR100417854B1 (en) | chip scale package and method of fabricating the same | |
| JPH06112402A (en) | Semiconductor device | |
| KR20000042665A (en) | Chip size package and fabrication method thereof | |
| KR100325466B1 (en) | Chip size package and method for fabricating the same |