JPH0462969A - Semiconductor integration method - Google Patents

Abstract

PURPOSE:To make a longitudinal wiring system identical to a transverse wiring system and to reduce the number of contacts by a method wherein a plurality of masks are arranged in a matrix shape so as to be alternately directed longitudinally and transversely via prescribed gaps and the masks are connected arbitrarily by using second conductors so as to match wiring routes. CONSTITUTION:Wiring by masks 1 by a first conductor which are prepared in advance by the side of a maker are alternately arranged longitudinally and transversely; and the wiring system of the longitudinal and transverse masks 1 are arranged in the same manner via second conductors 2. Since the longitudinal and transverse wiring systems are the same, a wiring delay is nearly proportional to a distance irrespective of the longitudinal wiring and the transverse wiring and can be treated in the same manner as a wiring delay in a general master slice system. When first wiring and through holes are constituted and second wiring are formed arbitrarily, they can be integrated. Consequently, wiring can be formed of only the second wiring not at individual fragments as long as the wiring does not collide. The number of contacts can be reduced in wiring and the resistance by the contacts during the wiring can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Field of Application) The present invention relates to a method for forming wiring in a semiconductor integrated circuit.

(Prior Art) Fig. 2 shows a wiring forming method using a single mask unique to the user side in the conventional mask slicing method.In the figure, (1) is already formed on a substrate not shown. (2) is a second conductor connected to each second conductor to form a wiring pattern; (3) is a contact that connects the first conductor and the second conductor (2); (4a) is a contact that connects the first conductor and the second conductor (2); ) −
(4b) to (9a) (9b) shows each wiring.

Note that an insulating layer is interposed between the first conductor (1) and the second conductor (2).

Next, a method of forming wiring by connecting each of the conductors described above will be explained. Regarding the wiring (4a)-(4b), as shown in the figure, the horizontal wiring is connected to each adjacent first conductor (1),
(1) a second conductor is formed between the second conductor (2);
Electrical contact between the first conductor and each first conductor (1) is made through a through hole (not shown). The vertical wiring is formed of one second conductor without making electrical contact with the first conductor. (5a) - (5b) ~ (9
The wiring from a) to (9b) is also performed in the same manner as above.

FIG. 3 shows wiring in a general mask slice method.

[Problem to be solved by the invention]

Conventional semiconductor integration methods were configured as described above, so vertical wiring can be wired with wood using the second conductor, but horizontal wiring can be wired using contacts with the first conductor and electricity of the second conductor. Because conduction is achieved through repeated physical contact,
Due to the high contact resistance caused by the contacts, a horizontally long wiring has a higher resistance than a vertically long wiring, causing problems such as variations in delay time.

Furthermore, as a conventional mask slicing method for manufacturing semiconductor integrated circuits using a mask prepared on the substrate by the manufacturer in advance and a mask specific to the user, there is a method known as Japanese Patent Laid-Open No. 14495/1983.
There is a "method for manufacturing a semiconductor device" disclosed in No. 6. This technology constructs the first and second wiring (first and second layer wiring) with a plurality of strip-like small pieces arranged in rows and columns in alternating vertical and horizontal directions. The purpose of this invention is to realize various two-layer interconnections using the master slice method by using the above-mentioned fixed pattern for interconnections and simply changing the positions of through-holes that alternately connect these two interconnections.

Therefore, in this technique, it is necessary to make electrical contact between the small pieces constituting the first and second wiring included in the wiring pattern through through holes, and the overall contact resistance tends to increase.

The present invention has been made to solve the above-mentioned problems, and its object is to provide a semiconductor integration method in which the vertical and horizontal wiring systems can be made the same and the number of contacts can be reduced.

[Means for Solving the Problems] A semiconductor integration method according to the present invention includes arranging a plurality of masks constituting a first conductor in a matrix shape on a substrate in alternating vertical and horizontal directions with predetermined gaps therebetween. , the respective masks are arbitrarily connected by a second conductor in accordance with the wiring route formed on the substrate.

[Function] The semiconductor integration method according to the present invention reduces the number of contacts when wiring by arranging the wiring of the first conductor mask prepared in advance by the manufacturer side alternately in the vertical and horizontal directions and using the same wiring method in the vertical and horizontal directions. The number of contacts is made substantially the same in the vertical and horizontal wiring, and the number of contacts is reduced.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
Figure (a) shows a wiring system for a first conductor mask that implements the semiconductor integration method in this embodiment. As shown in the figure, in this wiring method, the wiring of the mask (1) of the first conductor prepared in advance by the manufacturer is arranged alternately in the vertical and horizontal directions, and the wiring of the mask (1) in the vertical and horizontal directions is arranged through the second conductor (2). Use the same wiring method.

By adopting the wiring method described above, the number of contacts is 35 in total, 5 to 7 in the method of this embodiment, as shown in Figure 1 (b). ,
In the conventional method shown in FIG. 2, there are 3 to 12 pieces, for a total of 43 pieces. Therefore, in the conventional method shown in Fig. 2, the number of contacts differs several times depending on the wiring direction (vertical or horizontal), so the wiring delay greatly differs due to contact resistance, etc. In this method shown in a), since the vertical and horizontal wiring systems are the same, the wiring delay is approximately proportional to the distance regardless of the vertical and horizontal directions, and can be handled in the same way as the wiring delay in the master slice system.

Furthermore, in the prior art JP-A No. 60-144956 ``Method for manufacturing a semiconductor device'', the wiring is achieved by ``configuring the first wiring and the second wiring alternately vertically and horizontally, and forming through holes arbitrarily.'' However, in this embodiment, this is achieved by ``configuring the first wiring and the through hole, and then forming the second wiring arbitrarily.'' Therefore, the wiring in the prior art always goes from the first wiring to the through hole to the second wiring for each small fragment.
However, in this example, since the second wiring is formed arbitrarily, it is not necessary to form each small piece.
The advantage is that the wiring can be formed using only the second wiring as long as the wiring does not collide.

Moreover, this allows the number of contacts during wiring to be reduced, and the resistance due to contacts during wiring can also be reduced. Furthermore, with the miniaturization of processes in recent years, contact holes have also become smaller, and a decrease in yield due to contacts is expected, but reducing the number of contacts has the effect of suppressing the decrease in yield.

(Effects of the Invention) As described above, according to the present invention, in the wiring method in the semiconductor integration method, the first conductor masks prepared by the manufacturer in advance are arranged vertically and horizontally, and the second conductor masks prepared by the user are arranged alternately vertically and horizontally. The wiring method using a conductive mask can be made the same in both the vertical and horizontal directions, so there is little variation in the wiring delay due to differences in the vertical and horizontal wiring, and since the number of contacts can be reduced, the delay itself can also be reduced.

[Brief explanation of drawings]

FIG. 1(a) shows the wiring method according to the present invention, and FIG. 1(b) shows the wiring method according to the present invention.
2 is a diagram showing a comparison table of the number of contact points between the wiring method in this embodiment and the conventional wiring method, FIG. 2 is a wiring method in a method in which the user prepares one mask in the mask slice method, and FIG. is a wiring method in the general mask-slice method. In the figure, (1) is a first conductor, (2) is a second conductor, (3) is a contact, and (4) to (9) are wirings. In the figures, the same symbols indicate the same or equivalent parts.

Claims (1)

[Claims] A plurality of masks constituting the first conductor are arranged in a matrix in alternating vertical and horizontal directions with predetermined gaps between them, and a plurality of masks are arranged between each mask in alignment with the wiring route formed on the substrate. A semiconductor integration method characterized by arbitrarily connecting two conductors.