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JPH0462938A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

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Publication number
JPH0462938A
JPH0462938A JP17303890A JP17303890A JPH0462938A JP H0462938 A JPH0462938 A JP H0462938A JP 17303890 A JP17303890 A JP 17303890A JP 17303890 A JP17303890 A JP 17303890A JP H0462938 A JPH0462938 A JP H0462938A
Authority
JP
Japan
Prior art keywords
window
photoresist film
gate electrode
recess
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP17303890A
Other languages
Japanese (ja)
Other versions
JP3035994B2 (en
Inventor
Tomoaki Hirokawa
廣川 友明
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP2173038A priority Critical patent/JP3035994B2/en
Publication of JPH0462938A publication Critical patent/JPH0462938A/en
Application granted granted Critical
Publication of JP3035994B2 publication Critical patent/JP3035994B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Junction Field-Effect Transistors (AREA)

Abstract

PURPOSE:To highly accurately manufacture a gate electrode of a mushroom structure inclined toward the side of a source by a method wherein a window is opened and installed with high accuracy in order to form a gate electrode by utilizing the window in a photoresist film. CONSTITUTION:An active layer 2 and an oxide film 3 are formed on a GaAs substrate 1; and individual ohmic electrodes of a source electrode 4 and a drain electrode 5 are formed respectively through a window in the oxide film 3. Then, the whole surface is coated with a photoresist film 6; and a window 7 is opened and installed. The window 7 in the photoresist film 6 is constituted of the following: an upper-part window 7a whose width size is large; and a lower-part window 7b which is formed at the bottom of the upper-part window 7a and whose width size is very small. A recess 8 and a gate electrode 9A are formed so as to correspond to the window 7 formed in the resist film 6; and their size and their positional accuracy are controlled by the size and the positional accuracy of the window 7. Since the window 7 can be opened and installed with high accuracy by patterning the flat face of the photoresist film 6, the recess 8 and the gate electrode 9A can be formed with high accuracy.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置の製造方法に関し、特にMESFE
Tを備える高周波増幅用化合物半導体装置の製造方法に
関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, and in particular to a method for manufacturing a semiconductor device.
The present invention relates to a method of manufacturing a compound semiconductor device for high frequency amplification including T.

〔従来の技術〕[Conventional technology]

一般にこの種の半導体装置では、化合物半導体基板に活
性層を形成した上で、この活性層にリセスを形成し、さ
らにこのリセスにゲート電極を配設した構成がとられて
いる。この場合、ソース抵抗を低減するために、ゲート
電極はソース側に偏倚された所謂オフセット構造がとら
れることが多い。
Generally, this type of semiconductor device has a structure in which an active layer is formed on a compound semiconductor substrate, a recess is formed in the active layer, and a gate electrode is further provided in the recess. In this case, in order to reduce the source resistance, the gate electrode often has a so-called offset structure in which it is biased toward the source side.

従来、この種の半導体装置の製造方法では、半導体基板
上に形成したマクスを利用したウェットエツチング法に
より半導体基板にリセスを形成し、続いて同一マスクを
用いてアルミニウム等のゲート金属を斜方蒸着すること
により、リセス内にゲ−ト電極をオフセット形成する方
法がとられている。例えば、電子情報通信学会ED、 
88−16゜また、従来、この種の半導体装置の製造方
法では、ゲート電極をオフセット構造に形成するととも
に、ゲート電極をマツシュルーム構造としてゲート電極
の低抵抗化を図った製造方法も提案されている。例えば
、電子情報通信学会ED89−54゜この方法を、第3
図(a)ないしくe)に示す。
Conventionally, in the manufacturing method of this type of semiconductor device, a recess is formed in the semiconductor substrate by a wet etching method using a mask formed on the semiconductor substrate, and then a gate metal such as aluminum is obliquely evaporated using the same mask. By doing this, a method has been adopted in which the gate electrode is formed offset within the recess. For example, IEICE ED,
88-16゜Furthermore, conventionally, in the manufacturing method of this type of semiconductor device, a manufacturing method has been proposed in which the gate electrode is formed in an offset structure and the gate electrode is formed in a pine mushroom structure to reduce the resistance of the gate electrode. . For example, the Institute of Electronics, Information and Communication Engineers ED89-54
As shown in Figures (a) to e).

先ず、第3図(a)のように、活性層12を形成した半
導体基板11にソース電極14.ドレイン電極15とし
ての各オーミック電極を形成し、かつその中間部にオフ
セットリセスゲート形成用のシリコン酸化膜13を所要
の幅にパターン形成する。
First, as shown in FIG. 3(a), a source electrode 14. is formed on a semiconductor substrate 11 on which an active layer 12 is formed. Each ohmic electrode is formed as a drain electrode 15, and a silicon oxide film 13 for forming an offset recess gate is patterned to a desired width in the intermediate portion thereof.

次いで、第3図(b)のように、全面にシリコン窒化膜
16を被覆し、かつこのシリコン窒化膜16のソース電
極側の一部に窓16aを開設する。
Next, as shown in FIG. 3(b), the entire surface is covered with a silicon nitride film 16, and a window 16a is formed in a part of the silicon nitride film 16 on the source electrode side.

そして、第3図(C)のように、シリコン窒化膜16の
窓16aを通してシリコン酸化膜13をエツチングする
。続いて、第3図(d)のように、シリコン窒化膜16
の窓16aを通して半導体基板11をエツチングし、リ
セス17を形成する。
Then, as shown in FIG. 3C, the silicon oxide film 13 is etched through the window 16a of the silicon nitride film 16. Subsequently, as shown in FIG. 3(d), a silicon nitride film 16 is formed.
The semiconductor substrate 11 is etched through the window 16a to form a recess 17.

その上で、第3図(e)のように、全面にゲート金属を
形成し、かつこのゲート金属をシリコン窒化膜16の窓
16aを含む領域を残して選択エツチングすることで、
断面形状がT型(マツシュルーム形状)をしたゲート電
極18をオフセット構造に形成することができる。
Then, as shown in FIG. 3(e), a gate metal is formed on the entire surface, and this gate metal is selectively etched leaving a region including the window 16a of the silicon nitride film 16.
The gate electrode 18 having a T-shaped (mushroom-shaped) cross-sectional shape can be formed in an offset structure.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来の製造方法において、前者の方法ではゲー
ト電極をマツシュルーム構造に形成することができない
ため、ゲート抵抗を低減することが困難で、高速動作が
要求される半導体装置には採用することができないとい
う問題がある。
Among the conventional manufacturing methods described above, the former method cannot form the gate electrode in a mushroom structure, making it difficult to reduce gate resistance and cannot be used in semiconductor devices that require high-speed operation. There is a problem.

また、後者の方法では、オフセットリセスゲート形成用
のシリコン酸化膜13を再現性良く形成することが困難
であり、リセスを高精度に形成することが困難となる。
Furthermore, in the latter method, it is difficult to form the silicon oxide film 13 for forming the offset recess gate with good reproducibility, and it is difficult to form the recess with high precision.

また、シリコン窒化膜16に形成する窓16aをソース
側の段差の近傍に開設しなければならないため、これに
利用されるフォトリソグラフィ技術での取扱が困難とな
り、窓の寸法および位置を高精度に管理することができ
ず、ゲート電極のオフセット位置を高精度に形成するこ
とが難しいという問題がある。
Furthermore, since the window 16a formed in the silicon nitride film 16 must be opened near the step on the source side, it is difficult to handle the window 16a using the photolithography technology used for this purpose, and the size and position of the window must be determined with high precision. There is a problem in that it is difficult to control the offset position of the gate electrode with high accuracy.

本発明の目的は、リセスを高精度に形成し、かつ低抵抗
でかつ高精度のオフセットゲート電極を高精度に形成す
ることを可能にした半導体装置の製造方法を提供するこ
とにある。
SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor device, which makes it possible to form a recess with high precision and to form a low-resistance, high-precision offset gate electrode with high precision.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の半導体装置の製造方法は、化合物半導体基板上
に酸化膜を形成する工程と、この酸化膜上にフォトレジ
スト膜を形成しかつこのフォトレジスト膜に窓を開設す
る工程と、このフォトレジスト膜の窓を通して前記酸化
膜をエツチングする工程と、この酸化膜の窓を通して半
導体基板をエツチングしてリセスを形成する工程と、前
記フォトレジスト膜の窓に対してドレイン側の斜め方向
から金属を蒸着して前記リセスのソース側の位置にゲー
ト電極を形成する工程とを含んでいる。
The method for manufacturing a semiconductor device of the present invention includes a step of forming an oxide film on a compound semiconductor substrate, a step of forming a photoresist film on the oxide film and opening a window in the photoresist film, and a step of forming a window in the photoresist film. etching the oxide film through the window of the film; etching the semiconductor substrate through the window of the oxide film to form a recess; and depositing metal from an oblique direction on the drain side with respect to the window of the photoresist film. and forming a gate electrode at a source side position of the recess.

この場合、フォトレジスト膜の窓は、幅寸法の大きな上
部窓と、この上部窓の底部に設けた幅寸法の小さな下部
窓とで構成し、この下部窓を含む上部窓の底部上にまで
ゲート用金属を蒸着してマツシュルーム構造のゲート電
極を形成する。
In this case, the photoresist film window consists of an upper window with a large width and a lower window with a small width provided at the bottom of the upper window, and the gate extends over the bottom of the upper window including the lower window. A gate electrode having a pine mushroom structure is formed by vapor-depositing a metal.

また、上部窓は断面形状をテーパ状とし、下部窓は断面
形状を逆テーパ状とすることが好ましい。
Further, it is preferable that the upper window has a tapered cross-sectional shape, and the lower window has a reverse tapered cross-sectional shape.

〔作用〕[Effect]

本発明方法によれば、フォトレジスト膜における窓を利
用してゲート電極を形成するため、窓を高精度に開設す
ることで、ソース側に偏倚したマツシュルーム構造のゲ
ート電極を高精度に製造することが可能となる。
According to the method of the present invention, since the gate electrode is formed using the window in the photoresist film, by opening the window with high precision, it is possible to manufacture with high precision the gate electrode with the mushroom structure biased toward the source side. becomes possible.

〔実施例〕〔Example〕

次に、本発明を図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第1図(a)ないしくd)は本発明の第1実施例を製造
工程順に示す断面図であり、ここでは本発明をGaAs
MESFETに適用した例を示している。
FIGS. 1(a) to d) are cross-sectional views showing the first embodiment of the present invention in the order of manufacturing steps.
An example of application to MESFET is shown.

先ず、第1図(a)のように、GaAs基板1に活性層
2を形成した上で、表面に酸化膜3を形成し、かつこの
酸化膜3の所要領域に設けた窓(図示せず)を通してそ
れぞれソース電極4.ドレイン電極5の各オーミック電
極を形成する。しかる上で、全面にフォトレジスト膜6
を塗布し、このフォトレジスト膜6に窓7を開設する。
First, as shown in FIG. 1(a), an active layer 2 is formed on a GaAs substrate 1, an oxide film 3 is formed on the surface, and windows (not shown) are formed in required areas of this oxide film 3. ) respectively through the source electrodes 4. Each ohmic electrode of the drain electrode 5 is formed. After that, a photoresist film 6 is applied to the entire surface.
A window 7 is opened in this photoresist film 6.

このとき、フォトレジスト膜6の窓7は幅寸法が大きな
上部窓7aと、この上部窓7aの底面に形成した幅寸法
が微小な下部窓7bとで構成されるように形成する。こ
の場合、図示の例では上部窓7aは断面形状をテーパ状
とし、下部窓7bは断面形状を逆テーパ状に形成してい
るが、これらは垂直壁の窓として形成してもよい。
At this time, the window 7 of the photoresist film 6 is formed to include an upper window 7a having a large width and a lower window 7b having a small width formed on the bottom surface of the upper window 7a. In this case, in the illustrated example, the upper window 7a has a tapered cross section, and the lower window 7b has a reverse tapered cross section, but these may be formed as windows in a vertical wall.

次いで、第1図(b)のように、前記フォトレジスト膜
6の窓7を通して酸化膜3をウェットエツチングして窓
3aを開設し、さらにこの窓3aを介してGaAs基板
1をウェットエツチングしてGaAs基板1の活性層2
にリセス8を形成する。
Next, as shown in FIG. 1(b), the oxide film 3 is wet-etched through the window 7 of the photoresist film 6 to form a window 3a, and the GaAs substrate 1 is further wet-etched through this window 3a. Active layer 2 of GaAs substrate 1
A recess 8 is formed in.

しかる上で、第1図(C)のように、前記フォトレジス
ト膜6の窓7を通して全面にアルミニウム9を蒸着する
。このとき、アルミニウム9がソース側に向かって斜め
方向から蒸着されるように斜方蒸着を行う。これにより
、フォトレジスト膜6の上部窓7内ではソース側に偏倚
した箇所にアルミニウムが蒸着され、かつ下部窓7bを
通してリセス8のソース側に偏倚した位置にアルミニウ
ムのゲート電極9Aが形成される。
Then, as shown in FIG. 1C, aluminum 9 is vapor-deposited over the entire surface through the window 7 of the photoresist film 6. At this time, oblique deposition is performed so that aluminum 9 is deposited obliquely toward the source side. As a result, aluminum is vapor-deposited in the upper window 7 of the photoresist film 6 at a location biased toward the source side, and an aluminum gate electrode 9A is formed at a location biased toward the source side of the recess 8 through the lower window 7b.

その後、第1図(d)のように、フォトレジスト膜6を
除去することで、マツシュルーム形状をし、かつリセス
8内のソース側に偏倚した位置にゲート電極9Aが形成
されたMESFETが形成される。
Thereafter, as shown in FIG. 1(d), by removing the photoresist film 6, a MESFET having a mushroom shape and having a gate electrode 9A formed at a position biased toward the source side within the recess 8 is formed. Ru.

したがって、この製造方法では、フォトレジスト膜6に
形成した窓7に応じてリセス8およびゲート電極9Aが
形成され、かつその寸法や位置の精度は窓7の寸法や位
置の精度によって管理されることになる。そして、この
窓7はフォトレジスト膜6の平坦面におけるパターニン
グによって高精度に開設することができるため、リセス
8およびゲート電極9Aを高精度に形成することが可能
となる。
Therefore, in this manufacturing method, the recess 8 and the gate electrode 9A are formed in accordance with the window 7 formed in the photoresist film 6, and the accuracy of their dimensions and position is controlled by the accuracy of the dimension and position of the window 7. become. Since this window 7 can be formed with high precision by patterning the flat surface of the photoresist film 6, it becomes possible to form the recess 8 and the gate electrode 9A with high precision.

ゲート電極9Aがマツシュルーム形状であることにより
ゲート抵抗が低減されることは言うまでもない。
It goes without saying that the gate resistance is reduced because the gate electrode 9A has a mushroom shape.

第2図(a)ないしくd)は本発明の第2実施例を製造
工程順に示す断面図である。ここでは本発明をHJFE
Tに適用した例を示しており、第1実施例と同一または
等価な部分には同一符号を付しである。
FIGS. 2(a) to 2d) are cross-sectional views showing a second embodiment of the present invention in the order of manufacturing steps. Here, the present invention will be described as HJFE.
This figure shows an example applied to T, and the same or equivalent parts as in the first embodiment are given the same reference numerals.

この製造方法では、第2図(a)のように、GaAs基
板1に活性層としてn−A/2GaAs層2Aとn” 
GaAs層2Bを形成し、その上で第2図(b)ないし
くd)に示す工程でリセス8とゲート電極9Aを形成し
ている。この工程は第1実施例と全く同じである。
In this manufacturing method, as shown in FIG. 2(a), an n-A/2 GaAs layer 2A and an n''
A GaAs layer 2B is formed, and a recess 8 and a gate electrode 9A are formed thereon in the steps shown in FIGS. 2(b) to 2d). This process is exactly the same as the first embodiment.

この製造方法により、良好なマツシュルームゲートが形
成でき、ゲート抵抗が低減されたH J FETが形成
できる。
By this manufacturing method, a good mushroom gate can be formed, and an H J FET with reduced gate resistance can be formed.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、フォトレジスト膜に、幅
寸法の大きな上部窓と、この上部窓の底部に設けた幅寸
法の小さな下部窓を開設し、これら窓に対してドレイン
側の斜め方向からゲート金属を蒸着してゲート電極を形
成しているので、平坦なフォトレジスト膜に対して窓を
高精度に開設することが容易なことから、ソース側に偏
倚したゲート抵抗の低いゲート電極を高精度に製造する
ことができる。
As explained above, the present invention provides a photoresist film with an upper window with a large width and a lower window with a small width provided at the bottom of the upper window, and a diagonal direction on the drain side with respect to these windows. Since the gate electrode is formed by vapor-depositing the gate metal from the source, it is easy to form a window with high precision in the flat photoresist film. Can be manufactured with high precision.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(a)ないしくd)は本発明の第1実施例を製造
工程順に示す断面図、第2図(a)ないしくd)は本発
明の第2実施例を製造工程順に示す断面図、第3図(a
)ないしくe)は従来の製造方法の一例を工程順に示す
断面図である。 1・・・GaAs基板、2・・・活性層、2A・・・n
−AlGaAs層、2B−n”GaAs層、3・・・酸
化膜、4・・・ソース電極、5・・・ドレイン電極、6
・・・フォトレジスト膜、7・・・窓、8・・・リセス
、9・・・アルミニウム、9A・・・ゲート電極、11
・・・半導体基板、12・・・活性層、13・・・シリ
コン酸化膜、14・・・ソ−スミ極、 15・・・ドレイン電極、 16・・・シリコン 窒化膜、 17・・・リセス、 18・・・ゲート電極。 第2 図 (C) メメN ノア111 区ワ:vm 第 図
FIGS. 1(a) to d) are cross-sectional views showing the first embodiment of the present invention in the order of manufacturing steps, and FIGS. 2(a) to d) are cross-sectional views showing the second embodiment of the present invention in the order of the manufacturing steps. Figure, Figure 3 (a
) to e) are cross-sectional views showing an example of a conventional manufacturing method in the order of steps. 1...GaAs substrate, 2...active layer, 2A...n
-AlGaAs layer, 2B-n"GaAs layer, 3... Oxide film, 4... Source electrode, 5... Drain electrode, 6
... Photoresist film, 7... Window, 8... Recess, 9... Aluminum, 9A... Gate electrode, 11
... Semiconductor substrate, 12... Active layer, 13... Silicon oxide film, 14... Source-side electrode, 15... Drain electrode, 16... Silicon nitride film, 17... Recess , 18...gate electrode. Figure 2 (C) Meme N Noah 111 Ward Wa: vm Figure

Claims (1)

【特許請求の範囲】 1、化合物半導体基板上に酸化膜を形成する工程と、こ
の酸化膜上にフォトレジスト膜を形成し、かつこのフォ
トレジスト膜に窓を開設する工程と、このフォトレジス
ト膜の窓を通して前記酸化膜をエッチングする工程と、
この酸化膜の窓を通して半導体基板をエッチングしてリ
セスを形成する工程と、前記フォトレジスト膜の窓に対
してドレイン側の斜め方向から金属を蒸着して前記リセ
スのソース側の位置にゲート電極を形成する工程とを含
み、前記フォトレジスト膜の窓は、幅寸法の大きな上部
窓と、この上部窓の底部に設けた幅寸法の小さな下部窓
とで構成し、この下部窓を含む上部窓の底部上にまでゲ
ート用金属を蒸着してマッシュルーム構造のゲート電極
を形成することを特徴とする半導体装置の製造方法。 2、上部窓は断面形状をテーパ状に形成し、下部窓は断
面形状を逆テーパ状に形成してなる特許請求の範囲第1
項記載の半導体装置の製造方法。
[Claims] 1. A step of forming an oxide film on a compound semiconductor substrate, a step of forming a photoresist film on the oxide film, and a step of opening a window in the photoresist film, and a step of forming a window in the photoresist film. etching the oxide film through the window;
A step is to form a recess by etching the semiconductor substrate through the window of the oxide film, and a gate electrode is formed at a position on the source side of the recess by depositing metal from an oblique direction on the drain side with respect to the window of the photoresist film. The window of the photoresist film is composed of an upper window with a large width and a lower window with a small width provided at the bottom of the upper window, and the window of the photoresist film includes a 1. A method of manufacturing a semiconductor device, comprising depositing a gate metal up to the bottom to form a mushroom-structured gate electrode. 2. The upper window has a tapered cross section, and the lower window has a reverse tapered cross section.
A method for manufacturing a semiconductor device according to section 1.
JP2173038A 1990-06-30 1990-06-30 Method for manufacturing semiconductor device Expired - Lifetime JP3035994B2 (en)

Priority Applications (1)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102007028920A1 (en) * 2006-10-12 2008-04-24 Mitsubishi Electric Corp. Field effect transistor and method for producing the same
EP3613082A4 (en) * 2017-04-10 2021-05-12 The Government of the United States of America as represented by the Secretary of the Navy Diamond air bridge for thermal management of high power devices

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102007028920A1 (en) * 2006-10-12 2008-04-24 Mitsubishi Electric Corp. Field effect transistor and method for producing the same
DE102007028920B4 (en) * 2006-10-12 2009-09-10 Mitsubishi Electric Corp. Field effect transistor with a cavity formed in a silicon nitride layer and method for producing the same
US7642567B2 (en) 2006-10-12 2010-01-05 Mitsubishi Electric Corporation Field-effect transistor and method of manufacturing the same
CN101853879B (en) 2006-10-12 2013-03-13 三菱电机株式会社 Field-effect transistor
EP3613082A4 (en) * 2017-04-10 2021-05-12 The Government of the United States of America as represented by the Secretary of the Navy Diamond air bridge for thermal management of high power devices

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