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JPH0461259A - Cooling method and structure for semiconductor integrated circuit devices - Google Patents

Cooling method and structure for semiconductor integrated circuit devices

Info

Publication number
JPH0461259A
JPH0461259A JP2170031A JP17003190A JPH0461259A JP H0461259 A JPH0461259 A JP H0461259A JP 2170031 A JP2170031 A JP 2170031A JP 17003190 A JP17003190 A JP 17003190A JP H0461259 A JPH0461259 A JP H0461259A
Authority
JP
Japan
Prior art keywords
chip
cap
refrigerant
package
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2170031A
Other languages
Japanese (ja)
Inventor
Norishige Kikuchi
菊地 哲慈
Kanji Otsuka
寛治 大塚
Takashi Mori
隆志 森
Hiroshi Tate
宏 舘
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Renesas Semiconductor Package and Test Solutions Co Ltd
Hitachi Solutions Technology Ltd
Original Assignee
Hitachi ULSI Engineering Corp
Hitachi Hokkai Semiconductor Ltd
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi ULSI Engineering Corp, Hitachi Hokkai Semiconductor Ltd, Hitachi Ltd filed Critical Hitachi ULSI Engineering Corp
Priority to JP2170031A priority Critical patent/JPH0461259A/en
Publication of JPH0461259A publication Critical patent/JPH0461259A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73253Bump and layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1517Multilayer substrate
    • H01L2924/15172Fan-out arrangement of the internal vias
    • H01L2924/15174Fan-out arrangement of the internal vias in different layers of the multilayer substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161Cap
    • H01L2924/1615Shape
    • H01L2924/16152Cap comprising a cavity for hosting the device, e.g. U-shaped cap

Landscapes

  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

PURPOSE:To improve the cooling efficiency of a semiconductor integrated circuit device by blasting finely divided liquid or solid refrigerant over the surface of a semiconductor chip or a package where the semiconductor chip is hermetically sealed. CONSTITUTION:When an integrated circuit formed on a chip 5 starts its operation, the heat generated from the chip 5 is transmitted to a cap 6 or a package base 2 so that a whole chip carrier may be heated. Then, refrigerant fine particles are blasted to virtually the whole area of the rear side of the cap 6 of each chip carrier 1 from the tip of a nozzle 17 connected with a jacket 13 for refrigerant supply service. The refrigerant fine particles which have arrived at the rear side of the cap 6 are heated and boiled so that the heat may be robbed of the rear side of the cap 6 by heat of vaporization, thereby cooling the chip carriers.

Description

【発明の詳細な説明】 =産業上の利用分野: 本発明は、半導体集積回路装置の冷却技術に関するもの
である。
DETAILED DESCRIPTION OF THE INVENTION =Field of Industrial Application: The present invention relates to cooling technology for semiconductor integrated circuit devices.

二従来の技術〕 近年の工、Slは、高集積化、高速化に伴って半導体チ
ップあたりの消費電力が著しく増大り、てこハるだと、
チップを基板に実装するにあたっては、動作時にチップ
から発生ずる熱を如何に効$Jく外部に放出するかがチ
ップの動作信頼性を確保する上で重要な対策となる。特
にチップを基板に面実装(フェイスダウンボンディング
)したような場合は、チップと基板とが小径のバンブ電
極(半田バンブ)を介して接続されるので、チップの熱
が効率よく外部に伝達されず、チップが過熱状態となり
、その結果回路が誤動作したり、チップの寿命が短くな
ったりする虞れがある。
2. Conventional technology] In recent years, the power consumption per semiconductor chip has increased significantly due to higher integration and higher speed, and
When mounting a chip on a substrate, how efficiently the heat generated from the chip during operation can be released to the outside is an important measure to ensure the operational reliability of the chip. In particular, when a chip is surface-mounted on a board (face-down bonding), the chip and the board are connected via small-diameter bump electrodes (solder bumps), so the heat from the chip is not efficiently transferred to the outside. , the chip may become overheated, which may result in malfunction of the circuit or shorten the life of the chip.

ところで、日経BP社(1987,7,13>発行の「
日経エレクトロニクスJP167〜P176には、チッ
プ(またはチップを封止したパッケージ)を不活性液体
の冷媒に直接浸漬する冷却方式が記載されている。上記
浸漬冷却力式は、冷媒とチップ(またはパッケージ)と
を直接接触さゼ、チップ(またはパッケージ)の表面で
冷媒が6騰する際の熱伝達を利用した冷却方式であるた
釣、他の冷却方式(例えば伝導冷却方式など)に比べて
冷媒とチップとの間の熱抵抗をはるかに小さくできると
いう特長を備えている。
By the way, Nikkei BP (1987, July 13)
Nikkei Electronics JP167 to P176 describe a cooling method in which a chip (or a package in which the chip is sealed) is directly immersed in an inert liquid refrigerant. The above-mentioned immersion cooling method is a cooling method that uses heat transfer when the refrigerant rises on the surface of the chip (or package) by bringing the refrigerant into direct contact with the chip (or package). Compared to cooling methods (such as conduction cooling methods), it has the advantage of making the thermal resistance between the coolant and the chip much smaller.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

ところが、上記浸漬冷却方式においては、チップの発熱
量が比較的小さいときは、チップ(またはパッケージ)
の表面のキズや凹凸などを核とする沸騰(核沸騰)によ
って冷却が効率良く進杓するのに対し、チップの発熱量
が増大すると、チップ(またはパッケージ)の表面で発
生ずる気泡同士が次第に融合し、ついには表面全体が気
泡で覆われる、いわゆる膜沸騰状態が生じるため、表面
が蒸気の膜で断熱され、冷却効率が激減してしまうとい
う問題があった。その対策として前訂文献におし′1て
は、冷媒を沸点以下の温度で$騰させる(サブクール4
!11)ことによって、膜沸騰の発生を防止しているが
、この場合は冷媒4玲却づ゛るための熱交換器が必要と
なるなど、装置が複維化してしまうという欠点があった
However, in the immersion cooling method described above, when the amount of heat generated by the chip is relatively small, the chip (or package)
Cooling progresses efficiently by boiling (nucleate boiling) that is centered on scratches or irregularities on the surface of the chip, but as the amount of heat generated by the chip increases, the bubbles generated on the surface of the chip (or package) gradually As a result, a so-called film boiling state occurs in which the entire surface is covered with bubbles, which causes the surface to be insulated by a film of steam, resulting in a drastic reduction in cooling efficiency. As a countermeasure to this problem, the previous document '1 proposes to increase the temperature of the refrigerant below its boiling point (subcool 4
! 11) This prevents the occurrence of film boiling, but in this case, a heat exchanger is required to cool the refrigerant 4, which has the disadvantage of making the device complex.

本発明は、上記した問題点に着目してなされたものであ
り、その目的は半導体集積回路装置の冷却効率を向上さ
せることのできる冷却技術を提供することにある。
The present invention has been made in view of the above problems, and its purpose is to provide a cooling technique that can improve the cooling efficiency of semiconductor integrated circuit devices.

本発明の前記ならびにその他の目的と新規な特徴は、本
明細書の証述および添付図面から明らかになるであろう
The above and other objects and novel features of the present invention will become apparent from the written description and accompanying drawings.

3課題を解決するための手段〕 本願において開示される発明のうち、代表的なものの概
要を簡単に説明すれば、次のとおりである。
Means for Solving the 3 Problems] Among the inventions disclosed in this application, a brief overview of typical inventions is as follows.

本願の一発明は、半導体チップ、または半導体チップを
気密封止したパッケージの表面に液体状または固体状の
冷媒を微粒化して吹き付け、その気化熱を利用して冷却
を行う方法である。
One invention of the present application is a method in which a liquid or solid refrigerant is atomized and sprayed onto the surface of a semiconductor chip or a package in which the semiconductor chip is hermetically sealed, and cooling is performed using the heat of vaporization.

ご作用〕 上記した手段によれば、チップ(またはパッケージ)の
表面に冷媒を微粒化して吹き付けることにより、冷媒を
核沸1に近い状暫で111させることができるので、膜
4@による冷却効率の低下を回避することができる。
Effect] According to the above-mentioned means, by atomizing the refrigerant and spraying it on the surface of the chip (or package), the refrigerant can be brought to 111 in a state close to nucleate boiling point 1, so the cooling efficiency due to the film 4 is improved. can be avoided.

以下、実施例を用し)で本発駅を詳述する。The main departure station will be described in detail below using examples.

〔実施例)。〔Example).

本実施例の単導体集積回路装置は、第2図に示すような
チップキャリヤ(Chip Carrier) lであ
る。
The single conductor integrated circuit device of this embodiment is a chip carrier as shown in FIG.

チップキャリヤ1は、ムライトなどのセラミック材料か
らなるパッケージ基板2の主面の電極3上に半田バンブ
4を介して半導体チップ5をフェイスダウンボンディン
グし、このチップ5をキャップ6で気密封止したパッケ
ージ構造を備えている。
The chip carrier 1 is a package in which a semiconductor chip 5 is face-down bonded via a solder bump 4 onto an electrode 3 on the main surface of a package substrate 2 made of a ceramic material such as mullite, and the chip 5 is hermetically sealed with a cap 6. It has a structure.

キャップ6は、例えば窒化アルミニウム(、IN)など
の高熱伝導性セラミックからなり、封止用半田7によっ
てパッケージ基板2の主面に接合されている。パッケー
ジ基板2の主面の外周部およびキャップ6の脚部の下面
には、上記封止用半田7の濡れ性を向上させるためのメ
タライズ層8が設(ゴられている。上記メタライズ層8
は、]゛11N1およびAuを順次積層した複合金rR
膜からなる。上記キャップG内に封止されたチップ5の
背面(上面)は、伝熱用半田9によってキャップ6の下
面と接合されている。これは、チップ5から発生ずる熱
を伝熱用半田9を通じてキャップ6に伝達するたtであ
る。上記伝熱用半田9の濡れ性を向上させるため、キャ
ップ6の下面には、メタライズ層8が設けられている。
The cap 6 is made of a highly thermally conductive ceramic such as aluminum nitride (IN), and is bonded to the main surface of the package substrate 2 with a sealing solder 7. A metallized layer 8 is provided on the outer periphery of the main surface of the package substrate 2 and on the lower surface of the legs of the cap 6 to improve the wettability of the sealing solder 7.
]゛Composite gold rR in which 11N1 and Au are sequentially laminated
Consists of a membrane. The back surface (upper surface) of the chip 5 sealed within the cap G is joined to the lower surface of the cap 6 by heat transfer solder 9. This is to transfer the heat generated from the chip 5 to the cap 6 through the heat transfer solder 9. In order to improve the wettability of the heat transfer solder 9, a metallized layer 8 is provided on the lower surface of the cap 6.

パッケージ基板2の内層には、例えばW(タングステン
)からなる内部配線10が形成され、この内部配線10
を通じてパッケージ基板2の主面側の電極3と下面側の
電極3とが電気的に接続されている。下面側の電極3に
は、チップキャリヤ1を後述するモジュール基板に実装
する際の外部端子となる半田バンブ11が接合されてい
る。
An internal wiring 10 made of, for example, W (tungsten) is formed in the inner layer of the package substrate 2.
The electrode 3 on the main surface side of the package substrate 2 and the electrode 3 on the lower surface side are electrically connected through the package substrate 2 . Solder bumps 11, which serve as external terminals when the chip carrier 1 is mounted on a module substrate to be described later, are bonded to the electrode 3 on the lower surface side.

上記チップキャリヤ1を組立てるには、甘ずチップ5の
主面に形成した半田バンブ4をパッケージ基板2の主面
の電極3上に位置決めした後、このパッケージ基板2を
不活性ガス雰囲気のりフロ−炉に移送し、その中で半田
バンブ4を加熱、再溶融することによってチップ5をパ
ッケージ基板2の主面にフェイスダウンボンディングす
る。次に、封止用半田7を用いて上記パッケージ基板2
の主面にキャップ6を接合するとともに、伝熱用半田9
を用いてチップ5の背面をキャップ6の下面に接合する
。パッケージ基板2の主面にキャップ6を半田付けする
には、あらかしtパッケージ基板?、の主面およびキャ
ップ6の脚部に封止用半田7を被着した後、パッケージ
基板2の主面にキャップ6を被せ、次いでリフロー炉に
て封止用半田7を加熱、溶融する。その際、封止用半田
7の濡れ広がり性を向上させるたt、キャップ6上に適
度の重さの錘りを載せて荷重を印加する。
To assemble the chip carrier 1, the solder bumps 4 formed on the main surface of the sweet potato chip 5 are positioned on the electrodes 3 on the main surface of the package substrate 2, and then the package substrate 2 is placed in an inert gas atmosphere glue flow. The chips 5 are transferred face-down to the main surface of the package substrate 2 by being transferred to a furnace and heating and remelting the solder bumps 4 therein. Next, the package substrate 2 is sealed using the sealing solder 7.
At the same time, the cap 6 is bonded to the main surface of the heat transfer solder 9.
The back surface of the chip 5 is bonded to the bottom surface of the cap 6 using a . To solder the cap 6 to the main surface of the package board 2, please refer to the package board. After applying the sealing solder 7 to the main surfaces of the package substrate 2 and the legs of the cap 6, the cap 6 is placed on the main surface of the package substrate 2, and then the sealing solder 7 is heated and melted in a reflow oven. At this time, in order to improve the wettability and spreadability of the sealing solder 7, a weight of appropriate weight is placed on the cap 6 to apply a load.

上記封止用半田7および伝熱用半田9は、半田バンブ4
を構成する半田よりも低い溶融温度の半田で構成する。
The sealing solder 7 and the heat transfer solder 9 are connected to the solder bump 4.
It is made of solder that has a lower melting temperature than the solder that makes up the solder.

さもないと、リフロー炉内で封止用半田7および伝熱用
半田9を加熱、溶融する際に半田バンブ4が再溶融し、
キャップ6にかかる荷重によって半田バンブ4が潰れて
しまうた?l>、隣り合った半田バンブ4同七が短絡し
でしまうからである。このような理由から、Il記¥、
■バンブ4は、例えば3〜4重量%稈度のSnを含有す
るP b / S n合金(溶融温度7320〜330
℃程度)などの高融点半田で構成し、封止用¥、田7お
よび伝熱用半田9は、例えば10重量%程度のSnを含
有するPb/Sn合金(溶融温度 21)0〜310℃
程度)などの低融点半田で構成する。
Otherwise, when the sealing solder 7 and the heat transfer solder 9 are heated and melted in a reflow oven, the solder bumps 4 will be remelted.
Could the solder bump 4 be crushed by the load applied to the cap 6? l>, adjacent solder bumps 4 and 7 will be short-circuited. For this reason, Il.
■ The bump 4 is made of, for example, a Pb/Sn alloy containing Sn with a culmability of 3 to 4% (melting temperature 7320 to 330%).
The sealing solder, solder 7 and heat transfer solder 9 are made of a Pb/Sn alloy (melting temperature 21) containing about 10% by weight of Sn (melting temperature 21) from 0 to 310°C.
Consists of low melting point solder such as

本実施例は、以上のような構成からなるチップキャリヤ
1の所定数を半田バンブ11を介して第1図に示すモジ
ュール基板12の主面に実装し、たものである。
In this embodiment, a predetermined number of chip carriers 1 having the above structure are mounted on the main surface of a module substrate 12 shown in FIG. 1 via solder bumps 11.

モジコール基板12は、例えばセラミックで構成され、
その内部には図示しない多層配線が形成されている。チ
ップキャリヤ1をモジニール基板12の主面に実装する
には、パッケージ基板2の下面側の電極3に接続した半
田バンブ11をモジュール基板12の主面の電極(図示
せず)上に正確に位置決めし、このモジュール基板12
を不活法ガス雰囲気のりフロー炉に移送してその中で半
田バンブ11を加熱、再溶融する。その際、チップキャ
リヤ1の封止用半田7や伝熱用半田9が再溶融するのを
防止するたt1半田バンブ11は、封止用半田7や伝熱
用半田9よりもさらに低融点の半田、例えば30重量%
程度のSnを含有するPb/Sn合金(溶I!l!温度
−250〜269℃程度)などにより構成する。
The modicoll board 12 is made of ceramic, for example,
A multilayer wiring (not shown) is formed inside it. To mount the chip carrier 1 on the main surface of the module board 12, the solder bump 11 connected to the electrode 3 on the lower surface of the package board 2 is accurately positioned over the electrode (not shown) on the main surface of the module board 12. This module board 12
The solder bumps 11 are transferred to a flow furnace in an inert gas atmosphere, and the solder bumps 11 are heated and remelted therein. At this time, in order to prevent the sealing solder 7 and the heat transfer solder 9 of the chip carrier 1 from remelting, the t1 solder bump 11 has a lower melting point than the sealing solder 7 and the heat transfer solder 9. Solder, e.g. 30% by weight
It is made of a Pb/Sn alloy containing a certain amount of Sn (molten I!l! temperature of about -250 to 269°C).

チップキャリヤ1を実装した上記モジュール基板12の
上方には、冷媒供給用ジャケット13および冷媒排出用
ジャケット14がそれぞれ配置されている。冷媒供給用
ジャケット13内には、その一端に設けられた供給口1
5を通じて液体状の冷媒(例えばパーフルオロカーボン
)が圧入されるようになっている。他方、冷媒排出用ジ
ャケット14の一端には、冷媒の蒸気を外部に排出する
排出口16が設けられている。排出口16の途中には、
冷媒排出用ジャケット14内の冷媒の蒸気を強制排気す
るポンプ(図示せず)が接続されている。排出口16の
他端側は、冷媒供給源(図示せず)に接続され、ここで
冷却、液化された冷媒は、再び供給口15を通じて冷媒
供給用ジャケット13内に圧入される。
Above the module substrate 12 on which the chip carrier 1 is mounted, a coolant supply jacket 13 and a coolant discharge jacket 14 are arranged, respectively. Inside the refrigerant supply jacket 13, there is a supply port 1 provided at one end thereof.
A liquid refrigerant (for example, perfluorocarbon) is press-fitted through the hole 5. On the other hand, a discharge port 16 is provided at one end of the refrigerant discharge jacket 14 for discharging refrigerant vapor to the outside. In the middle of the discharge port 16,
A pump (not shown) for forcibly exhausting refrigerant vapor within the refrigerant discharge jacket 14 is connected. The other end of the discharge port 16 is connected to a refrigerant supply source (not shown), and the cooled and liquefied refrigerant is again press-fitted into the refrigerant supply jacket 13 through the supply port 15 .

上記モジュール基板12の主面に実装されたそれぞれの
チップキャリヤ1の上方には、上端が冷媒供給用ジャケ
ット13内に開孔されたノズル17が配置されている。
Above each chip carrier 1 mounted on the main surface of the module substrate 12, a nozzle 17 whose upper end is opened into the coolant supply jacket 13 is arranged.

上記ノズル17の先端(下端)は、それぞれのチップキ
ャリヤ1のキャップ6の背面近傍に配置されており、キ
ャップ6の背面のほぼ全域に冷媒の微粒子を吹き付ける
ようになっている。また、それぞれのチップキャリヤ1
のキャップ6上には、上端が冷媒排出用ジャケット14
内に開孔された筒状の冷却ブロック18が搭載されてい
る。冷却ブロック18の下端は、ろう材19を介してキ
ャップ6の外周部に接続されている。上記冷却ブロック
18の側壁の一部にはベローズ20が形成されている。
The tip (lower end) of the nozzle 17 is arranged near the back surface of the cap 6 of each chip carrier 1, so that fine particles of the refrigerant are sprayed over almost the entire back surface of the cap 6. Also, each chip carrier 1
A refrigerant discharge jacket 14 is located on the cap 6 at the upper end.
A cylindrical cooling block 18 with holes formed inside is mounted. The lower end of the cooling block 18 is connected to the outer circumference of the cap 6 via a brazing material 19. A bellows 20 is formed on a part of the side wall of the cooling block 18.

上記ベローズ20は、チップ5の発熱によってキャップ
6、冷却ブロック18、パッケージ基板2、モジ、−ル
基板12などが熱膨張した際、それら各部材の熱膨張係
数差によって半田バンブ11に強いストレスが加わるの
を防止するた於に形成されl:、(、)Z)。
In the bellows 20, when the cap 6, cooling block 18, package board 2, module board 12, etc. thermally expand due to the heat generated by the chip 5, strong stress is applied to the solder bump 11 due to the difference in the coefficient of thermal expansion of each of these members. 1:, (,)Z).

次に、ト、記した本実施例の冷却構造の信用、効果を説
明する。
Next, the reliability and effects of the cooling structure of this embodiment described above will be explained.

チップ5に形成された集積回路がIl!I會を開始′4
ると、チップ5から発生した熱がキャンプ6やパッケー
ジ基板2に伝達され、チップキャリヤ1全体が加熱され
る。すると、冷媒供給用ジ丁ケット・13に接続された
ノズル17の先端からそれぞれのチップキャリヤ1のキ
ャップ6の背面のほぼ全域に冷媒の微粒子が吹き付lj
られる。キャップ6の背面に到達し5た冷媒の微粒子は
、加熱されてr騰し、七の気化熱1.:よ−っでキャッ
プ6の背面から熱が奪われるた〆)、チップキャリヤ1
が冷却さ才する。キャップ6の背面で気化した冷媒は、
冷却ブロック18、冷媒排出用ジャケット14および排
出口16を通じて外部に排出される。
The integrated circuit formed on chip 5 is Il! Start an I-meeting'4
Then, the heat generated from the chip 5 is transferred to the camp 6 and the package substrate 2, and the entire chip carrier 1 is heated. Then, fine particles of refrigerant are sprayed from the tip of the nozzle 17 connected to the refrigerant supply jacket 13 onto almost the entire back surface of the cap 6 of each chip carrier 1.
It will be done. The fine particles of the refrigerant that reach the back surface of the cap 6 are heated and rise to a temperature of 1. :The heat is removed from the back of the cap 6), and the chip carrier 1
Let it cool down. The refrigerant vaporized on the back of the cap 6 is
The coolant is discharged to the outside through the cooling block 18, the refrigerant discharge jacket 14, and the discharge port 16.

上記冷却41造においては、ノズル17の先端からキャ
ップ6の背面に到達し、たそれぞれの冷媒微粒子は、キ
ャップ6の背面の極めて微細な領域で沸騰するため、冷
媒は核沸騰に近い状態で沸騰する。そこで、ノズル17
の先端か・)吐出さix玲媒微杓了の種類や吐出t4最
適化し4、キヤ・lプ〔jの背面に供給4″る冷媒量と
沸騰する玲:*mh:iはぼ同(: i、”、’、、’
、 1’−6(、とに、にす、チップ5が動作11、′
τ゛いる間、冷媒を常に核飢騰1コ送い状蓄ひf2遭さ
(ることが又・きる。これにより、2冷媒の膜S @ 
I: l、る冷却効率の低ドを回避−4ることができる
の”て・、チップ5の過熱1こよる集積回路の誤1や、
チップ5の寿命低下を有効に防止することができる。
In the above-mentioned cooling system, each fine refrigerant particle reaches the back surface of the cap 6 from the tip of the nozzle 17 and boils in an extremely fine region on the back surface of the cap 6, so the refrigerant boils in a state close to nucleate boiling. do. Therefore, nozzle 17
Optimize the type of discharge ix and discharge t4, the amount of refrigerant supplied to the back of the cap, and the amount of refrigerant that boils: * mh: i is the same ( : i,",',,'
, 1'-6(, ni, nis, chip 5 operates 11,'
During the τ period, the refrigerant is always nuclear starved and the invoice is stored f2. This allows the refrigerant film S @
I: It is possible to avoid low cooling efficiency due to overheating of the chip 5, failure of the integrated circuit, etc.
It is possible to effectively prevent the life of the chip 5 from decreasing.

以上、本発明者によってなされた発明を実施例に基づき
具体的に説明し、だが、本発明は、前記実施例に限定さ
れるものではなく、その要旨を逸脱しない範囲で種・ヤ
変更可能であることはいうまでもない。
In the above, the invention made by the present inventor has been specifically explained based on examples, but the present invention is not limited to the above-mentioned examples, and the species and type can be changed without departing from the gist of the invention. It goes without saying that there is.

前a己実施例では、液体状の冷媒微粒子を用いた場合に
ついて説明したが、固体状の冷媒微粒子を用いることも
できる。
In the previous embodiments, the case where liquid refrigerant fine particles were used was described, but solid refrigerant fine particles may also be used.

前記実施例では、チップ→ヤリャの冷却技術に適用しま
た場合について説明したが、チップを気密封止した各種
構造のパッケージに適用することがて・きる。また、基
板上1こ天笠しブこ裸のチップ(ベアチップ)の背面に
直接冷媒微粒−f4吹きイ・フけで冷却を行うこともで
きる。
In the embodiment described above, the case was explained in which the present invention was applied to a cooling technique from a chip to a chip, but the present invention can also be applied to packages of various structures in which a chip is hermetically sealed. It is also possible to directly cool the back surface of a bare chip (bare chip) by blowing fine refrigerant particles -F4 on the substrate.

=発明の効果〕 本願において開示される発明のうち代表的なものによっ
て得るれる効果を簡単に説明すれば、下記の通りである
=Effects of the Invention] The effects obtained by typical inventions disclosed in this application are briefly explained below.

米導体チップ、または半導体チップを気密Itihした
パッケージの表面に固体、または液体からなる冷媒の微
粒子を吹き付ける半導体集積回路装置の冷却方法によれ
ば、冷媒を核沸騰に近い状態で涜騰させることができる
ので、膜沸騰による冷却効率の低下が回避され、半導体
チップから発生する熱を効率良(外部に逃がすことがで
きる。
According to a cooling method for semiconductor integrated circuit devices in which fine particles of a solid or liquid refrigerant are sprayed onto the surface of a conductor chip or a package in which a semiconductor chip is airtight, the refrigerant can boil to a state close to nucleate boiling. As a result, a decrease in cooling efficiency due to film boiling can be avoided, and the heat generated from the semiconductor chip can be efficiently released to the outside.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は、本発明の一実施例である半導体集積回路装置
の冷却構造を示す要部破断正面図、第2図は、チップキ
ャリヤ形半導体集積回路装置の要部破断正面図である。 1・・・チップキャリヤ、2・・・パッケージ基板2.
3・・・電極、4.11・・・半田バンプ、5・・・単
導体チップ、6・・・キャップ、7・・・封」−用崖田
、8・・・メタライズ層、9・・・伝熱用半田、10・
・・内部配線、12・・・モジュール基板、13・・・
冷媒供給用ジャケット、14・・・冷媒排出用ジャケッ
ト、15・・・供給口、16・・・排出口、17・・・
ノズル、18・・・冷却ブロック、19・・・ろう材、
2G・・・ベローズ。
FIG. 1 is a cutaway front view of a main part showing a cooling structure of a semiconductor integrated circuit device according to an embodiment of the present invention, and FIG. 2 is a cutaway front view of a main part of a chip carrier type semiconductor integrated circuit device. 1... Chip carrier, 2... Package substrate 2.
3... Electrode, 4.11... Solder bump, 5... Single conductor chip, 6... Cap, 7... Sealing cliff, 8... Metallized layer, 9...・Solder for heat transfer, 10・
...Internal wiring, 12...Module board, 13...
Refrigerant supply jacket, 14... Refrigerant discharge jacket, 15... Supply port, 16... Discharge port, 17...
Nozzle, 18... Cooling block, 19... Brazing metal,
2G...Bellows.

Claims (1)

【特許請求の範囲】 1、半導体チップ、または半導体チップを気密封止した
パッケージの表面に固体、または液体からなる冷媒の微
粒子を吹き付けることを特徴とする半導体集積回路装置
の冷却方法。 2、半導体チップ、または半導体チップを気密封止した
パッケージを基板の主面に実装し、前記半導体チップ、
またはパッケージの近傍に固体、または液体からなる冷
媒の微粒子が吐出される吹き付け手段を配置したことを
特徴とする半導体集積回路装置の冷却構造。 3、前記パッケージは、パッケージ基板の主面にフェイ
スダウンボンディングした半導体チップをキャップで気
密封止したチップキャリヤ構造を有していることを特徴
とする請求項2記載の半導体集積回路装置の冷却構造。
[Claims] 1. A method for cooling a semiconductor integrated circuit device, which comprises spraying fine particles of a solid or liquid refrigerant onto the surface of a semiconductor chip or a package in which the semiconductor chip is hermetically sealed. 2. A semiconductor chip or a package in which the semiconductor chip is hermetically sealed is mounted on the main surface of the substrate, and the semiconductor chip,
Alternatively, a cooling structure for a semiconductor integrated circuit device, characterized in that a spraying means for discharging fine particles of a solid or liquid refrigerant is arranged near the package. 3. The cooling structure for a semiconductor integrated circuit device according to claim 2, wherein the package has a chip carrier structure in which a semiconductor chip face-down bonded to the main surface of the package substrate is hermetically sealed with a cap. .
JP2170031A 1990-06-29 1990-06-29 Cooling method and structure for semiconductor integrated circuit devices Pending JPH0461259A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2170031A JPH0461259A (en) 1990-06-29 1990-06-29 Cooling method and structure for semiconductor integrated circuit devices

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2170031A JPH0461259A (en) 1990-06-29 1990-06-29 Cooling method and structure for semiconductor integrated circuit devices

Publications (1)

Publication Number Publication Date
JPH0461259A true JPH0461259A (en) 1992-02-27

Family

ID=15897324

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2170031A Pending JPH0461259A (en) 1990-06-29 1990-06-29 Cooling method and structure for semiconductor integrated circuit devices

Country Status (1)

Country Link
JP (1) JPH0461259A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2002046677A1 (en) * 2000-12-04 2002-06-13 Fujitsu Limited Cooling system and heat absorbing device
JP2007538384A (en) * 2004-02-24 2007-12-27 アイソサーマル システムズ リサーチ,インコーポレイティッド No hotspot spray cooling (relevant application) (Federal sponsored research or development statement) This invention was made with government support under # F33615-03-M-2316 contract ordered by the Air Force Institute . The government has certain rights in the invention.
US7498830B2 (en) 2004-07-30 2009-03-03 Espec Corp. Burn-in apparatus
US7558064B2 (en) 2004-07-30 2009-07-07 Espec Corp. Cooling apparatus

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2002046677A1 (en) * 2000-12-04 2002-06-13 Fujitsu Limited Cooling system and heat absorbing device
US7055341B2 (en) 2000-12-04 2006-06-06 Fujitsu Limited High efficiency cooling system and heat absorbing unit
JP2007538384A (en) * 2004-02-24 2007-12-27 アイソサーマル システムズ リサーチ,インコーポレイティッド No hotspot spray cooling (relevant application) (Federal sponsored research or development statement) This invention was made with government support under # F33615-03-M-2316 contract ordered by the Air Force Institute . The government has certain rights in the invention.
US7498830B2 (en) 2004-07-30 2009-03-03 Espec Corp. Burn-in apparatus
US7558064B2 (en) 2004-07-30 2009-07-07 Espec Corp. Cooling apparatus

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