JPH045833A - Junction-gate field-effect transistor - Google Patents

Abstract

PURPOSE:To prevent a cutoff frequency from being lowered, to restrain unstable operations such as a change in an output level by a pulse ratio, an operation following a signal pulse singly, a fluctuation in an operating point and the like and to stabilize a high-speed operation by a method wherein a reversed- polarity potential which constitutes a junction-gate FET is grounded by forming a low-resistance and high-concentration region. CONSTITUTION:A gate electrode 7 by a heat-resistant metal WSi-W is formed on a semiinsulating GaAs substrate 1; an N-type channel region 2 is formed under it; an N<+> type channel contact region 3 is formed so as to come into contact with it; a source electrode 8 and a drain electrode 9 of AuGeNi are attached onto it. On the other hand, a P-type reversed-polarity region 5 by implanting Be<+> ions is formed under the layer 2 and the region 3; a P-type ohmic electrode 10 of AuZn is formed on it; an element isolation region 6 whose resistance has been made high by causing a defect by implanting Be<+> ions is formed around an element. Mg, C or Zn may be used as ions; a potential at a reversed-polarity electrode can be grounded simply when it is connected to the source electrode.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a junction gate field effect transistor for high frequency and high speed signal processing.

(Prior Art) Compound semiconductors, represented by GaAs, have a feature of having higher electron mobility than 8i, and are increasingly being applied to amplifier elements for ultra-high frequency and ultra-high speed signal processing.

Here, a GaAs Schottky junction gate field effect transistor (hereinafter referred to as MESFET) will be explained as an example.

This MESFET is described on pages 5-49 of the Proceedings of the 1989 IEICE Autumn National Conference.
Simplification of sBPLDD-MESFET manufacturing process]
C-49) has been reported. This MESFET+7)
The new surface structure is shown in Figure 2. There is a Schottky junction gate electrode 7 on a semi-insulating GaAs substrate 1, and below it there is an n-type channel layer 2 formed by ion implantation. There is a channel contact region 3 as an n+ high concentration region, an ohmic source electrode 8 and a drain electrode 9 are provided on both channel contact regions 3, and an ohmic source electrode 8 and a drain electrode 9 are provided below the n-type channel layer 2 and contact region 3. There is a p-type reverse polarity layer 4, and element isolation regions 6 are formed around these element regions by introducing defects by ion implantation.

The purpose of this reverse polarity layer 4 is to suppress the short channel effect at short gate lengths and to improve the cutoff frequency. In order to suppress the substrate current in this reverse polarity layer, it was more effective to make the concentration higher to some extent.

(Problem to be solved by the invention) When a MESFET having such a reverse polarity layer is used for large amplitude signal processing, there are few problems when the signal has a square wave with an equal pulse ratio (01 ratio), but when the pulse When the ratios are different, the output level may fluctuate, or the output signal may not follow a single signal pulse, resulting in no output signal. Furthermore, when used for analog amplification, the operating point may fluctuate at low frequencies.

An object of the present invention is to solve these problems and provide a junction gate field effect transistor with stable circuit operation.

(Means for Solving the Problems) A junction gate field effect transistor of the present invention includes a junction gate electrode on a semiconductor substrate, a channel layer having carriers on the surface of the semiconductor substrate below the gate electrode, and a junction gate electrode on the semiconductor substrate. a channel contact region having a high concentration of carriers close to both sides of the channel layer and in contact with the channel layer; an ohmic source electrode and a drain electrode on both the channel contact regions; and an ohmic source electrode and a drain electrode below the channel layer and the channel contact region. a reverse polarity layer having opposite carriers, a highly concentrated reverse polarity region penetrating the channel contact region on the source electrode side and in contact with the reverse polarity layer, and a reverse polarity electrode on the surface of the high concentration reverse polarity region. It is characterized by having the following.

(Function) When the concentration of the reverse polarity layer is high in the conventional FET structure, the reverse polarity layer is not completely depleted due to the depletion layer extending from the channel layer. Charges accumulated in the reverse polarity layer due to changes in gate and drain potential are discharged in the forward pn direction,
There is a voltage of about 0.6V. Further, deep defect levels existing in the substrate have a long charging/discharging time constant, so that a reverse polarity layer floats. For this reason, it is thought that unstable phenomena have occurred, such as the charge accumulated in the reverse polarity layer suppressing the sudden change in gate potential, and the instability of deep defect levels causing the potential of the reverse polarity layer to fluctuate. It will be done.

In the present invention, by grounding the potential of the reverse polarity layer by providing a low resistance high concentration region, the potential of the reverse polarity layer is fixed and unstable phenomena are suppressed.

(Example) An example of a junction gate field effect transistor of the present invention will be described with reference to FIG. Semi-insulating GaAs substrate 1
There is a gate electrode 7 made of all-metal WSiW on top of the S
i+ is acceleration voltage 40 keV, implantation dose 1, I x 1
An n-type channel layer 2 ion-implanted at 0.013 cm-2 is below the gate electrode 7, and in contact with the n-type channel layer 2 is a Si
+130keV, 4. There is an n+ channel contact region 3 implanted with OX 1013 cm-2, above which A
There is a source electrode 8 and a drain electrode 9 of uGeNi. On the other hand, channel layer 2 and n+ channel contact region 3
Be+ is 70 keV under 4. OX 1012cm
There is a p-type reverse polarity layer 4 which is ion-implanted with 8.
There is a p-high concentration reverse polarity region 5 ion-implanted at cm-2, on the surface of which there is a p-type ohmic electrode 10 of AuZn. In addition, each ion-implanted impurity region was heated to 80°C2.
It is activated by annealing for 0 minutes, but B+ is 150 keV, 5, OX 1012 cm-2 around the device.
There is an element isolation region 6 which has been ion-implanted to create defects and have a high resistance.

The ion-implanted impurities for the p+ region include Mg in addition to Be.
, C, Zn, etc. are possible. Also, the implantation dose is 10
When the concentration is 15 cm-2 or more, the concentration is as high as 1019 cm-3, and ohmic properties can be obtained even with Schottky metals such as Ti and Cr without heat treatment. On the other hand, a similar high concentration can be obtained by diffusing Zn in a sealed tube at 600 to 700° C. using the SiN film used as the annealing protective film as a mask instead of ion implantation.

It is easy to ground the potential of the opposite polarity electrode to the source electrode. It is also possible to apply a potential different from that of the source, and when a negative potential is applied, the gate threshold voltage of the FET becomes relatively shallow, which can also be used to adjust the gate threshold voltage.

The characteristics of the FET obtained were that the gate length was 0.3 pm, the gate width was 50 pm, and the cutoff frequency of gate threshold voltage of -1 and 2 V was 40 GHz, which was almost the same as in the case without the p+ region, and there was no deterioration. By providing the p+ region, the operating point no longer fluctuates. Furthermore, fluctuations in the output level due to pulse ratios have been significantly suppressed, and the possibility of malfunctions caused by single pulses has also been significantly reduced.

Furthermore, in the above embodiments, the case where the channel layer 2 is n-type and the reverse polarity layer 4 is p-type has been described, but when the channel layer is p-type, the reverse polarity layer is n-type.

(Effects of the Invention) As explained above, in the junction gate field effect transistor of the present invention, the cutoff frequency etc. do not decrease.
Furthermore, the output level fluctuates depending on the pulse ratio, it does not follow a single signal pulse, and the operating point fluctuates.
This suppresses unstable operations such as the following, and enables stable high-speed operation.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of a junction gate field effect transistor according to the present invention, and FIG. 2 is a cross-sectional view of a conventional junction gate field effect transistor.
FIG. 3 is a cross-sectional view of a transistor. In the figure, 1... Semiconductor substrate, 2... Channel layer, 3... Channel contact region, 4... Reverse polarity layer, 6... High concentration reverse polarity region, 6... Element isolation region, 7... gate electrode, 8... source electrode, 9... drain electrode,
10...Reverse polarity electrode.

Claims (1)

[Claims] a junction gate electrode on a semiconductor substrate, a channel layer having carriers on the surface of the semiconductor substrate below the gate electrode, and a channel contact region having a high concentration of carriers close to both sides of the gate electrode and in contact with the channel layer. , comprising an ohmic source electrode and a drain electrode on both the channel contact regions, and an opposite polarity layer having opposite carriers below the channel layer and the channel contact region, and a channel contact region on the source electrode side. a high concentration reverse polarity region penetrating through and in contact with the reverse polarity layer;
A junction gate field effect transistor comprising a reverse polarity electrode on the surface of the high concentration reverse polarity region.