JPH0457108B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to the structure of a large-scale integrated circuit (LSI) consisting of multiple chips.

In recent years, LSIs have become increasingly large-scale, and chip sizes have become larger, leading to wafer-scale LSIs.
began to be studied, and LSIs called wafer integration (wafer IC), or functional wafers, began to appear.

In order to realize such an LSI, if input/output (I/O) is performed only by pads arranged around the periphery of a large chip or wafer using conventional assembly technology using wire bonding, the internal complex Since the circuit becomes completely inaccessible, the end result is a collection of small chips that are integrated on a flat surface.

On the other hand, studies have begun to consider a method of stacking chips three-dimensionally to achieve high integration. At present, the configuration is such that a small chip is stacked on top of a large chip such as the above-mentioned wafer IC, and both chips are connected, but there is a demand for the possibility of arranging chips in multiple layers.

[Conventional technology]

FIG. 2 is a sectional view showing the main points of a conventional multi-chip LSI.

In the figure, the second chip 2 is placed face-up on the first chip 1, and one pad is placed between the pad 2 formed on the first chip 1 and the pad 4 formed on the second chip 3. The wires were connected by wire bonding using the destination wire 5.

In this case, workability was poor, the area of the bonding pad was large, and there were problems in miniaturization.

FIG. 3 is a sectional view showing the main points of another conventional multi-chip LSI.

In the figure, using the flip-chip method, the second
The bumps (hemispherical connection terminals) 4B of the chip 3 are placed face down on the bumps 2B formed on the first chip 1, and the bumps are melted and connected. Alternatively, instead of bumps, beam leads were used to connect the wafer and chips.

In this case, there were problems such as the accuracy of chip alignment, the adhesion of the solder forming the bumps, a reduction in speed due to the capacitance of the bump pads, destruction of the elements under the pads, and heat dissipation.

[Problem that the invention seeks to solve]

In conventional multi-chip LSIs, the area of the pads required for inter-chip connections becomes large, making it difficult to miniaturize the chips, and as a result, high speed performance is also lost.

Furthermore, the three-dimensional structure of a chip with three or more layers is extremely difficult and impractical due to many restrictions.

[Means for solving problems]

The solution to the above problem is to stack semiconductor chips and transparent stretchable insulating films alternately on a stage, and each layer of the insulating film covers the semiconductor chip and covers any of the layers below. A flexible wiring pattern conductive film is formed in close contact with a lower layer insulating film, and connections between the semiconductor chips are formed in close contact with both surfaces of the insulating film, and in three holes opened in the insulating film. This is achieved by a semiconductor device which is formed by connecting the wiring pattern conductive films on both sides.

[Effect]

According to the present invention, a flexible film is used as an interlayer insulating layer between chips, and connections between chips are made using a flexible conductive layer formed on the flexible film and vias (connections on the front and back sides of the film). It can be carried out.

In addition, it is possible to simultaneously bond a large number of conductive patterns formed on a flexible film and a large number of pads formed on a chip, improving work efficiency. In particular, if a transparent film is used, alignment during bonding becomes easier. Become.

At this time, bias cuts (cuts made to promote expansion and contraction) may be made in the film to accommodate the misalignment of the chip.

〔Example〕

FIGS. 1a and 1b are a perspective view and a sectional view, respectively, showing the main points of a multi-chip LSI according to an embodiment of the present invention.

In the figure, 11 is a stage with high thermal conductivity, and the first layer of chips 12A, 12B, 1
2C,... are die bonded. The first layer of contact film 14 is placed on top of this and the chip 12
Bonding parts 1 of A, 12B, 12C, ...
3A, 13B, 13C, . . . and the conductive pattern 15 formed on the lower surface of the first contact film 14 are bonded.

A conductive pattern 16 is formed on the upper surface of the first layer contact film 14, and a via is formed at a predetermined position.
17A, 17B, 17C, . . . are formed, and conductive patterns 15 and 16 are connected.

Next, put the second layer of chips 18 on top of this.
A layer of contact film 20 is placed on the chip 18.
The conductive pattern 16 formed on the upper surface of the bonding pad 19 and the first contact film 14 is bonded to the conductive pattern 21 formed on the lower surface of the second contact film 20.

A conductive pattern 22 is formed on the upper surface of the second layer contact film 20, and a via is formed at a predetermined position.
23 is formed, and the conductive patterns 21 and 22 are connected.

Next, put the third layer of chips 24 on top of this.
Place the contact film 26 of the second layer and insert the chip 2.
4 bonding pad 25, the conductive pattern 22 formed on the top surface of the second layer contact film 20, the conductive pattern 16 formed on the top surface of the first layer contact film 14, and the third layer contact film 26. A conductive pattern 27 formed on the lower surface of the chip is bonded to complete the interconnection between the chips.

The LSI configured as described above has the following advantages.

The heat dissipation of the first layer chip is good. Therefore, bipolar high-speed circuits, power supply circuits, etc. are inserted here.

Positioning is easy using a transparent film.

It is possible to make the pad smaller than in the case of wire bonding.

Multiple simultaneous bonding is possible and productivity is good.

The elasticity of the film makes it possible to package chips in multiple layers, resulting in a high-density three-dimensional LSI.

Traditional packaging can be used.

〔Effect of the invention〕

As described in detail above, according to the present invention, the area of pads required for inter-chip connections in a multi-chip LSI becomes smaller, allowing miniaturization, and therefore high speed can be maintained.

Furthermore, a three-dimensional structure of the chip with three or more layers becomes possible.

[Brief explanation of the drawing]

1A and 1B are a perspective view and a cross-sectional view showing the main points of a multi-chip LSI according to an embodiment of the present invention, FIG. 2 is a cross-sectional view showing the main points of a multi-chip LSI according to a conventional example, and FIG. FIG. 2 is a cross-sectional view showing the main points of a conventional multi-chip LSI. In the figure, 1 is the first chip, 2 and 4 are pads, 2B and 4B are bumps, 3 is the second chip, 1
1 is a stage, 12A, 12B, 12C,... are first-layer chips, 13A, 13B, 13C,... are bonding pads, 14 is a first-layer contact film, 15, 16 are conductive patterns, 17A,
17B, 17C, ... are vias, 18 is a second layer chip, 19 is a bonding pad, 20 is a second layer contact film, 21, 22 are conductive patterns, 23 is a via, 24 is a third layer chip, 25 is a bonding pad, 26 is a third layer contact film, and 27 is a conductive pattern.

Claims (1)

[Claims] 1 Semiconductor chips and transparent stretchable insulating films are alternately laminated on a stage,
The insulating film of each layer covers the semiconductor chip and is in close contact with any lower insulating film below that layer, and the connection between the semiconductor chips is a flexible film formed in close contact with both surfaces of the insulating film. What is claimed is: 1. A semiconductor device comprising: a conductive film with a wiring pattern; and a connection formed in a through hole opened in the insulating film to connect the conductive film with the wiring pattern on both sides.