JPH0456158A - Surface mounting semiconductor package - Google Patents
Surface mounting semiconductor packageInfo
- Publication number
- JPH0456158A JPH0456158A JP16339290A JP16339290A JPH0456158A JP H0456158 A JPH0456158 A JP H0456158A JP 16339290 A JP16339290 A JP 16339290A JP 16339290 A JP16339290 A JP 16339290A JP H0456158 A JPH0456158 A JP H0456158A
- Authority
- JP
- Japan
- Prior art keywords
- pin
- hole
- board
- diameter
- terminal pin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 17
- 239000000758 substrate Substances 0.000 claims description 13
- 230000037431 insertion Effects 0.000 claims 1
- 238000003780 insertion Methods 0.000 claims 1
- 229910000679 solder Inorganic materials 0.000 abstract description 15
- 239000011347 resin Substances 0.000 description 7
- 229920005989 resin Polymers 0.000 description 7
- 239000000463 material Substances 0.000 description 6
- 229910000906 Bronze Inorganic materials 0.000 description 2
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 2
- 239000010974 bronze Substances 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- KUNSUQLRTQLHQQ-UHFFFAOYSA-N copper tin Chemical compound [Cu].[Sn] KUNSUQLRTQLHQQ-UHFFFAOYSA-N 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 235000002568 Capsicum frutescens Nutrition 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 241000270722 Crocodylidae Species 0.000 description 1
- 229910000640 Fe alloy Inorganic materials 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 239000004721 Polyphenylene oxide Substances 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- LNNWVNGFPYWNQE-GMIGKAJZSA-N desomorphine Chemical compound C1C2=CC=C(O)C3=C2[C@]24CCN(C)[C@H]1[C@@H]2CCC[C@@H]4O3 LNNWVNGFPYWNQE-GMIGKAJZSA-N 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- -1 fluororesin Substances 0.000 description 1
- 239000003365 glass fiber Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 229910010272 inorganic material Inorganic materials 0.000 description 1
- 239000011147 inorganic material Substances 0.000 description 1
- 229910052742 iron Inorganic materials 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 239000005011 phenolic resin Substances 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 229920006380 polyphenylene oxide Polymers 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、半導体搭載用に用いられる表面実装用の半
導体パッケージに係る。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a surface mounting semiconductor package used for mounting a semiconductor.
プリント配線板による表面実装用の半導体パッケージと
して第５図に示した特開昭６１−１７４７５２号公報に
開示されたものがある。プリント配線板１の表面に形成
された導体回１ｓ５は貫通孔２を通じて裏面へ展設され
、貫通孔２にはピン３などの穴埋め剤が半田４が確実に
厚く盛れるようにフラット化され、半田４のバンプが厚
く形成できるものである。しかし、半田４のバンプが厚
く形成できたものであっても、この半導体パッケージを
マザーボード上の導電パターンと半田４のバンプによっ
て接続するには、半田がマザーボードの反りやねじれの
隙間を埋める支柱材とはなりえないので、マザーボード
に反りやねじれのないことが必須条件になり表面実装上
の問題を残していた。A semiconductor package for surface mounting using a printed wiring board is disclosed in Japanese Patent Application Laid-Open No. 174752/1983 as shown in FIG. The conductor circuit 1s5 formed on the front surface of the printed wiring board 1 is extended to the back surface through the through hole 2, and the through hole 2 is flattened with a hole filler such as a pin 3 to ensure that the solder 4 is applied thickly. The bumps of solder 4 can be formed thickly. However, even if the bumps of solder 4 can be formed thickly, in order to connect this semiconductor package to the conductive pattern on the motherboard and the bumps of solder 4, the solder must be used as a supporting material to fill in the gaps caused by warping or twisting of the motherboard. Therefore, it is essential that the motherboard is free from warping and twisting, which leaves problems with surface mounting.
マザーボードの反りやねじれに係わり無く表面実装が容
易に行える表面実装用パンケージを提供することにある
。To provide a surface mounting pancase that allows surface mounting to be easily carried out regardless of warping or twisting of a motherboard.
本発明は、前記の課題を解決するため絶縁基板の表面か
ら端子ピンが突出した表面実装用の半導体パッケージに
おいて、絶縁基板に形成された貫通孔に、この貫通孔よ
り小さい径の外部接続用の端子ピンが挿入され、この端
子ピンの突出した端部の少なくとも一方は、挿入部分よ
り大きな形状の鍔を有することを特徴とする表面実装用
半導体パッケージである。In order to solve the above-mentioned problems, the present invention provides a semiconductor package for surface mounting in which terminal pins protrude from the surface of an insulating substrate. The present invention is a surface-mount semiconductor package in which a terminal pin is inserted, and at least one of the protruding ends of the terminal pin has a flange larger than the inserted portion.
以下、図面にしたがって本発明の一実施例について説明
する。An embodiment of the present invention will be described below with reference to the drawings.
第１図の断面図は本発明の一実施例に係る表面実装用半
導体パッケージを示す。この表面実装用半導体パ、７ケ
ージは、絶縁基板１に形成された円形の貫通孔２、この
貫通孔２の径より小さな径の円柱状の端子ピン３が貫通
孔２に挿入されたものである。この端子ピン３の絶縁基
板１から突出した端部は貫通孔２の径より大きな径の鍔
６を有している。この端子ピン３は貫通孔２において、
半田４によって一時固定されている。この表面実装用半
導体バ、ケージをマザーボードに半田リフローで実装す
るとき、−時固定の半田４が融け、貫通孔２の径より端
子ピン３の径が小さいことから端子ピン３が上下に自由
に動くことができ、マザボートの反りやねしれに端子ピ
ン３が追随して取りつけることができるのである。さら
に、端子ピン３が絶縁基板から突出した部分の鰐６の形
状は断面Ｔ字状に形成され、広い面形状を有するために
マザーボードの導電パターンとの接続面積が拡大するの
で接続の信顛性も向上するのである。The sectional view of FIG. 1 shows a surface mounting semiconductor package according to an embodiment of the present invention. This surface mounting semiconductor package 7 cage has a circular through hole 2 formed in an insulating substrate 1, and a cylindrical terminal pin 3 having a smaller diameter than the through hole 2 is inserted into the through hole 2. be. The end of the terminal pin 3 protruding from the insulating substrate 1 has a flange 6 having a diameter larger than the diameter of the through hole 2. This terminal pin 3 is located in the through hole 2,
It is temporarily fixed with solder 4. When this surface mounting semiconductor bar or cage is mounted on a motherboard by solder reflow, the fixed solder 4 melts, and since the diameter of the terminal pin 3 is smaller than the diameter of the through hole 2, the terminal pin 3 can move up and down freely. It can move, and the terminal pins 3 can be attached to the motherboard by following the warping or twisting of the motherboard. Furthermore, the shape of the crocodile 6 in the portion where the terminal pin 3 protrudes from the insulating substrate is formed into a T-shaped cross section, and has a wide surface shape, which increases the connection area with the conductive pattern of the motherboard, thereby improving the reliability of the connection. It also improves.
第２図は、貫通孔２に挿入した端子ピン３を絶縁基板１
から突出した上下の鍔６で抜けないようにした他の実施
例であり、特に半田で一時固定しなくても良い場合を示
す。第３図と第４図は、貫通孔２に挿入した端子ピン３
を半田４で一時固定した他の実施例である。Figure 2 shows the terminal pin 3 inserted into the through hole 2 placed on the insulating substrate 1.
This is another embodiment in which upper and lower flanges 6 protruding from the top and bottom prevent it from coming off, and particularly shows a case where temporary fixation with solder is not required. Figures 3 and 4 show the terminal pin 3 inserted into the through hole 2.
This is another embodiment in which the wire is temporarily fixed with solder 4.
端子ピン３の形状は、第２図の絶縁基板１からの突出し
た端部が円盤状や円錐台状の鍔６である端子ピン３でも
よく、第３図の円柱の一方の端部に円盤状の鍔６の付い
た断面Ｔ字型の端子ピン３でもよく、第４図の円柱の一
方の端部に円錐台状の鍔６の付いた断面路Ｔ字型の端子
ピン３でもよい。また、このような円柱状の端子ピンす
なわち、平面円形に限るものではなく平面が足型、十字
型の形状など適宜選ぶことができるものである。The shape of the terminal pin 3 may be a terminal pin 3 in which the end protruding from the insulating substrate 1 in FIG. The terminal pin 3 may have a T-shaped cross section with a cylindrical flange 6, or the terminal pin 3 may have a T-shaped cross section with a truncated conical flange 6 at one end of the cylinder shown in FIG. Further, such a cylindrical terminal pin is not limited to a circular shape in plan view, but can be appropriately selected such as a foot-shaped planar shape, a cross-shaped planar shape, etc.
このときは、これら足型、十字型の凹凸の稜線で一時固
定することもできる。At this time, it can be temporarily fixed using the ridge lines of these foot-shaped and cross-shaped unevenness.
次に、表面実装用半導体パッケージの使用材料について
述べる。第１図から第４図の表面実装用半導体パノケー
ノを構成する絶縁基板１には、アルミナ、窒化珪素など
のセラミック基板や基材に樹脂を含浸乾燥して得られた
プリプレグの樹脂を硬化させた絶縁樹脂材料などを用い
ることができる。この絶縁樹脂材料の樹脂としては耐熱
性、耐湿性に優れかつ樹脂純度、特にイオン性不純物の
少ないものが好ましい。具体的にはエポキシ樹脂、ポリ
イミド樹脂、弗素樹脂、フェノール樹脂、ポリフェニレ
ンオキサイド樹脂などの樹脂が適している。なお、基材
としては、ガラス繊維などの無機材料の方が有機材料よ
りも耐熱性、耐湿性などに優れ好ましい。Next, the materials used in the surface-mount semiconductor package will be described. The insulating substrate 1 constituting the surface-mount semiconductor pannocene shown in FIGS. 1 to 4 is made of a prepreg resin obtained by impregnating and drying a ceramic substrate or base material such as alumina or silicon nitride with a resin. An insulating resin material or the like can be used. The resin for this insulating resin material is preferably one that has excellent heat resistance and moisture resistance, and has high purity, especially low ionic impurities. Specifically, resins such as epoxy resin, polyimide resin, fluororesin, phenol resin, and polyphenylene oxide resin are suitable. Note that as the base material, inorganic materials such as glass fibers are preferable because they have better heat resistance and moisture resistance than organic materials.
外部接続用の端子ピン３としては、銅、りん青銅、アル
ミニウム、鉄、鉄合金などの金属の線材から用途に応し
て適宜選択し、さらに、金、銀、半田などのメツキ加工
し使用することができる。The terminal pin 3 for external connection is selected from metal wires such as copper, phosphor bronze, aluminum, iron, and iron alloys depending on the application, and is then plated with gold, silver, solder, etc. be able to.
中でちりん青銅が、加工のし易さ、電気抵抗の小さい点
で優れ、好んで用いることができる。Among these, chili bronze is preferred because it is easy to process and has low electrical resistance.
〔作用］
貫通孔の径より端子ピンの径が小さいことから端子ピン
が上下に自由に動くことができ、マザボードの反りやね
しれに追随可能なのである。さらに、貫通孔に挿入され
た端子ピンの絶縁基板から突出した端子ピンの鍔がピン
の軸径より大きいのでマザーボードの導電パターンとの
接続面積を拡大し、接続信頼性を向上させるのである。[Function] Since the diameter of the terminal pin is smaller than the diameter of the through hole, the terminal pin can move freely up and down, and can follow the warping or twisting of the motherboard. Furthermore, since the collar of the terminal pin inserted into the through-hole protruding from the insulating substrate is larger than the shaft diameter of the pin, the connection area with the conductive pattern of the motherboard is expanded and connection reliability is improved.
本発明の表面実装用半導体パッケージによって端子ピン
が可動できる構成のために、マザーボドの反りやねしれ
に係わり無く端子ピンがマザボードに追随し、表面実装
が容易にかつ確実に行えるのである。Since the surface mounting semiconductor package of the present invention allows the terminal pins to move, the terminal pins follow the motherboard regardless of the motherboard's warpage or twisting, and surface mounting can be easily and reliably performed.
第１図は本発明の一実施例の断面図、
第２図、第３図、第４図は本発明のそれぞれ異なる他の
実施例の断面図、
４図は一従来例の断面図である。
第１
図
１・・・絶縁基板
２・・・貫通孔
３・・・端子ピン
４・・・半田
５・・・導体回路
６・・・鍔
第２
因
第３
第４図
特許出願人 松下電工株式会社
代理人弁理士 佐藤成示 （ほか１名）第５
凶
手続補正書（方式）
％式％
事件の表示
平成２年 特許願 第１６３３９２号
発明の名称
表面実装用半導体パンケージ
補正をする者
事件との関係 特許出願人
補正の内容
（１）明細書の第７頁第２行の「第４図は一従来例の断
面図である。」を 「第５図は一従来例の断面図である
。」に訂正します。
以上
代表者 二好俊夫
平成２年
９月２５日
（全送日）FIG. 1 is a cross-sectional view of one embodiment of the present invention, FIGS. 2, 3, and 4 are cross-sectional views of other different embodiments of the present invention, and FIG. 4 is a cross-sectional view of a conventional example. . 1st Figure 1...Insulating substrate 2...Through hole 3...Terminal pin 4...Solder 5...Conductor circuit 6...Tsuba 2nd factor 3rd figure 4th patent applicant Matsushita Electric Works Representative Patent Attorney Shigeji Sato (and 1 other person) No. 5 Written Amendment (Method) % Formula % Display of the Case 1990 Patent Application No. 163392 Title of the Invention Case of a person making an amendment to a semiconductor package for surface mounting Relationship with Contents of Patent Applicant's Amendment (1) Change ``Figure 4 is a cross-sectional view of a conventional example'' to ``Figure 5 is a cross-sectional view of a conventional example'' in the second line of page 7 of the specification. There is.'' Representative: Toshio Niyoshi September 25, 1990 (all sending dates)
Claims (1)
用の半導体パッケージにおいて、絶縁基板に形成された
貫通孔に、この貫通孔より小さい径の外部接続用の端子
ピンが挿入され、この端子ピンの突出した端部の少なく
とも一方は、挿入部分より大きな形状の鍔を有すること
を特徴とする表面実装用半導体パッケージ。(1) In a surface mount semiconductor package in which a terminal pin protrudes from the surface of an insulating substrate, a terminal pin for external connection with a smaller diameter than the through hole is inserted into a through hole formed in the insulating substrate, and the terminal pin is inserted into a through hole formed in the insulating substrate. A semiconductor package for surface mounting, wherein at least one of the protruding ends of the pin has a flange larger in shape than the insertion portion.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16339290A JPH0456158A (en) | 1990-06-21 | 1990-06-21 | Surface mounting semiconductor package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16339290A JPH0456158A (en) | 1990-06-21 | 1990-06-21 | Surface mounting semiconductor package |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0456158A true JPH0456158A (en) | 1992-02-24 |
Family
ID=15773018
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16339290A Pending JPH0456158A (en) | 1990-06-21 | 1990-06-21 | Surface mounting semiconductor package |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0456158A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5889333A (en) * | 1994-08-09 | 1999-03-30 | Fujitsu Limited | Semiconductor device and method for manufacturing such |
| US6031283A (en) * | 1996-09-09 | 2000-02-29 | Intel Corporation | Integrated circuit package |
| JP2001035968A (en) * | 1999-07-01 | 2001-02-09 | Intersil Corp | Power semiconductor mounting package equipped with ball grid array |
| CN100464429C (en) * | 2003-10-28 | 2009-02-25 | 株式会社半导体能源研究所 | Liquid crystal display device, manufacturing method thereof, and liquid crystal television receiver |
-
1990
- 1990-06-21 JP JP16339290A patent/JPH0456158A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5889333A (en) * | 1994-08-09 | 1999-03-30 | Fujitsu Limited | Semiconductor device and method for manufacturing such |
| US6031283A (en) * | 1996-09-09 | 2000-02-29 | Intel Corporation | Integrated circuit package |
| JP2001035968A (en) * | 1999-07-01 | 2001-02-09 | Intersil Corp | Power semiconductor mounting package equipped with ball grid array |
| CN100464429C (en) * | 2003-10-28 | 2009-02-25 | 株式会社半导体能源研究所 | Liquid crystal display device, manufacturing method thereof, and liquid crystal television receiver |
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