JPH045584A - Ic testing device - Google Patents

Abstract

PURPOSE:To test an IC efficiently by providing a timing generator which generates a timing clock for each test pin and generating the timing clock which is a set quantity delayed behind each reference clock by the timing generator. CONSTITUTION:Timing generators 131 - 13n which generate timing clocks are provided corresponding to test pins 141 - 14n. Then the output timing clocks of the generators 131 - 13n are supplied to timing switching circuits 311 - 31n, whose outputs are supplied to waveform shaping circuits 161 - 16n and comparators 191 - 19n. Further, reference clocks from a reference clock generator 11 is supplied to a switching signal generator 32, which outputs a switching signal in test cycles. The timing generators 131 - 13n generate the timing clocks which are the set quantity delayed behind the respective reference clocks.

Description

Detailed Description of the Invention "Industrial Application Field" This invention shapes the waveform of a pattern from a pattern generator using a timing clock and supplies it to an IC device under test, so that the output of the IC device under test is set to an expected value. The present invention relates to an IC testing device that tests an IC device under test by comparing the timing of a timing clock, and particularly relates to a timing clock generating section thereof.

"Prior Art" FIG. 5 shows a conventional IC testing device. A reference clock for each test cycle is supplied from a reference clock generator 11 to a pattern generator 12 and a timing generator 13. The pattern generator 12 outputs the IC under test for each test cycle.
A pattern to be applied to the device and an expected value for the output from the IC device under test are generated, and the timing generator 13 generates various types of timing clocks (P types in total) delayed by a set delay amount with respect to the reference clock. .

A clock selection circuit 15 for each of the test bins 141-141 of the IC test equipment. ~15. ．． is established,
Each of these clock selection circuits 15+ to 15. In each test bin, q clocks (q
<p) timing clock is selected. A portion of these selected timing clocks is transmitted to each waveform shaping circuit 16. ~16. .

are supplied to these waveform shaping circuits t6. A pattern is supplied from the pattern generator 12 to each waveform shaping circuit 161 to 167. The waveform shaping circuit 16. creates a waveform to be applied to the IC device under test at the timing using the input pattern and timing clock. ~16,
Each output waveform of the driver 17. ~17. Through the test pin 14. ~14. The signal is applied to the corresponding bin of the IC device under test 18 through the signal line. IC device under test 1
The outputs of 8 are connected to the corresponding test pins 141-14. through comparators 191-19. The clock selection circuits 15+ to 15. The respective outputs of these comparators 19, .about.19.degree. ~21° and compared with the expected value from pattern generator I2.

These logic comparison circuits 21. The outputs of the comparison results of 21 and 21 are supplied to a common OR circuit 22. Logical comparison circuit 21
, ~217 are each set to “1” if the comparison results do not match.
The output of the OR circuit 20 is output as a comparison result, and a result of determining whether the device under test 18 is good or bad.

This conventional IC testing device has the expensive timing generator 13 in common, so it can be configured at a relatively low cost, but the timing clock seeds W4 (number) generated by the timing generator 13 are limited. Therefore, a clock selection circuit 15 for each test pin is required. ~15. In this case, a timing clock cannot be freely selected, and a timing clock close to a desired timing clock must be selected.

On the other hand, conventionally, as shown in FIG. 6, each test pin 14. ~14, respectively timing generator 1
3. ~13. These timing orderers 13. ~
13. ．． , respectively, generate timing clocks necessary for the test pins, and transmit them to waveform shaping circuits 161 to 16, l and comparators 191 to 19.1, respectively.
Some are designed to supply to l. In this case, the timing generator 13. ~13. Each configuration can be made relatively simple, and a desired timing clock can be freely generated for each test bin.

"Problem to be Solved by the Invention" As an IC element to be tested, for example, as shown in FIG.
The signal of gate 23.2 is fed to gate 23.24.
The signals from the bins 25 and 26 are supplied to the gates 24 and 24, respectively, and the outputs of the gates 23 and 24 are supplied to the data terminal of the flip-flop 28 through the OR circuit 27, and the input of this data terminal is connected to the signal from the bin 29. Assume that there is a circuit that takes in the Fugutsubu flop 2B. In this case, when measuring the set-up time Ts and hold time Th for the flip-flop 28 of the input of the bin 22 with respect to the input of the bin 29, the input of the bin 22 must be set up through the gate 23 in order to perform accurate measurement.

The measured value may be different between the path to the flip-flop 28 and the path to the flip-flop 28 through the gate 24. Therefore, in the cycle in which the input of the bin 22 in the test pattern is taken into the flip-flop 28, it is not possible to measure Ts and rh by slightly shifting the input timing of the bin 220 for each series of tests. The test pattern for IC elements is IC
Internal gate logic malfunction or disconnection, etc.
It is made to detect defects inside the C element and is made by an electronic computer. Changing part of this test pattern is a big deal. Therefore, in the above example, a new test pattern is created in which only the path where the input of bin 220 passes through gate 23 is created, and the input phase of bin 22 is changed in the test cycle in which the input of bin 22 in the test pattern is taken into flip-flop 28. A slight shift is performed every time a series of test patterns are tested, and Ts and Th when passing through the gate 23 are determined. Similarly, we created a new test pattern in which only the path where the input of pin 22 passes through gate 24 operates, and using this test pattern, we slightly shifted the input phase of pin 22 for each test of a series of test patterns. Find Ts and Th when passing through 24.

There is relatively no problem if the internal circuit configuration of the IC device under test 18 is simple as shown in FIG. It becomes necessary to make a

"Means for Solving the Problem" In the present invention, a timing generator is provided for each test pin, and at least one of the timing clock for waveform shaping timing or the timing clock for expected value comparison timing is a timing generator. Two timing clocks from the device are switched and supplied by a timing switching circuit. A switching signal is output from a switching signal generator in a test cycle of a specific test pattern, and the timing switching circuit is switched and controlled by the switching signal.

Embodiment J An embodiment of the present invention is shown in FIG. 1, and parts corresponding to those in FIG. 6 are given the same reference numerals. The outputs of the timing switching circuits 31. to 31. are supplied to the waveform shaping circuits 16. to 16° and the comparators 19. to 16°, respectively.
~19°. The reference clock from the reference clock generator 11 is also supplied to the switching signal generator 32, and the switching signal generator 32 outputs a switching signal in a set test cycle. In other words, since it is known in advance in which test cycle a specific pattern in the pattern generated by the pattern generator 12 occurs, the switching signal generator 32 outputs the switching signal in that test cycle. Configure. Alternatively, the output pattern of the pattern generator 12 is branched and supplied to the switching signal generator 32, and when a specific set pattern is input, the switching signal generator 32 detects this and outputs a switching signal. The timing switching circuit 31 . ~31. is switched and controlled.

Next, a specific example of one test pin 14i will be explained with reference to FIG. 2, and FIG.
A reference clock shown in is generated and the timing generator 13
In FIG. 3B, timing clocks B and C delayed by a set amount with respect to each reference clock are shown in FIG.
This occurs as shown in C. These timing clocks B
, C are the gates 3 in the timing switching circuit 31i, respectively.
In this example, the timing clock C is supplied to the comparator 19i through the timing switching circuit 31i. The switching signal from the switching signal generator 32 is supplied to the gate 35 in the timing switching circuit 31i. The output of the register 36 is also supplied to the gate 35 . The register 36 has this timing switching circuit 31.
When switching the timing with t, the control device must set “1” in advance.
” is stored, and “0” is stored when timing switching is not performed.The output of the gate 35 is directly supplied to the gate 34 and is inverted by the inverter 37 and supplied to the gate 33. The respective outputs of the gates 33 and 34 are supplied to the OR circuit 38, and the output of the OR circuit on the third day is supplied to the waveform shaping circuit 164 as the output of the timing switching circuit 31i.The waveform shaping circuit 16i is used when shaping into an NRZ waveform. The output timing clock of the OR circuit 3 is supplied to the gate 39.41, and the pattern from the pattern generator 12 is supplied to the gate 39 and is also supplied to the gate 41 through the inverter 42. Flip-flop 43 is set, and the output of gate 41 resets flip-flop 43. The output of flip-flop 43 is supplied to driver 17i.

If the pattern from the pattern generator 12 is as shown in Figure 3, for example, and no switching signal is generated from the switching circuit 32, the output of the switching signal generator 32 is "0" as shown in Figure 3. , the flip-flop 43 is set by the clock when the pattern is "1", and the pattern is "1".
The flip-flop 43 is reset by the clock B when the clock is 0'', and the output shown in FIG. 3F is obtained from the flip-flop 43. In the example of FIG. As shown in FIG.
6 stores "B"), the timing switching circuit 31i is switched and the timing clock C is supplied to the waveform shaping circuit 16i instead of the timing clock B, and the flip-flop 43 is set. The pattern applied to the IC device under test through this test pin 14i has a phase of clock B for this test cycle.
will be changed from C to C.

Therefore, when applying this figure to the measurement of the setup time Ts and hold time Th taken from the pin 22 to the flip-flop 28 in the example shown in figure 7, it is necessary to For example, gate 2 in the test pattern for detecting internal defects.
The switching signal generator 32 outputs the switching signal in a specific pattern, that is, in a cycle in which the input of the pin 22 passes through the switching signal generator 32.
Ts is set by sequentially shifting the phase of the timing clock C for each test of this series of test patterns.

Th is measured, and then the switching signal generator 32 is set so that the switching signal is generated in the cycle (specific pattern) in which the input of the pin 22 passes through the gate 24, and the timing clock C is set for each test of a series of test patterns. Ts and Th are measured by sequentially shifting the phase of . In this way Ts
, Th can be measured using a normal test pattern for detecting internal defects in this IC element without creating a special test pattern for measuring Ts and Th.

Timing generator 13. ~13. is the number of timing clocks required for one test pin, typically 3 to
Approximately seven timing clocks are generated, but as shown in FIG. Not all timing generators necessarily use all of their generated timing clocks, and some timing generators may use fewer timing clocks than they can generate; The extra timing clock may be used for switching, and in some cases, it may be possible to switch not only between two timing clocks, but also between three or more timing clocks, or to switch multiple sets of timing clocks. It may be provided.

Conventionally, in order to change the timing clock in the middle of testing a series of test patterns, a timing memory is provided in the timing generator, and this timing memory is sequentially read out for each reference clock (each test cycle). Since a timing clock is generated according to timing information, the configuration of one timing generator becomes extremely complicated. However, the timing generators 131 to 13 in this invention. has a simple configuration in which the timing is set before testing a series of test patterns and the timing clock is not changed during the test, without a complicated configuration that changes the timing clock for each test cycle. Moreover, during a series of tests, the timing switching circuits 311 to 31. The timing clock can be changed by controlling the .

In this case, the timing switching circuit 31. ~31. l is required, but this configuration is extremely simple.

In the embodiment of FIG. 1, test pin 14. -14° is all input/output pins, but it may also be an input pin or an output pin.Therefore, in the case of an output pin, there is a margin in the number of timing clocks of the timing generator, and for example, the first, It is also possible to create and output an RZ waveform using the second timing clock, and to create and output an RZ waveform using the third and fourth timing clocks in the case of a specific pattern. FIG. 4 shows another embodiment of the present invention. In this example, a common timing generator 13 is also provided, and timing switching circuits 31I--
3111, each corresponding timing generator 131
In addition to switching the timing clocks from the timing generator 13 to 131, the timing clock from the timing generator 13 can also be switched and output. In such a configuration, the timing generators 131-13. The timing generator 1
The timing clock from 3 can be used as the switching timing clock.

"Effects of the Invention" As described above, according to the present invention, the timing clock is configured to be switched at a specific set cycle (pattern). Ts.

AC parameters such as Th can be measured, and A
There is no need to create a large number of test patterns for C parameter measurement, and timing generators 13I-13.
The timing clock can be switched during testing using a simple closure, which is extremely convenient.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a block diagram showing a specific example of the timing generator, timing switching circuit, and waveform shaping circuit, and FIG. 3 is an example of the operation of FIG. 2. 4 is a block diagram showing another embodiment of the present invention, FIGS. 5 and 6 are block diagrams showing conventional IC test equipment, and FIG. 7 is a block diagram showing a conventional IC test device.
FIG. 2 is a logic circuit diagram showing an example of an element. Patent applicant Atopantest Co., Ltd.

Claims (1)

[Claims] (1) Waveform shaping the pattern from the pattern generator using a timing clock and supplying it to the IC device under test, and comparing the output of the IC device under test with the expected value at the timing of the timing clock. IC that performs the test
In the test equipment, a timing generator that generates the timing clock is provided for each test pin, and at least one of the timing clocks for the waveform shaping timing or the expected value comparison timing is generated from the timing generator. Two timing clocks are switched and supplied by a timing switching circuit, and a switching signal generator is provided for generating a switching signal for switching and controlling the timing switching circuit in a test cycle of a specific one of the patterns. IC testing equipment.