JPH0453262A - Semiconductor device and manufacture thereof - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Table of Contents] Overview Industrial Application Fields Conventional Technology Problems to be Solved by the Invention Means for Solving the Problems Actions Embodiments 1 Manufacturing process cross-sectional view according to the embodiments (Fig. 1) ) Effects of the invention (Summary 1) Regarding a method of manufacturing a semiconductor device, particularly a method of manufacturing a DRAM cell having a stacked capacitor with a multilayer fin structure,
, AM cells have become highly integrated1, and even when the capacitors of adjacent cells are arranged close to each other, "Z" is formed on the gap between the capacitors of the insulating film formed to cover the cell. The purpose of the present invention is to provide a manufacturing method in which the insulating film is not formed, thereby preventing the deterioration of the passivation function of the insulating film and short circuits between the metal wiring formed in the insulating film-L, and improving the reliability of the DRAM. , the storage electrode has a storage capacitor having a plurality of layers of mutually connected fins covered with a counter electrode through a dielectric film, and the fins of the storage electrode are formed to become smaller as the layer increases. an etching-resistant film is formed on the semiconductor substrate, and a plurality of spacer films and a plurality of conductor films are formed on the etching-resistant film so that the spacer films become the bottom layer and the top layer. A step of alternately laminating the spacer film and the conductive film, a step of forming a contact hole that penetrates the etching-resistant film and the insulating film below it and exposes the semiconductor substrate surface, and a step of forming the contact ball. A step of covering the surface of the laminated film including the inner surface with the uppermost conductive film, forming a resist film on the uppermost conductive film, and performing a first etching for forming dividing grooves in the resist film. The step of forming a hole for etching, through the first hole for etching, isotropic etching or anisotropic dry etching and isotropic etching to the uppermost conductor film and the uppermost spacer film. forming a first groove having a first undercut I portion of a predetermined width at the bottom of the resist film; By dry etching, the spacer film of the uppermost layer is
A step of forming a second etching hole that exposes the conductor nl in the second layer from above, isotropic etching or rock etching is performed through the first etching hole and the second etching hole. Through directional dry etching and isotropic etching, the second conductor film reaches the second spacer film from above, and a second underlayer of a predetermined width is formed below the top spacer film. forming a second groove having a cut portion and enlarging the first undercut portion at the same time; after removing the resist film, selectively etching away the spacer film to remove the plurality of grooves; A method for manufacturing a semiconductor device including a step of forming a plurality of layers of interconnected fin structure electrodes made of conductive films.

[Industrial application field]

The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a DRAM cell having a stacked capacitor having a multilayer fin structure.

DRA with high density of 1 megabit or more, M
In recent years, as the storage node structure, a three-dimensional stacked type or L-wrench type, which can obtain a higher storage capacity than the conventional planar type, has been mainly used.

As a result, the unevenness of the memory cell surface becomes severe and, for example, in the exposure process of photolithography, the resolution of the pattern decreases due to the depth of focus.In the dry etching process, the residue generated on the sidewalls of the steps causes short circuits between patterns. In metal wiring,
Problems such as a decrease in the leakage properties at the stepped portion, which makes wire breakage more likely to occur due to stress migration or electromigration, have become apparent, and improvements in the flattening technology of the element surface are desired.

[Conventional technology]

Conventionally, the surface of an element has been flattened by using a silicate glass layer such as phosphosilicate glass (PSG) as an insulating film and reflowing the layer at a high temperature.

On the other hand, a conventional DRAM cell equipped with a stacked capacitor having, for example, a three-layer fin structure has a structure as shown in FIG.

That is, in FIG. 2, 51 is a semiconductor substrate, 52 is a field insulating film, 53 is a gate insulating film, 54 is a gate electrode,
55A, 55[1 is the source/drain region that becomes the storage node of the first and second cells, 56 is the gate covering insulating film,
57 is a lower insulating film, 58 is a silicon nitride (SjJn) film which is an etching-resistant film, and 59A and 59B are poly-Si.
60 is a dielectric film, 61 is a counter electrode made of poly-Si, etc., 62 is an interlayer insulating film made of PSG, LlsT.
r2 indicates a cell transistor, and SC, , sc2 indicates a storage capacitor (capacitance).

As shown in this figure, in conventional DRA and M cells, the length of the fins in each layer of storage electrodes 59A, 59B, etc. is equal, and therefore the surfaces of storage electrodes 59A, 59B, etc. are covered with a counter electrode 61. storage capacitor sc
, , SC2 had nearly vertical sides s1, s2.

(Problem to be Solved by the Invention) As a result, the degree of integration of cells increases, and as shown in the figure, the distances between storage electrodes 59A, 59B, etc. of adjacent cells (
When D) comes extremely close to about 1 μm or less,
The aspect ratio of the groove formed between the storage gap
The thickness of the grown film is significantly reduced, and due to the lack of step coverage, the film is formed over the groove.
P film (second interlayer insulating film) with a thickness of about 6000
62, even after the reflow process, a "socket" 63 as shown in the figure is formed. Therefore, when a metal film is deposited on the glabellar insulating film 62 made of PSG and selectively etched away to form a metal wiring pattern such as a pill line, the portion of the F 63 is Residues of the metal film that could not be removed by etching remain and adhere to the wiring that runs side by side (
This causes a problem of short-circuiting between the two (corresponding to the front-to-back direction of the page). In addition, there was a problem that the passivation function was impaired due to the formation of the above-mentioned "S" 63, and the reliability of the cell was impaired.

Therefore, the present invention provides a solution for the gap between the capacitors even when DRA and M cells having stacked capacitors having a multilayer fin structure are highly integrated and the capacitors of adjacent cells are arranged close to each other. Provided is a method for forming a multilayer fin structure stacked capacitor that is capable of flattening the surface of an insulating film formed over a cell without forming a "s" on top, and improves the passivation function of the insulating film. It is an object of the present invention to improve the yield and reliability of a DRAM including a stacked capacitor having a multilayer fin structure by preventing a decrease in performance and a short circuit between metal wirings formed on the insulating film.

[Means to solve the problem]

The above problem has a storage capacitor in which a storage electrode having multiple layers of fins connected to each other is covered with a counter electrode through a dielectric film, and the fins of the storage electrode are formed smaller as they go up the layer. or an etching-resistant film is formed on a semiconductor substrate, and a plurality of spacer films and a conductive film having etching selectivity with respect to the plurality of spacer films are formed on the etching-resistant film. , a step of alternately stacking the spacer film as the bottom layer and the top layer, penetrating the stacked film of the spacer film and the conductive film, the etching-resistant film and the insulating film below the etching film, and etching the surface of the semiconductor substrate. a step of forming an exposed contact hole, a step of covering the surface of the laminated film including the inner surface of the contact hole with an uppermost conductor film, and forming resists 1 to 3 on the uppermost conductor film. and forming first etching holes in the resist film for forming grooves that divide the laminated film including the uppermost conductive film, through the first etching holes, etc. By directional etching or anisotropic dry etching and isotropic etching, a first underlayer of a predetermined width is formed on the uppermost conductor film, reaching the uppermost spacer film immediately below it, and under the resist film. a first groove forming a first groove having a cut portion;
etching step, exposing the second conductor film from above directly below the uppermost layer spacer film by anisotropic dry etching through the first etching hole and the first groove; A second etching step for forming a second etching hole, isotropic etching, anisotropic dry etching, and isotropic etching through the first etching hole and the second etching hole. A second undercut portion is formed on the second conductor film, reaching the second spacer film from directly below the second conductor film, and having a second undercut portion with a predetermined width under the uppermost spacer film. a third etching step for forming a groove and simultaneously enlarging the first undercut portion; after removing the resist film, the spacer film is selectively etched away to form a groove formed of the plurality of conductor films; This problem is solved by a method of manufacturing a semiconductor device according to the present invention, which includes a step of forming a plurality of interconnected layers of fin structure electrodes.

[For production]

That is, in the present invention, when forming a storage electrode with a multilayered fin structure constituting a stacked capacitor, grooves are formed to divide the conductive film stacked in multiple layers via a spacer film into a plurality of cells. At this time, the amount of side etching of both conductive films is increased as one goes to the upper layer, so that the end face of the fin in the upper layer is set back, thereby forming the multilayer fin into an umbrella-like structure.

As a result, the side surface of the counter electrode that covers the surface of the storage electrode is formed at an acute angle with respect to the substrate surface, and an opening widens from the bottom in the gap between the side surface of the counter electrode of the adjacent capacitor.
A glyph groove is formed.

Therefore, the insulating film covering the capacitors is grown sufficiently thickly with good coverage in the grooves in the gaps between the capacitors, and even when the insulating film is reflowed to planarize the surface of the insulating film, the upper part of the grooves ``Z'' will no longer be formed on the insulating film.

Therefore, the passivation function of this insulating film does not deteriorate,
Further, short circuits between metal wirings formed on the insulating film are also prevented, improving the reliability of the DRAM having stacked capacitors having a multilayer fin structure.

〔Example〕

The present invention will be specifically described below by way of an embodiment of the manufacturing method with reference to process cross-sectional views shown in FIGS. 1(a) to (i).

FIG. 1(i) is a diagram showing an embodiment of a DRAM cell having a stacked capacitor using a three-layer fin structure storage electrode according to the present invention as a storage capacitor.

In the figure, 1 is a p-type Si substrate, 2 is a field oxide film, 3 is a p-type channel stopper, 4 is an element formation region, and 5 is a p-type Si substrate.
is a gate oxide film, 6 is a gate electrode, and 78 is a first n" type source train (S/D) vJ connected to a bit line.
area, 7B, 107B are the second n type S
/D region, 8 is gate covering silicon dioxide (SiOz)
9 is a lower insulating film, 29.129 is a three-layer storage electrode throughout the area, 30 is a Si3N4 dielectric film, 31 is a poly-Si counter electrode, 32 is a PSG interlayer insulating film, 33 is a bit line, and 34 is a V-shaped groove. , Tr is a cell transistor, sc, , sc2
indicates a storage capacitor, and as shown in this figure, the storage electrodes 29. of the storage capacitor 5C1SC2 according to the present invention.
129, the size of the fins decreases as you go up to the 111th floor. For this purpose, the side surface of the counter electrode 31 that covers the storage electrode surface via the dielectric film 30 is formed into a slope shape that recedes toward the top, so that the storage capacitors of adjacent cells are arranged close to each other. Even when this is done, the shape of the deep groove formed between the storage capacitors becomes a figure-7 groove 34 with a widened opening. Therefore, the coverage of the interlayer insulating film 32, which is grown in a vapor phase to cover the storage capacitor formation surface, with respect to the grooves 34 between the storage gabbers is improved, and a "z" is formed on the grooves 34. There is no.

The manufacturing method according to the present invention used in forming the structure described above will be described below with reference to Examples.

Refer to FIG. 1(a) When forming a DRAM cell equipped with a storage capacitor having storage electrodes having a three-layer fin structure, a well-known method is used to form a DRAM cell in which one surface of a p-type Si substrate is connected to a field oxide film 2 and its lower part. A gate I-oxide film 5, a gate electrode 6, and a first n-type S/D 9i connected to a bit line are formed on an element formation region 4 separated by a p-type channel stopper 3 by a well-known MOS process. A cell transistor Tr consisting of a region 7A, a second n+ type S/Dv4 region 7B (107B) which becomes a storage node, and a gate-coated silicon dioxide (SiO□〉 film 8) is formed, and a lower insulating layer of 5in2 is formed on the surface. On a conventionally processed substrate on which the film 9 has been formed, first a Si layer with a thickness of about 500 to 1000 layers and an etching resistance of l&!10 is formed using the CVD method. Thickness of about 2000 people 0l layer 5iOz spazer film 11, thickness of the bottom layer 0l layer 12 of about 2000 people thickness, thickness of the second layer from the bottom about 2000 people 0l layer 5i02 spazer film 1
3. A poly-Si film 14 having a thickness of about 2,000 layers, which is the second layer from the bottom, and an upper layer, that is, a 3N-th 5i02 smoother film I5, having a thickness of about 2,000 layers are sequentially formed. Note that 107B indicates the second S/D area of the adjacent cell. Furthermore, both the IN-th and second-layer poly-Si films have n'-type conductivity.

Referring to FIG. 1(b), the above-mentioned group IN I: is then covered with a first resist film 16, and an etching opening 17 of, for example, about 0.6 μm is formed in this resist film 16 by photolithography.
Reactive ion etching (R
IE) treatment, the SiO□ spacer film, Bo 1Js
A contact hole 18 is formed in the laminated film of the i film, Si, and 3N4 film to connect the second S/DiJf region 7B, which will become the storage node. In the above RIE process, a fluorine (F)-based etching gas is used for 5i02 and 5idIn H, and a chlorine (CI)-based etching gas is used for poly-Si.

Refer to FIG. 1(C) Next, after removing the first resist film 16, the third layer 5i02 spacer film 15-1 including the inner surface of the contact hole 18 is coated with C1 and a thickness of about 2000 ml by ID method.
6. A third uppermost poly-Si film I9 having n-type conductivity is formed.

Referring to FIG. 1(d), the third poly-Si counter electrode is then etched with a first etching opening for forming grooves to divide the laminated film of the 5iOz spacer film and the poly-Si film into a plurality of storage electrode shapes. A second resist film 20 having holes 21 is formed, and this resist 1
Using the lU 20 as a mask, the third layer poly-Si film 19 exposed in the etching opening 21 is removed by RIE processing using a CI gas, and then by a wet method using a fluoronitric acid solution or a dry method using an F gas. By directional etching, the end face of the third layer poly-Si film 19 is etched to form a first groove 23 having a first undercut portion 22 of about 2000λ in the lower part of the resist film 20. Note that the first groove 23 can also be formed only by the above-mentioned isotropic etching. However, when anisotropic etching and isotropic etching are used together as in this embodiment, the dimensional accuracy of the zide etching is improved. (corresponds to the first etching step in the claims) Figure 1 (e
) Reference Next, using the second resist film 20 as a mask, the first
A first etching hole is formed in the third layer SiO□ spacer film I5 exposed at the bottom of the first groove 23 by RIE treatment using F-based gas through the etching hole 21 and the first groove 23. A second etching aperture 24 is formed in alignment with the first and second etching apertures 21.
Similarly to the first etching step, CI
The second layer poly-Si film 14 exposed in the second etching hole 24 is removed by RIB processing using a base gas, and then isotropically etched using a wet method using a fluoronitric acid-based solution or a dry method using an F-based gas. Side etching is performed on the second layer poly-Si counter electrode surface, and the third layer poly-Si is etched.
A second groove 26 having about 20,000 second undercut portions 25 and communicating with the first groove 23 is formed in the lower part of the O□ spacer film 15, and at the same time, the third layer poly-Si
The first undercut portion 22 of the membrane 19 is enlarged to approximately 40,000 mm. Note that this second groove 26 can also be formed by only isotropic etching, similar to the first groove 23 described above. (corresponds to the second etching step in the claims) See FIG. 1(f) Next, the second resist film 20 and the third layer 5i0
Using the second scrubber film 15 as a mask, F is etched through the first and second etching holes 21 and 24 formed therein.
A third etching hole 27 aligned with the first etching hole 21 is formed in the second layer SiO□ spacer film 13 by performing RIE treatment using a system gas.
PI using CI gas through the etching hole 27 of
By F treatment, the first layer 5iO)4 spacer film 11 is exposed on the poly-Si film 12 of 1 layer 1'' in alignment with the third etching opening 27, and is connected to the second groove 27. A communicating third groove 28 is formed.

1 (see (2)) Next, after removing the second resist film 20, the 5i02 spacer film 1 is etched by wet etching using hydrofluoric acid.
1.13.15 removed, 1.2.3rd layer poly-Si film 1
2.14.19, it has an umbrella-shaped three-layer fin structure in which the 0 end part recedes by about 2000 as it goes to the upper layer due to the formation of the undercant part 22.25 by the side etching, and the second S/D area 7B of
A storage electrode 29 connected to is formed. (129 is a similar storage electrode of an adjacent cell) Refer to FIG. 1(b) Next, a 5iJ4 dielectric film 30 with a thickness of about 100 mm is formed on the surface of the storage electrode 29 (129) by the CVD method. ), then the same <
A poly-Si film 23 for the counter electrode with a thickness of about 2,000 mm is formed on this substrate by the CVD method.
form. Note that this poly-Si film 231 is formed by filling the trench portion in the contact hole 18 with a small diameter and the gap portion between the narrow fins between the layers. and,
The three-layer fin structure storage electrode 29 (129) covered by this poly-Si film 231 has an umbrella shape in which the ends of the -1- layer fins are sequentially retreated as described above. The surface is formed in the shape of a slope with a receding top.

Referring to FIG. 1(i), the poly-Si film 231 and the Si3N4 dielectric film 30 other than the gap capacitor region are selectively removed by normal photolithography to form a storage electrode 29 with an umbrella-shaped three-layer fin structure. (129) are covered with a poly-Si counter electrode 31 via a Si3N4 dielectric film 30, and the side surfaces have a slope shape with the upper part receding.Storage capacitors SC1 and SC2
etc. are completed. Next, a 0PSG interlayer insulating film 32 with a thickness of about 5,000 layers is formed on this substrate by the usual CVD method, and the first S/D? A contact hole is formed on the region 7A, and then the PSG interlayer insulating film 32 is subjected to a reflow treatment to planarize its surface. Then, a bit line 33 made of aluminum or the like is formed on the contact hole, and the above-mentioned process is performed. A DRAM cell including a storage capacitor having a three-layer fin structure storage electrode according to the present invention is completed. Note that, as mentioned above, the storage capacitor sc
Since the side surfaces of L, SC2, etc. are formed in a slope shape with the upper part receding, the adjacent storage capacitors SC1 and SC2
The groove formed between them is a V-shaped groove 34 whose top is open at a predetermined angle that is controlled by the amount of side etching of the fins of the storage electrode. Therefore, the above PSG
During the vapor phase growth of the interlayer insulating film 32, the step coverage in the groove is improved, and there is no possibility that "ZJ" will be formed in the PSG interlayer insulating film 32 above the groove.

〔Effect of the invention〕

As described above, according to the present invention, even when DRAM cells equipped with tall storage capacitors using storage electrodes having a multilayered fin structure are highly integrated and arranged in high density, adjacent This prevents the formation of "holes" in the insulating film on the deep grooves formed between the storage capacitors. Therefore, short circuits between wirings due to wiring material residue caused by "holes" in the insulating film, and insulation Since deterioration of the film's padgage-one effect is prevented, the yield and reliability of the DRAM can be improved.

[Brief explanation of drawings]

FIGS. 1(a) to 1(1) are sectional views of the manufacturing process of an embodiment according to the present invention, and FIG. 2 is a schematic side sectional view of a conventional structure. In the figure, 1 is a p-type Si substrate, 2 is a field oxide film, 3 is a p-type channel I collar, 4 is an element formation region, 5 is a first oxide film, 6 is a gate electrode, and 7A is a first 7B, 1.07B is the second 04 type S/D region, 8 is the gate coating 5iOz film, 9 is the lower layer insulating film, 10B is the 5i3Nn etching resistant film, 11.13.15 1.2.3rd layer 5i02 spacer film, 12.14.19 is 1.2.3rd layer polySil pattern, 1
6.20 is the first and second resist 1-film, 17 is an etching hole, 18 is a contact I hole, 21.24.27 is the first, second and third etching hole, 22 .25 is the first and second undercut part, 23.26
．． 28 are first, second, and third grooves, 29 is an umbrella-shaped three-layer storage electrode, 30 is a 5iJn dielectric film, 31 is a poly-Si counter electrode, 32 is a PSG interlayer insulating film, 33 is a bit line, 34 is a 7-shaped trench, Tr is a cell transistor, SC, SC2 is a storage capacitor. − Toa Bacteria − ≦Wealth's "Conventional model" side cross-sectional view of the rod fork

Claims (3)

[Claims] (1) A storage electrode having multiple layers of fins connected to each other has a storage capacitor covered with a counter electrode through a dielectric film, and the fins of the storage electrode are formed to become smaller as they go up the layer. A semiconductor device characterized by: (2) An etching-resistant film is formed on a semiconductor substrate, and a plurality of spacer films and a conductive film having etching selectivity with respect to the plurality of spacer films are formed on the etching-resistant film, with the spacer film being the bottom layer. forming a contact hole that penetrates the laminated film of the spacer film and the conductive film, the etching-resistant film, and the insulating film below to expose the semiconductor substrate surface; a step of covering the surface of the laminated film including the inner surface of the contact hole with an uppermost conductive film; forming a resist film on the uppermost conductive film; A step of forming a first etching hole for forming a groove to divide the laminated film including the conductor film, and performing isotropic etching, anisotropic dry etching, etc. through the first etching hole. A first groove is formed in the uppermost conductive film by directional etching, reaching the uppermost spacer film immediately below the uppermost conductive film, and having a first undercut portion of a predetermined width under the resist film. In the first etching step, the second conductor film from above is exposed on the uppermost layer spacer film by anisotropic dry etching through the first etching hole and the first groove. a second etching step for forming a second etching hole to expose the substrate; By chemical etching, the second conductive film is
A second groove is formed that reaches the second layer of spacer film from above immediately below it and has a second undercut portion of a predetermined width at the bottom of the uppermost layer of spacer film, and at the same time a third etching step for enlarging the undercut;
A semiconductor characterized by comprising a step of selectively etching and removing the spacer film after removing the resist film to form a multi-level interconnected fin structure electrode made of the plurality of conductor films. Method of manufacturing the device. (3) The conductor film has four or more layers including the uppermost conductor film, and the second and third etching steps are sequentially repeated multiple times to form a multilayer of four or more layers of the conductor film. Claim 2 characterized in that a hierarchical fin structure electrode is formed.
) A method for manufacturing a semiconductor device according to the method.