JPH0453256A - Semiconductor device - Google Patents

Abstract

PURPOSE:To enable a semiconductor device to operate even if the power supply of a second power supply terminal is shut off on standby or in sleep by a method wherein a diode is connected between a first and a second power supply terminal in an I/O cell around a chip so that the biasing in the direction from the first to the second terminal, may be the forward biasing. CONSTITUTION:A first power supply terminal vdd1 is supplied from a PAD2 and connected to a logic inside a chip, and a second power supply terminal vdd2 is also supplied from the PAD1. A ground terminal vss is connected to a PAD3 and connected to the logic inside the chip. At this point, diode means 8, 9, 10, and 11 are connected to an I/O cell section around the chip so as to make a direction of the first power supply terminal vdd1 to the second power supply terminal vdd2 serve as a forward direction. In result, even if the second power supply terminal vdd2 is cut off, as the second power supply terminal vdd2 is supplied from the first power supply terminal vdd1 through the intermediary of the diode means 8, 9, 10, and 11, a logic can be kept stable.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device incorporating two power supply systems.

[Prior Art] In the conventional input/output (Ilo) cell of a semiconductor device that has two built-in power supply systems, the second power supply terminal (vdd2) is the input of the first stage as shown in Fig. 3. connected to the circuit,
A first power supply terminal (vdd, 1) is connected to the second stage input circuit. At this time, the second power supply terminal (vdd2)
It is assumed that the voltage of the first power supply terminal (vddl, ) is higher than the voltage of the first power supply terminal (vddl, ).

In normal operation, power is supplied to both power terminals, and power is supplied to both terminals even in standby or sleeve states.

[Problems to be Solved by the Invention] However, a problem with the conventional circuit configuration is that when the second power terminal (vdd2) is turned off to save power, the first stage in FIG. Since power is no longer supplied to the input circuit of C, the signal of C becomes undefined, and the input circuit of the second stage also becomes undefined, and since a short current flows through this circuit, this semiconductor device stops operating.

In order to avoid this, a new power source must be supplied from another backup power source, which poses a major problem in terms of performance and price.

The present invention is intended to solve these problems, and its purpose is to connect the second power terminal (vd
d2) It is an object of the present invention to provide a low-power semiconductor arithmetic device that can operate even when the power is turned off.

[Means for Solving the Problem] In a semiconductor device incorporating two power supply systems, a voltage higher than that applied to (a) the first power supply terminal means and (b) the first power supply terminal means is provided. (c) the direction from the first power terminal means to the second power terminal means is forward biased, and the direction from the second power terminal means to the first power terminal means is forward biased; The semiconductor device is characterized in that at least one first diode means connected to a reverse bias and (d) first diode means are provided in an I/O cell portion in a peripheral portion of the semiconductor device.

[Function] The features of the first phase configuration of the present invention are shown in Figures 1 and 2 below.
The explanation will be given according to the figures and FIG.

In FIG. 1, a first power terminal (vddl) is connected between a first power terminal (vddl, ) and a second power terminal (vdd2).
1) to the second power supply terminal (vdd2) is connected to a first diode which is forward biased. This allows the fourth
In the figure, even if the second power supply terminal (vdd2) is turned off, power is supplied from the first power supply terminal (vdcll) to the second power supply terminal (vdd2) through the first diode, and the signal B becomes unstable. What will become will cease to be.

This allows the semiconductor device to operate even if the second power supply terminal (vdd2) is turned off during standby or sleeve mode. Also, when actually configuring this circuit as a semiconductor device, it becomes possible to insert a diode for each I/O, and the second power supply terminal (Vdd
2) Even if the output of the I/O cell connected to is turned on, current is supplied from each diode in the peripheral I/O cells, so the second power supply terminal (Vdd2) is turned off. However, it has the characteristic that there is no uncertainty at the input end and no uncertainty at the output side.

[Embodiment] FIG. 1 is a layout diagram of a semiconductor device according to an embodiment of the present invention. Further, FIG. 2 shows a combination of the diode means shown in FIG. 1 with a circuit. Further, FIG. 4 is a timing diagram for explaining in an easy-to-understand manner the operation according to the present invention when the second power supply terminal (vdd2) is cut off midway and becomes in an undefined state. The explanation will proceed according to FIGS. 1, 2, and 4.

In Figure 1, the second power supply terminal (vdd2) runs around the outermost periphery of the chip, the first power supply terminal (vddN) goes around the inside of it, and the ground terminal (VSS) goes around the inside of it. ing.

The first power terminal (vcldl,) is supplied from PAD (2) and is connected to the logic inside the chip, and the second power terminal (vdd2) is also supplied from PAD (], ). The ground terminal (VSS) is connected to PAD (3) and connected to the internal logic of the chip. I/O cells (22) are lined up around the periphery of the chip. At this time, the corner parts (4, 5, 6, 7) of the chip are the I/O cells (
22) cannot be placed, so in most cases it becomes wasted space, so usually the first power terminal (vddl) and the second power terminal (vdd2), which are power lines, are connected.
and the ground terminal (vss). In the present invention, by arranging a diode means in the cell part of this peripheral part, current is also supplied to the second power supply terminal (Vdd2) from the first power supply terminal (Vddl) from the diode in each I/O cell. It becomes possible to do so. Also, as shown in FIG. 1, diode means (8, 9, /O, ],
], ) are connected so that the direction from the first power terminal (vddl) to the second power terminal (vdd2) is the forward direction, so that if the second power terminal (vdd2) is turned off, an undefined state will occur. Even if the first power supply terminal (vdd
l) to 8.9. of the diode means. /O. Since the voltage of VDD 1 is supplied from the first power terminal (VDD 1.) to the second power terminal (VDD2) through 11, the logic section connected to the second power terminal (VDD2) is floated. Inconsistency in the logic section and short-circuit current caused by this will no longer flow to the next stage of logic.

FIG. 4 shows this state in a timing diagram.

When the second power supply terminal (vdd2) is cut off at point X in the figure, the diode means 8.9. /O. 11 of the logic part connected to the second power supply terminal (vdd2) so that the voltage of VDD1 is supplied from the first power supply terminal (vd, d, j) to the second power supply terminal (vdd2) through 11. The state remains fixed, does not become indeterminate, and remains a constant state. Fig. 2 is a diagram that is used to explain item 1 in an easy-to-understand manner.Here, the diode means is connected so that the direction of the second power supply terminal (vdd2) is in the forward direction from the first power supply terminal (vddl,). When the second power terminal (vdd2) is cut off, the connection is made such that when the second power terminal (vdd2) is cut off, the connection is made from the first power terminal (vddl) through the diode means (13) to the first power terminal (vddl,). The first power supply terminal (Vddl) is connected to the source terminal of the PCHMOS transistor of the inverter, which is a logic section connected to the second power supply terminal (vdd2), so that the voltage of Vddl is supplied to the second power supply terminal (vdd2). , ), since a voltage of vd d l is applied, the PCHMOS transistor does not float, and B, which is the output from the drain terminal, takes a definite value. In addition, since the input of the inverter, which is the next stage logic section, is also determined, no current flows in this section.

In this embodiment, diode means are included at each periphery of the chip. Furthermore, the order of the power lines vddl, vdd2, and VSS may be arbitrary. In addition, as a diode means,
It is clear that even if a transistor is used without being limited to just a diode, the current can flow from V d d 1 to V dd 2 and the same effect can be obtained.

[Effects of the Invention] As stated above, according to the configuration of item 1 of the present invention, the first power terminal (Vddl) and the second power terminal (vdd2
), a first diode which is forward biased in the direction from the first power terminal (Vddl) to the second power terminal (vdd2) is connected between
Even if the power supply is turned off, the power is supplied from the first power supply terminal (Vddl) through the first diode to the second power supply terminal (Vddl).
d2), and even if the second power supply terminal (vdd2) is turned off during standby or sleeve mode, this semiconductor device can operate, and when actually configuring this circuit as a semiconductor device, By using the I/O cell section on the periphery of the device, the second power supply terminal (Vdc)2
) Even if the output of the ■/O cell connected to
It has the characteristic that even if it is cut off, the input end and the output end are also undefined, and the effect is tremendous.

[Brief explanation of the drawing]

FIG. 1 is a layout diagram of a semiconductor device showing an embodiment of the present invention. FIG. 2 is a circuit diagram of an embodiment of the present invention. FIG. 3 shows an example of a conventional circuit diagram. FIG. 4 is a timing diagram showing the operation of FIG. FIG. 5 is a timing diagram 1 to 1 showing the operation of the third section.・PAD of the second power supply terminal (vdd2) ・PAD of the first power terminal (Vddl, ) ・PAD of the ground terminal (vss) ・Part of the corner of the semiconductor device ・Part of the corner of the semiconductor device 6 ・ 7 ・ 8・ /O ・ 12 ・ ] 4 ・ 15 ・ 18 ・ l 9 ・ 20 ・ 22 ・ Corner part of semiconductor device ・ Corner part of semiconductor device ・ Diode means Diode means ・ Diode means ・ Diode means ・ Logic section ・ Diode means・P-type MO5 transistor ・N-type MO8 transistor Japanese 1 animal dd2 νdd1 Plan 3 animals

Claims (1)

[Claims] In a semiconductor device incorporating two power supply systems, (a) a first power supply terminal means; (b) a first power supply terminal means to which a voltage higher than that of the first power supply terminal means is applied; (c) the direction from the first power terminal means to the second power terminal means is forward biased and the direction from the second power terminal means to the first power terminal means is reverse biased; (d) At least one first diode means is provided in a peripheral I/O cell portion of the semiconductor device.