JPH0452247U - - Google Patents
Info
- Publication number
- JPH0452247U JPH0452247U JP9541590U JP9541590U JPH0452247U JP H0452247 U JPH0452247 U JP H0452247U JP 9541590 U JP9541590 U JP 9541590U JP 9541590 U JP9541590 U JP 9541590U JP H0452247 U JPH0452247 U JP H0452247U
- Authority
- JP
- Japan
- Prior art keywords
- instruction
- central control
- data
- section
- control processing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Test And Diagnosis Of Digital Computers (AREA)
- Detection And Correction Of Errors (AREA)
Description
第１図は、この考案の一実施例による計算機を
示す構成図、第２図はこの考案のアドレス・デー
タ・ラツチ部の構成図、第３図は従来の計算機の
構成図である。
図において１は中央制御処理部、２はメモリ部
、３は入出力部、４はアドレス・データ・ラツチ
部、５はアドレス信号、６はデータ信号、７は制
御信号、８はレジスタ、９はカウンタ、１０は遅
延回路、１１はレジスタ、１２はメモリ、１３は
コマンド・リード信号、１４はデータ・リード信
号、１５はスタート・アドレス信号、１６はアド
レス・データ・リード信号である。なお、図中同
一符号は同一又は相当部分を示す。
FIG. 1 is a block diagram showing a computer according to an embodiment of this invention, FIG. 2 is a block diagram of an address/data latch section of this invention, and FIG. 3 is a block diagram of a conventional computer. In the figure, 1 is a central control processing unit, 2 is a memory unit, 3 is an input/output unit, 4 is an address/data latch unit, 5 is an address signal, 6 is a data signal, 7 is a control signal, 8 is a register, and 9 is a 10 is a delay circuit, 11 is a register, 12 is a memory, 13 is a command read signal, 14 is a data read signal, 15 is a start address signal, and 16 is an address/data read signal. Note that the same reference numerals in the figures indicate the same or equivalent parts.
Claims (1)
中央制御処理部と、上記中央制御処理部からのデ
ータ信号を制御信号に基づき入出力する能力を持
つ入出力部と、上記中央処理部で処理すべきデー
タが収納されているメモリ部と、上記中央制御処
理部が実行した命令の格納アドレスと命令データ
を記憶する機能を持つアドレス・データ・ラツチ
部とを備え、ある所定の命令を実行する際に、中
央制御処理部が実行した命令のメモリ部におおけ
る格納アドレスと命令データを確認することが出
来ることを特徴とする計算機。 A central control processing unit that has the ability to execute predetermined instructions and perform arithmetic processing; an input/output unit that has the ability to input and output data signals from the central control processing unit based on control signals; and processing by the central processing unit. A memory section that stores data to be executed, and an address/data latch section that has a function of storing the storage address and instruction data of the instruction executed by the central control processing section, and executes a certain predetermined instruction. A computer characterized in that it is possible to check the storage address and instruction data in a memory section of an instruction executed by a central control processing section.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9541590U JPH0452247U (en) | 1990-09-11 | 1990-09-11 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9541590U JPH0452247U (en) | 1990-09-11 | 1990-09-11 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0452247U true JPH0452247U (en) | 1992-05-01 |
Family
ID=31834118
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9541590U Pending JPH0452247U (en) | 1990-09-11 | 1990-09-11 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0452247U (en) |
-
1990
- 1990-09-11 JP JP9541590U patent/JPH0452247U/ja active Pending
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