JPH0451582A - Hybrid integrated circuit device - Google Patents
Hybrid integrated circuit deviceInfo
- Publication number
- JPH0451582A JPH0451582A JP2161601A JP16160190A JPH0451582A JP H0451582 A JPH0451582 A JP H0451582A JP 2161601 A JP2161601 A JP 2161601A JP 16160190 A JP16160190 A JP 16160190A JP H0451582 A JPH0451582 A JP H0451582A
- Authority
- JP
- Japan
- Prior art keywords
- component mounting
- electronic
- bonded
- parts
- opening
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims abstract description 15
- 239000000853 adhesive Substances 0.000 claims abstract description 11
- 230000001070 adhesive effect Effects 0.000 claims abstract description 11
- 239000011521 glass Substances 0.000 claims abstract description 5
- 239000004593 Epoxy Substances 0.000 claims abstract description 4
- 230000003014 reinforcing effect Effects 0.000 claims description 9
- 229910052751 metal Inorganic materials 0.000 claims description 3
- 239000002184 metal Substances 0.000 claims description 3
- 238000000034 method Methods 0.000 abstract description 8
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 abstract description 7
- 239000011347 resin Substances 0.000 abstract description 7
- 229920005989 resin Polymers 0.000 abstract description 7
- 229920001721 polyimide Polymers 0.000 abstract description 6
- 239000009719 polyimide resin Substances 0.000 abstract description 6
- 230000009477 glass transition Effects 0.000 abstract description 5
- 239000003990 capacitor Substances 0.000 abstract description 4
- 229910052737 gold Inorganic materials 0.000 abstract description 4
- 239000010931 gold Substances 0.000 abstract description 4
- 230000002787 reinforcement Effects 0.000 abstract description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 abstract description 3
- 239000011889 copper foil Substances 0.000 abstract description 3
- 238000010438 heat treatment Methods 0.000 abstract description 3
- 238000005516 engineering process Methods 0.000 description 5
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- 238000007747 plating Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 239000003822 epoxy resin Substances 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 238000005728 strengthening Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01028—Nickel [Ni]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19041—Component type being a capacitor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0393—Flexible materials
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
Landscapes
- Structure Of Printed Boards (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、混成集積回路装置に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a hybrid integrated circuit device.
従来、ガラス基材エポキシ樹脂をベースにしたプリント
配線板に半導体チップをグイボンディングし、ワイヤボ
ンディング法にて半導体チップの所定電極とプリント配
線板上の所定電極とを電気的に接続し、樹脂にて所定領
域を封止する技術（ＣＯＢ技術）または、ポリイミド樹
脂をベースにしたフレキシブルプリント配線板上に半導
体チップを前述と同じ方法で組立を行なう技術（ＣＯＦ
技術）が、電子機器の小型化、薄形化の目的で一般的に
使用されつつある。Conventionally, a semiconductor chip is bonded to a printed wiring board based on glass-based epoxy resin, and predetermined electrodes of the semiconductor chip and predetermined electrodes on the printed wiring board are electrically connected using the wire bonding method, and bonded to the resin. (COB technology) or technology (COF technology) to assemble semiconductor chips on a flexible printed wiring board based on polyimide resin using the same method as described above.
technology) is becoming commonly used to make electronic devices smaller and thinner.
第２図は従来の混成集積回路装置の一例を示す断面図で
ある。FIG. 2 is a sectional view showing an example of a conventional hybrid integrated circuit device.
第２図に示すように、厚さ２５μｍのポリイミド樹脂フ
ィルム１の上に設けた厚さ１８μｍの銅箔をバターニン
グし、選択的にニッケルめっき及び金めつきを施した配
線２を有するフレキシブル配線板の裏面に補強板１１を
接着剤４により接着してフレキシブル配線板の機械的強
度を補強する０次に、フレキシブル配線板の電子部品搭
載部に半導体チップ７をダイマウントし、ワイヤボンデ
ィング法により半導体チップ７の電極と配線２のパッド
とを金線８で電気的に接続し、樹脂体９により半導体チ
ップ７を含んで封止する。次に、チップコンデンサ１０
を配線２に半田付けして混成集積回路装置を構成する。As shown in FIG. 2, a flexible wiring having a wiring 2 formed by patterning a copper foil with a thickness of 18 μm provided on a polyimide resin film 1 with a thickness of 25 μm and selectively plating with nickel and gold. The mechanical strength of the flexible wiring board is reinforced by bonding the reinforcing plate 11 to the back surface of the board with adhesive 4. Next, the semiconductor chip 7 is die-mounted on the electronic component mounting area of the flexible wiring board, and then the semiconductor chip 7 is die-mounted using the wire bonding method. The electrodes of the semiconductor chip 7 and the pads of the wiring 2 are electrically connected with a gold wire 8, and the semiconductor chip 7 is sealed with a resin body 9. Next, chip capacitor 10
is soldered to wiring 2 to form a hybrid integrated circuit device.
この従来の混成集積回路装置は、フレキシブル配線板上
にマウントした半導体チップのワイヤボンディング工程
で、フレキシブル配線板を１００〜１５０℃に加熱する
ために接着剤のガラス転移点を超えてしまい接着剤の軟
化あるいは材料劣化を生じてパッド上にボンディングす
る圧力が不足してボンディング線とパッドの接合性が低
下し、ボンディングの信頼性が低下するという欠点があ
った。In this conventional hybrid integrated circuit device, during the wire bonding process of semiconductor chips mounted on a flexible wiring board, the flexible wiring board is heated to 100 to 150°C, which exceeds the glass transition point of the adhesive. There has been a drawback that softening or material deterioration occurs, resulting in insufficient bonding pressure on the pad, resulting in poor bonding between the bonding line and the pad, and lowering reliability of bonding.
また、接着剤のガラス転移点以下の温度でワイヤボンデ
ィングする場合にもボンディングの接合性の低下が生ず
るという問題点があった。Furthermore, when wire bonding is performed at a temperature below the glass transition point of the adhesive, there is also a problem in that the bonding properties of the bonding are reduced.
本発明の目的はワイヤボンディング工程の加熱温度を接
着剤のガラス転移点と無関係に設定できワイヤボンディ
ングの接合強度を向上させた混成集積回路装置を提供す
ることにある。An object of the present invention is to provide a hybrid integrated circuit device in which the heating temperature in the wire bonding process can be set independently of the glass transition point of the adhesive and the bonding strength of the wire bonding can be improved.
本発明の混成集積回路装置は、半導体チップを含む電子
部品を配線板上に搭載して設けた混成集積回路装置にお
いて、少くとも前記電子部品搭載部に対応する領域に開
孔部を設け且つ前記電子部品搭載部の周囲に接着剤によ
り取付けた補強板を有する。A hybrid integrated circuit device of the present invention is a hybrid integrated circuit device in which an electronic component including a semiconductor chip is mounted on a wiring board, and in which an opening is provided in at least a region corresponding to the electronic component mounting portion, and It has a reinforcing plate attached with adhesive around the electronic component mounting section.
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は本発明の一実施例を示す混成集積回路装置の断
面図である。FIG. 1 is a sectional view of a hybrid integrated circuit device showing one embodiment of the present invention.
第１図に示すように、厚さ２５μｍのポリイミド樹脂フ
ィルム１の上に厚さ１８μｍの銅箔を設けてバターニン
グしニッケルめっき層及び部分的に金めつき層を設けた
配線２を有するフレキシブル配線板と、フレキシブル配
線板の電子部品搭載部に対応する部分に開孔部５ａ、５
ｂを設けた厚さ０．５〜２ｍｍのガラスエポキシ板やエ
ポキシ系樹脂板等の補強板６を少くとも電子部品搭載部
の周囲に接着剤４により接着して固定する。As shown in FIG. 1, a flexible wire 2 is formed by providing a copper foil with a thickness of 18 μm on a polyimide resin film 1 with a thickness of 25 μm, buttering it, and providing a nickel plating layer and a partially gold plating layer. Openings 5a, 5 are formed in the wiring board and the portions of the flexible wiring board corresponding to the electronic component mounting parts.
A reinforcing plate 6, such as a glass epoxy plate or an epoxy resin plate, having a thickness of 0.5 to 2 mm and provided with a portion b is adhered and fixed at least around the electronic component mounting portion with an adhesive 4.
ここで、補強板６はガラスエポキシ板の代りにポリイミ
ド系樹脂板やアルミニウム等の金属板を使用しても良く
、金属板の場合にはグランド配線と接続してシールドの
機能を持たせたり放熱性を向上させる等の利点がある。Here, the reinforcing plate 6 may be a polyimide resin plate or a metal plate such as aluminum instead of the glass epoxy plate, and in the case of a metal plate, it can be connected to the ground wiring to provide a shielding function or to provide heat dissipation. It has advantages such as improving sex.
次に、開孔部５ａの電子部品搭載部に半導体チップ７を
ダイボンディングし、半導体チップ７の電極と配線２の
金めつき層を設けたパッドとの間を金線８によりワイヤ
ボンディングして接続し、樹脂体９により開孔部５内を
充填して被覆する。Next, the semiconductor chip 7 is die-bonded to the electronic component mounting part of the opening 5a, and wire-bonded using the gold wire 8 between the electrode of the semiconductor chip 7 and the pad provided with the gold plating layer of the wiring 2. Then, the resin body 9 fills and covers the inside of the opening 5.
家な、開孔部５ｂの電子部品搭載部の配線２にチップコ
ンデンサ１０を半田付けして搭載する。Finally, the chip capacitor 10 is soldered and mounted on the wiring 2 of the electronic component mounting portion of the opening 5b.
以上説明したように本発明は、フレキシブル配線板の電
子部品搭載部に対応する部分に開孔部を設けた補強板を
少くとも電子部品搭載部の周囲に接着して設けることに
より、電子部品のワイヤボンディング工程の加熱温度を
接着剤のガラス転移点に無間係にボンディングの最適条
件に設定でき、ワイヤボンディングの接合強度を強化し
て混成集積回路装置の信頼性を向上させるという効果を
有する。As explained above, the present invention provides a flexible wiring board with a reinforcing plate provided with an opening in a portion corresponding to the electronic component mounting portion by adhering it at least around the electronic component mounting portion. The heating temperature in the wire bonding process can be set to the optimum conditions for bonding without any delay to the glass transition point of the adhesive, which has the effect of strengthening the bonding strength of wire bonding and improving the reliability of the hybrid integrated circuit device.
また、補強板に設けた開孔部内に樹脂体を充填して封止
することにより、開孔部を樹脂の流れ止め、あるいはダ
ム枠を兼ねるという効果を有する。Furthermore, by filling and sealing the apertures provided in the reinforcing plate with a resin body, the apertures have the effect of stopping the resin from flowing or serving as a dam frame.
第１図は、本発明の一実施例を示す混成集積回路装置の
断面図、第２図は従来の混成集積回路装置の一例を示す
断面図である。
１・・・ポリイミド樹脂フィルム、２・・・配線、４・
・・接着剤、５ａ、５ｂ・・・開孔部、６・・・補強板
、７・・・半導体チップ、８・・・金線、９・・・樹脂
体、１０・・・チップコンデンサ、１１・・・補強板。FIG. 1 is a sectional view of a hybrid integrated circuit device showing an embodiment of the present invention, and FIG. 2 is a sectional view showing an example of a conventional hybrid integrated circuit device. 1... Polyimide resin film, 2... Wiring, 4...
... Adhesive, 5a, 5b... Opening portion, 6... Reinforcement plate, 7... Semiconductor chip, 8... Gold wire, 9... Resin body, 10... Chip capacitor, 11... Reinforcement plate.
Claims (1)
設けた混成集積回路装置において、少くとも前記電子部
品搭載部に対応する領域に開孔部を設け且つ前記電子部
品搭載部の周囲に接着剤により取付けた補強板を有する
ことを特徴とする混成集積回路装置。 ２、補強板としてガラスエポキシ板を用いた請求項１記
載の混成集積回路装置。 ３、補強板として金属板を用いた請求項１記載の混成集
積回路装置。[Scope of Claims] 1. In a hybrid integrated circuit device in which electronic components including semiconductor chips are mounted on a wiring board, an opening is provided at least in a region corresponding to the electronic component mounting portion and the electronic component is mounted on a wiring board. A hybrid integrated circuit device characterized by having a reinforcing plate attached with an adhesive around a component mounting part. 2. The hybrid integrated circuit device according to claim 1, wherein a glass epoxy plate is used as the reinforcing plate. 3. The hybrid integrated circuit device according to claim 1, wherein a metal plate is used as the reinforcing plate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2161601A JPH0451582A (en) | 1990-06-20 | 1990-06-20 | Hybrid integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2161601A JPH0451582A (en) | 1990-06-20 | 1990-06-20 | Hybrid integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0451582A true JPH0451582A (en) | 1992-02-20 |
Family
ID=15738258
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2161601A Pending JPH0451582A (en) | 1990-06-20 | 1990-06-20 | Hybrid integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0451582A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0594427A3 (en) * | 1992-10-21 | 1995-06-21 | Nippon Electric Co | A printed circuit board mounted with electric elements thereon. |
| EP0607929A3 (en) * | 1993-01-19 | 1996-03-13 | Canon Kk | Flexible printed circuit board and ink jet recording head using the same. |
| JPH09283889A (en) * | 1996-04-09 | 1997-10-31 | Rohm Co Ltd | Reinforcing method of flexible substrate and flexible substrate |
| JP2008085340A (en) * | 2006-09-27 | 2008-04-10 | Samsung Electronics Co Ltd | Circuit board for warpage prevention and manufacturing method thereof |
| JP2010103516A (en) * | 2008-09-29 | 2010-05-06 | Ngk Spark Plug Co Ltd | Wiring board with reinforcement |
| JP2012104557A (en) * | 2010-11-08 | 2012-05-31 | Ngk Spark Plug Co Ltd | Wiring board with electronic component and manufacturing method of the same |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6054364B2 (en) * | 1979-11-07 | 1985-11-29 | 三菱マテリアル株式会社 | Composite sintered piece for cutting blade |
-
1990
- 1990-06-20 JP JP2161601A patent/JPH0451582A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6054364B2 (en) * | 1979-11-07 | 1985-11-29 | 三菱マテリアル株式会社 | Composite sintered piece for cutting blade |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0594427A3 (en) * | 1992-10-21 | 1995-06-21 | Nippon Electric Co | A printed circuit board mounted with electric elements thereon. |
| EP0607929A3 (en) * | 1993-01-19 | 1996-03-13 | Canon Kk | Flexible printed circuit board and ink jet recording head using the same. |
| US6328427B1 (en) | 1993-01-19 | 2001-12-11 | Canon Kabushiki Kaisha | Method of producing a wiring substrate |
| JPH09283889A (en) * | 1996-04-09 | 1997-10-31 | Rohm Co Ltd | Reinforcing method of flexible substrate and flexible substrate |
| JP2008085340A (en) * | 2006-09-27 | 2008-04-10 | Samsung Electronics Co Ltd | Circuit board for warpage prevention and manufacturing method thereof |
| JP2010103516A (en) * | 2008-09-29 | 2010-05-06 | Ngk Spark Plug Co Ltd | Wiring board with reinforcement |
| JP2012104557A (en) * | 2010-11-08 | 2012-05-31 | Ngk Spark Plug Co Ltd | Wiring board with electronic component and manufacturing method of the same |
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