JPH0451342A - Disk cache system - Google Patents

Abstract

PURPOSE:To improve the hit rate of cache by providing an LRU chain storage area and a data access number of times memory circuit at a segment managing area which manages a correspondent segment, and deciding the segment to substitute storage data by referring to both the area and the circuit. CONSTITUTION:When a substitution candidate segment for the next request of a host system is decided after completing data transfer, a microprocessor 5 detects the segment(SG) 7n shown by the LRU chain storage area 20i of the segment managing area 8i. When the value of the segment access number of times storage area 21n of the segment managing area 9n which manages the SG 7n is less than 100, it is set as a substitution candidate, and the value of a substitution candidate segment number of times storage area 13 is updated to the segment number of the SG 7n. Also, when the value of the segment access number of times 21n exceeds 100, the segment SG 7m shown by the LRU chain storage area 20n is further detected.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention provides a method for replacing data stored in a cache with read data read from a disk device (or write data received from a host system) in a disk Φ processing system. Regarding.

[Conventional technology]

As described in Japanese Unexamined Patent Publication No. 65-4556, conventional devices use LRU processing to store stored data 'etc.
The segment to be replaced) has been determined.

When a segment in which stored data is to be replaced is determined by LRU processing, data that has not been accessed recently is replaced even if the number of accesses is large, which poses a problem in improving the hit rate.

[Problem to be solved by the invention]

The above conventional technology does not take into account the number of accesses to the data stored in the cache, and even if the number of accesses is large, data that has not been accessed recently is read data,
Alternatively, since the data is replaced with write data, there is a problem in improving the hit rate of the catch.

An object of the present invention is to improve the cache hit rate by considering the number of accesses to data stored in the cache.

[Failure to solve the problem]

In order to achieve the above object, the present invention provides a segment management area for managing a corresponding segment with an LRU chain storage area for storing a chain of LRHs and an access count storage circuit for storing the number of data accesses, and a microprocessor. The segment in which stored data is to be replaced is determined by referring to both the υLRU chain and the number of data accesses.

[Effect]

In the LRU chain storage area of the segment management area, the microprocessor detects replacement candidate segments by LRU processing. Further, the data access count storage area allows the microprocessor to detect the data access count 7# of the replacement candidate segment by LRU processing. By referring to the number of data accesses of the replacement candidate segment by LRU processing, it can be determined that there has been no recent access, but
Data that is frequently accessed is not replaced with read/write data, and the cache hit rate can be improved.

〔Example〕

Hereinafter, one embodiment of the present invention will be explained with reference to Figures 1 to 7. FIG. 6 is a flowchart of the disk cache system. The disk storage system includes a host interface control circuit 1, a cache memory 2, a memory control circuit 3, a disk device control circuit 4, a microprocessor +j5. and a disk unit f6.

The behavior f'Fi of the disk storage system in response to a data read request from the host system will be explained using FIG.

The host interface control circuit 1 controls the host interface and receives commands from the host system. The microprocessor 5 identifies the received command and detects a data read request. Furthermore, the microprocessor 5 determines whether data requested by the host system exists in the cache memory 2. If the data requested by the host system exists in the cache memory 2, that is, if the cache is hit, the memory control circuit 3 transfers the corresponding data in the cache memory 2 to the host system via the host interface control circuit 1. Further, if the data requested by the host system does not exist in the cache memory 2, that is, if the cache is not hit, the disk device control circuit 4 reads the corresponding data from the disk device f6 and sends the data via the host interface control circuit 1. In addition to transferring the applicable data to the host system,
The corresponding data is stored in the cache memory 2.

Further, the operation of the disk cache system in response to a data write request from the host system will be explained below.

The host interface control circuit 1 fully controls the host interface and receives commands from the host system. Microprocessor 5 identifies the received command and detects a data write request. Write data transferred from the host is sent to the host interface control circuit 1,
And, via the disk device control circuit 4, the disk device 6
and is stored in the cache memory 2.

Cache memory 2 includes one or more segments 7
Use by dividing into. The number of segments to be divided can be set by the host system using a host interface command. The microprocessor 5 manages the cache memory using the cache management area 8 existing in the built-in RAM. In addition, MicroProcera t5 has built-in RAM.
Each segment 7t- is managed by the segment management area 9 existing in the segment management area 9. In this embodiment, the cache memory 2 has a storage capacity of 64KB SRAMX! i-use. Furthermore, this is an example in which the host system sets the host interface command to use J:9, and the cache memory 2 is divided into eight segments 7 of equal capacity.

FIG. 6 shows the configuration of the cache memory management area 8. Cache memory management area 8 is segment number storage area 1
0, segment capacity storage area 11, segment status storage area 12, replacement candidate segment number storage area 16
=9 is configured. The segment number storage area 10 is an area in which the host system stores the number of segment divisions designated by a host interface command, and in this embodiment, it is (value of the segment number storage area 10) -8. The segment capacity storage area 11 has the storage capacity i of segment 7.
This is an area for all storage, and in this embodiment, (value of segment company storage area 11) = 8. The segment status storage area 12 is a flag indicating that each segment 7 stores all data. The replacement candidate segment number storage area 16 stores a segment 70 number used when replacing data stored in the carriage tool memory 2 with read data read from the disk device 6 (or write data received from the host system). It is an area.

Further, FIG. 4 is an explanatory diagram of the segment management area 9. The segment management area 9 includes a segment start address storage area 14, a staging address storage area 15, a staging address storage area 16, a staging storage area 17, a read pointer storage area 18, a write pointer storage area 19, and an LRU chain storage area. According to area 20 and segment access count storage area 21! llll configured. The segment start address storage area 14 indicates the start address (absolute address) of the corresponding segment) 7a. The staging address storage area 15 is the corresponding segment 7a.
This is an area that stores the start address (logical address of the host interface) of the data stored in the host interface. The staging address storage area 16 is an area for storing the start address (physical address of disk drive #6) of the data stored in the corresponding segment 7a. Staging capacity storage area 17Vi, the number of blocks of data stored in the corresponding segment (segment) 7a (number of logical blocks of the host interface) 't-This is an area for storing. The read pointer storage area 18 is an area for storing the IJ-to-pointer data of the corresponding segment 7a. The write pointer storage area 19 is an area that stores a write pointer for data of the corresponding segment 7a. The LRU chain storage area 20 is
This is an area for storing the next segment number of segment 7a in chaining using the R1J method. The segment access count storage area 21 is an area for storing the number of times data of the segment 7a has been accessed. Segment) 7a is the logical address #0OOOOOH of the host interface (cylinder number #0000 of the physical address of disk device 1)
H, head number #OOH, sector number #00H), if the middle logical probe is stored (value of staging address storage area 15) = $000
000H (value of staging address storage area 16) = #0O0
00000H (value of staging capacity storage area 17); 10.

Next, the microprocessor 5 executes the Cage Island management area 8.
The process of determining one segment 7 to be used in response to a data read/write request from the host system using the segment management area 9 will be explained with reference to FIGS. 1, 5, and 7.

FIG. 5 is a 70-chart of a process in which the microprocessor 5 determines one segment 7 to be used in response to a data read/write request from the host system. If the request from the host system is to read data, the microprocessor 5 determines whether the data requested by the host system exists in the carriage tool memory 2. That is, it is determined whether the cache is hinted. For this determination, the microprocessor 5 uses the staging address storage area and the staging capacity storage area 17 of the segment management area 91 corresponding to each segment 71. (
1 is one of awb), it is determined that the segment 71 in which the data requested by the host system exists will be used for the host system board request. If not, the microprocessor 5 stores the segment status storage area 12 of the cache management area 8 in the segment 7 where no data is stored.
V, that is, free segment 7v (V is either awb). If there is a free segment 7v,
In response to a read request from the host system, it is decided to use empty segment 7vt. vacant segment) 7
If v does not exist, the microprocessor 5 reads the cash management area 80 in response to a read request from the host system.
It is decided to use the segment 7j (j is either a or b) indicated by the fl conversion candidate segment number storage area 13.

If the cache is hit, the memory control circuit 3 transfers the corresponding data in the segment 71 to the host system via the host interface control circuit 1. If the cache is not hit, the disk device control circuit 4 reads the corresponding data from the disk device 6, transfers it to the host system via the host interface control circuit 1, and writes the segment 7v (
or 7j).

After the data transfer is completed, the microprocessor 5 updates the values in the cache management area 8 and segment management area 91.

FIG. 1 is a 70-chart of the process in which the microprocessor 5 updates the value of the cache management area 8 after the data transfer is completed. The microprocessor 5 stores the corresponding segment 71 (
Or change the status corresponding to 7v, 7j),
Applicable segment 71 (or 7v, 7j
) to indicate that the data is stored.

Next, the microprocessor 5 controls the segment management area 81.
(or the segment indicated by the LRU chain storage area 201 (or 20v, 20j)) 7n (n is one of a to h) is detected.

Segment management area 9n to manage this segment 7nf
The value of the segment access count storage area 21n is 100.
If less than
Update to segment number. In addition, if the value of segment access count 21n is 100 or more, LRUM
The entire segment) 7m (m is one of a to h) indicated by the chain storage area 20n is detected. Hereinafter, whether the candidate segment determines all the same judgments as those for segment 7nK,
Alternatively, it is performed until the end of the LRU chain.

If this judgment is made until the end of the LRU chain and no replacement candidate segment is determined, segment 7n'kfff is designated as a replacement candidate segment, and the value of replacement candidate segment number storage area 1 is updated to the segment number of segment 7n.

After updating the cache management area 8, the microprocessor +j5 updates the segment management area 90.

FIG. 7 is a 70-chart of the process in which the microprocessor 5 updates the segment management area 8. The microprocessor''!lth'5 updates the LRU chain storage area 20 and updates the segment 71 (or 7v).

7j)'t-Attach to the end of the LRU chain. Next, segment access count storage area 211 (or 21v, 21j) for segment 71 (or 7v, 7j)
Update the value of

In this embodiment, after data transfer is completed, a replacement candidate segment for the next request from the host system is determined and stored in the replacement candidate segment number storage area 13, so that replacement can be performed at high speed in response to a data request from the host system. Candidate segments can be determined.

[Effects of the Invention] According to the present invention, it is not necessary to completely replace data that has not been accessed recently but has been accessed frequently, which is effective in improving the cache hit ratio.

[Brief explanation of the drawing]

Fig. 1 is a management 70-chart for a disk and Yasshi system according to an embodiment of the present invention, Fig. 2 is an explanatory diagram of the cache memory, Fig. 6 is an explanatory diagram of the cache management area, and Fig. 4 is a segment management area. FIG. 5 is a flowchart of segment determination processing used for read/write requests, FIG. 6 is a flowchart of cache management area update processing, W, and FIG. 7 is 70- of segment management area update processing. Chill on the chart. Explanation of symbols 1... Host interface control circuit, 2... Cache memory, 5... Memory control circuit, 4...
... Disk device control circuit, 5... Microprocessor, 6... Disk device, 7... Segment, 8...
... Cache management area, 9... Segment management area, 15... Replacement candidate segment number storage area, 20.
...LRU chain storage area, 21...Segment access count 1 time Cache tape's resiliency. Day 5) Large determination diagram of P-butment for 1 length

Claims (1)

[Claims] 1. In a disk cache system including a cache memory consisting of one or more segments, a segment management area for managing the corresponding segment includes an LRU chain storage area and a data access count storage area. 1. A disk cache system, characterized in that a segment in which stored data is to be replaced is determined by referring to both an LRU chain and a segment access count. 2. In claim 1, when the number of data accesses of the segment selected to replace the stored data by the LRU process is equal to or greater than a predetermined number of times, the stored data is replaced in the segment at the end of the segment in the LRU chain. A disk cache system that is determined as a segment.