JPH0451084B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to the structure of an intermediate frequency amplifier of a receiver, and particularly to a receiving electric field detection method suitable for use in mobile radios, telemeters, and the like.

Prior Art Prior art to the present invention includes, for example, Microelectronics and Reliability;
No. 16, pp. 345-366, Bergamon Press
Published in 1977 (Microelectronics and Reliability,
vol.16, PP.345-366.Pergamon Press, 1977)
exists. The circuit configuration shown in FIG. 3, which is disclosed as a conventional example of the present invention, is shown in the above-mentioned document.
This is an extracted part of the IC called CA3089.
Other parts in the above document that are related to Figure 3 of this specification are Figure 1, Figure 2, Figure 10, Figure 11,
Fig. 12 and its explanatory text.

Conventionally, the configuration of an intermediate frequency amplifier having an electric field detection function is as shown in FIG. The output of each stage of the third stage consisting of transistors Q20' to Q27' is rectified via capacitors C8', C9', and C10', and the rectified current waveforms of each stage are added to output electric field level information. Ta.

Problems to be Solved by the Invention In the configuration of the conventional intermediate frequency amplifier described above, signal rectification is performed using diodes Q28', Q29', and Q3.
0';Q32',Q33',Q34';Q35', Q
36' and Q37', the disadvantage is that the temperature characteristics are particularly poor and the circuit becomes complicated to compensate for the temperature characteristics.

In addition, as the rectifier is a half-wave rectifier using diodes as mentioned above, capacitors C8', C9', and C10' are required for each. Therefore, lowering the intermediate frequency requires a correspondingly larger capacitor. It becomes necessary. Therefore, when integrated into an IC, the chip size becomes large in order to form the above-mentioned capacitor. Furthermore, in order to reduce the chip size by attaching an external capacitor, an external capacitor is required for each stage. This increased the number of terminals for external capacitors, which was disadvantageous for IC implementation. In addition, the rectifier uses a diode as described above, and therefore the transistor Q1'
It is possible to detect only the signal input until the first stage differential amplifier consisting of Q10' is saturated. Even if the total gain of the differential amplifier was increased by increasing the number of stages in order to widen the dynamic range, the maximum input level was determined by the saturation level described above, and a sufficient dynamic range could not be obtained.

On the other hand, in order to reduce the deviation from linearity with respect to the log characteristic of the input signal detection voltage,
Generally, it is necessary to lower the gain per stage of the above-mentioned differential amplifier and increase the number of stages, and to match the number of stages of the above-mentioned rectifier to the number of stages of the differential amplifier. Therefore, as mentioned above, as many capacitors as there are rectifier stages are required, and all of the above-mentioned disadvantages are magnified.

The present invention has been made in view of the above-mentioned conventional circumstances, and therefore, an object of the present invention is to improve the above-mentioned drawbacks, operate from a low intermediate frequency, have excellent temperature characteristics of input electric field detection voltage, and provide linearity. An object of the present invention is to provide a novel intermediate frequency amplification circuit having a wide dynamic range electric field detection function that can operate even at high input signal levels and has a small circuit scale.

Means for Solving the Problems In order to achieve the above object, an intermediate frequency amplifier circuit with a field strength detection function according to the present invention has n stages of differential amplifiers each having transistors whose emitters are connected in common. a first input that constitutes an intermediate frequency amplifier connected so that the output of each differential amplifier is sequentially input to the next stage, and whose first input is an input signal in each stage of the differential amplifier; There are n double-balanced differential amplifiers corresponding to the differential amplifiers, each consisting of a pair of double-balanced differential amplifiers and a second input pair whose second input is the output signal of each stage of the differential amplifier; n
In the intermediate frequency amplifier circuit which has the function of outputting a DC voltage with respect to the input AC signal level by a circuit that adds the positive-sequence output currents of each of the double-balanced differential amplifiers, The first input pair of the double-balanced differential amplifier includes a first differential transistor pair whose emitters are connected in common without an emitter resistor, and a second differential transistor pair whose emitters are commonly connected through an emitter resistor. A pair of active transistors are connected in parallel to each other.

Embodiments of the Invention Next, a preferred embodiment of the present invention will be specifically described with reference to the drawings.

FIG. 1 shows one embodiment of the present invention, and is a circuit configuration diagram for a four-stage configuration.

In FIG. 1, transistors Q1 to Q14 constitute a first-stage double-wave rectifier, and transistor Q
15 to Q26 constitute a second stage double wave rectifier,
Transistors Q27-Q38 constitute a third-stage double-wave rectifier, transistors Q39-Q50 constitute a fourth-stage double-wave rectifier, and transistor Q5
1, Q52 constitutes a current mirror circuit that adds the load currents of the double-wave rectifiers from the first stage to the fourth stage, and outputs the DC voltage smoothed by the resistor R23 and capacitor C1 as Vs. There is.

Now, the IF input signal V _IN is the transistor Q1, Q2
After being amplified by the first stage differential amplifier consisting of
The level is shifted by the transistors Q3 and Q4, and the amplification and level shifting are repeated in sequence, and the outputs of the transistors Q41 and Q42 are outputted as the IF output Vo.

On the other hand, as the IF input signal V _IN gradually increases,
The double-balanced differential amplifier saturates sequentially starting from the fourth stage.

First, the saturation level of the fourth stage double-balanced differential amplifier will be explained. Since the double balanced differential amplifier described above is a multiplier, the first input V ₄ is input to the pace pair of transistors Q47 and Q48, and the second input Vo is input to the base pair of transistors Q43 to Q46. It is saturated for both.

However, the input level of the fourth differential amplifier V ₄
Since the relationship between and the output level Vo is Vo≧V ₄ ,
The saturation of the fourth stage double-balanced differential amplifier is determined by the amplitude of the first input _V4 . The saturation amplitude level at this time is V ₄ ≧2V _T (1).

However, V _T = kT/q k: Boltzmann constant T: absolute temperature q: unit electronic charge Similarly, for the third stage double-balanced differential amplifier, V ₃ ≧2V _T ...(2) Second stage Similarly, for the double-balanced differential amplifier in the first stage, V ₂ ≧2V _T ...(3) For the double-balanced differential amplifier in the first stage,
It is as follows.

First, for a differential amplifier composed of constant current source _I2 , V _IN ≧2V _T ...(4) For a differential amplifier composed of constant current source _I3 , R6 = R7 = RE1, V _IN ≧2V _T +RE1I ₃ ...(5) Here, if 2V _T <RE1I ₃ is selected, the saturation of the first stage double-balanced differential amplifier is V _IN ≧2V _T +RE1I ₃ ...(6) This occurs for an input signal level of That is, the first
The saturation level of the second stage double-balanced differential amplifier is
Improved by 20log (1+RE1I ₃ /2V _T ) dB. In other words, the range of input signal levels that can be detected by the field strength of the IF amplifier is 20log lower than that of the conventional type.
(RE1I ₃ /2V _T ) improved by dB.

The solid line in FIG. 2 shows the characteristics of the output sink current Is in FIG. 1 with respect to the input signal level V _IN (dB value). The broken line is transistor Q1
1, Q12, resistors R6, R7, and constant current source _I3 are removed.

Effects of the Invention As described above in the embodiments, according to the present invention, a pair of transistors in which an emitter resistor is inserted in the pair of transistors serving as the first input of the first-stage double-balanced differential amplifier are connected in parallel. This makes it possible to detect even large signal inputs and provides electric field detection functionality over a wide dynamic range.

Also, as can be seen from Figure 1, the phase can be matched by using a double-balanced differential amplifier as a double-wave rectifier, and a capacitor for the rectifier is required for each stage in the case of the half-wave rectifier described above. can be omitted.

Therefore, according to the present invention, there is no need to integrate the rectifier capacitor on an IC chip, and there is an advantage that a field strength detection function that operates from a low frequency can be realized with a small chip area.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of an embodiment of the present invention constructed in four stages. Q1-Q52...transistor, R1-R23
...Resistor, C1 ... Capacitor, Vcc ... Power supply voltage, I ₁ , I ₂ , I ₃ ... Constant current source, Is ... Output section sink current, V _IN ... IF input signal, Vo ... IF output signal. Figure 2 shows the characteristics (solid line) of the output sink current Is versus the IF input voltage V _IN in the circuit configuration of Figure 1.
Output voltage Vs is determined by Vs=Vcc−R23・Is. The broken lines in Figure 2 represent the transistors Q11 and Q12, resistors R6 and R7, and constant current source in Figure 1.
The characteristics when Is is removed are shown. Figure 3 is 3
1 shows an example of a conventional circuit composed of a stage differential amplifier circuit. Q1' to Q50'...transistor, D1'...
Diode, R1' to R43'...Resistance, C1' to
C11'...Capacitor, S-METER OUT...
...Electric field detection level output terminal, Vcc...Power supply voltage.

Claims (1)

[Claims] 1. There are n stages of differential amplifiers each consisting of a pair of transistors whose emitters are commonly connected, and an intermediate frequency amplifier is configured in which the output of each differential amplifier is sequentially connected to the input of the next stage. A first input pair whose first input is the input signal at each stage of the amplifier, and a second input pair whose second input is the output signal at each stage of the differential amplifier. A double balanced differential amplifier corresponds to the differential amplifier.
In an intermediate frequency amplifier circuit having a function of outputting a DC voltage with respect to an input AC signal level by a circuit that adds the positive sequence output currents of each of the n double balanced differential amplifiers. ,
The first input pair of the first-stage double-balanced differential amplifier includes a first differential transistor pair whose emitters are connected in common without an emitter resistor, and a first differential transistor pair whose emitters are commonly connected through an emitter resistor. An intermediate frequency amplifier circuit with an electric field strength detection function, characterized in that a second differential transistor pair is connected in parallel with each other.