JPH0449250B2 - - Google Patents
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- Publication number
- JPH0449250B2 JPH0449250B2 JP58047958A JP4795883A JPH0449250B2 JP H0449250 B2 JPH0449250 B2 JP H0449250B2 JP 58047958 A JP58047958 A JP 58047958A JP 4795883 A JP4795883 A JP 4795883A JP H0449250 B2 JPH0449250 B2 JP H0449250B2
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- soi
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02664—Aftertreatments
- H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
- H01L21/02675—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using laser beams
- H01L21/02683—Continuous wave laser beam
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02664—Aftertreatments
- H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
- H01L21/02675—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using laser beams
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02373—Group 14 semiconducting materials
- H01L21/02381—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02439—Materials
- H01L21/02488—Insulating materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02587—Structure
- H01L21/0259—Microstructure
- H01L21/02598—Microstructure monocrystalline
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02664—Aftertreatments
- H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
- H01L21/02675—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using laser beams
- H01L21/02678—Beam shaping, e.g. using a mask
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02664—Aftertreatments
- H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
- H01L21/02689—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using particle beams
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02664—Aftertreatments
- H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
- H01L21/02691—Scanning of a beam
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Optics & Photonics (AREA)
- Materials Engineering (AREA)
- Recrystallisation Techniques (AREA)
Description
【発明の詳細な説明】
本発明は、非晶質絶縁物あるいは、絶縁膜上
に、単結晶半導体薄膜を形成する方法に関するも
のである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for forming a single crystal semiconductor thin film on an amorphous insulator or an insulating film.
３次元集積回路を形成する場合の重要なポイン
トの１つに、SOI（Semiconductor−On−
Insulator）構造がある。このSOIの形成方法とし
ては、第１図に示す様に、２つに大別出来る。第
１の方法において、試料の構造は、第１図ａに示
す様に、単結晶半導体１上に、絶縁膜２を付着さ
せ、その一部に開口を設けた後に、半導体膜３を
全面に付着させたものである。この場合、半導体
膜３の一部は、単結晶半導体１と直接接してお
り、この部分は、シード部４と呼ばれている。こ
の方法においては、単結晶半導体１の結晶性の情
報をシード部４を通して、半導体３に伝えること
が出来るため、結晶成長後の半導体３の結晶方位
は、単結晶半導体１と同一に出来る特長がある。
第２の方法における試料構造は、第１図ｂに示す
様に、単結晶半導体１上に全面に、絶縁膜２を付
着させ、さらに、その上に、半導体膜３を付着さ
せたものである。この方法においては、第１の方
法と異なり、シード部を設けなくてよい特長があ
る。 One of the important points when forming a 3D integrated circuit is SOI (Semiconductor-On-
Insulator) structure. As shown in FIG. 1, methods for forming this SOI can be roughly divided into two. In the first method, the structure of the sample is as shown in FIG. It is attached. In this case, a part of the semiconductor film 3 is in direct contact with the single crystal semiconductor 1, and this part is called a seed part 4. In this method, information on the crystallinity of the single crystal semiconductor 1 can be transmitted to the semiconductor 3 through the seed part 4, so that the crystal orientation of the semiconductor 3 after crystal growth can be the same as that of the single crystal semiconductor 1. be.
The sample structure in the second method is as shown in FIG. 1b, in which an insulating film 2 is deposited over the entire surface of a single crystal semiconductor 1, and a semiconductor film 3 is further deposited on top of that. . This method has the advantage that, unlike the first method, there is no need to provide a seed section.
しかし、いづれの方法においても、従来、グレ
インあるいは、サブグレインの粒界が存在してい
ない単結晶のSOIの大きさとしては、幅が数10μ
ｍであり長さが数mmといつた細長いものである。
３次元集積回路形成のためのSOIの大きさとして
は、少なくともチツプサイズ以上あれば望まし
い。さらに、また、３次元集積回路を考えた場
合、SOIの形成方法としては、シード部を設ける
制限がなくなり、自由度が増すため前述した、第
２の方法すなわち、シード部を用いない形成法が
有効と考えられる。 However, in either method, conventional single-crystal SOI without grain or subgrain boundaries has a width of several tens of μm.
It is a long and thin object with a length of several mm.
The size of the SOI for forming a three-dimensional integrated circuit is preferably at least the chip size. Furthermore, when considering a three-dimensional integrated circuit, the second method mentioned above, that is, the formation method that does not use a seed part, is preferable because there is no restriction on providing a seed part and the degree of freedom increases. It is considered effective.
従来、第１図ｂに示した構造のSOIの形成手段
としては、レーザあるいは、電子ビームを用いる
方法と、カーボンヒーターを用いる方法の２つに
大別できる。まず、レーザあるいは、電子ビーム
を用いる従来法について述べる。通常SOIの形成
のために用いられているレーザあるいは、電子ビ
ームは40〜100μｍ程度のビーム径を有しており、
近似的に、ガウス分布と見なせる。このようなビ
ームを第１図ｂに示した様な試料に照射を行な
い、表面の半導体膜３を溶融させ、一方向にビー
ムの走査を行なつても、半導体膜３をビーム径程
度に単結晶化することはできない。すなわち、第
２図ａに示す様に、ガウス分布をしたビームにお
いては、ビームの中心が最も高温になるため、半
導体３は溶融後、ビームの照射された周辺から冷
却が生じるため、結晶核が多数発生し、ビーム径
程度の大きさの結晶粒を成長させることは、でき
ない。この様子を、第２図ａの右側に示してあ
り、この図は、ビーム照射後の、試料の模式的平
面図であり、斜めの曲線は、結晶粒界を示す。こ
のように、通常のガウスビームでは、大きな結晶
粒を成長させることが出来ないため、その対策と
しては、ビームを整形する方法あるいは、レーザ
を用いる場合には、半導体膜３上にさらに、膜を
付着させ、レーザ光の透過率を変化させる方法な
どにより、第２図ｂの様な、温度分布を実現する
事により、大きな結晶粒の形成を行なつている。
すなわち、中心付近の温度が低いために、中心か
ら結晶成長が生じ、外側へ成長するために、第２
図ｂの右側に示した様に、大きな結晶粒を成長で
きる。しかし、この方法を用いても、幅の広い
SOIを形成するために、ビームを、重ね合せて、
SOIの形成を行なうと、結晶粒ごとに、結晶軸が
異なつたり、また、重ね合せ部分に、凹凸が生
じ、欠陥が多数発生するなどの問題が生じ、スポ
ツト状のビームを用いて、幅の広いSOIを形成す
ることは、従来、困難であつた。 Conventionally, methods for forming SOI having the structure shown in FIG. 1b can be roughly divided into two methods: methods using a laser or electron beam, and methods using a carbon heater. First, a conventional method using a laser or an electron beam will be described. The laser or electron beam normally used to form SOI has a beam diameter of about 40 to 100 μm.
Approximately, it can be regarded as a Gaussian distribution. When such a beam is irradiated onto a sample as shown in FIG. 1b, the semiconductor film 3 on the surface is melted, and even if the beam is scanned in one direction, the semiconductor film 3 can be irradiated to the same size as the beam diameter. It cannot be crystallized. In other words, as shown in FIG. 2a, in a beam with a Gaussian distribution, the center of the beam has the highest temperature, so after the semiconductor 3 is melted, cooling occurs from the periphery where the beam is irradiated, so that the crystal nuclei are A large number of crystal grains are generated, and it is impossible to grow crystal grains with a size comparable to the beam diameter. This situation is shown on the right side of FIG. 2a, which is a schematic plan view of the sample after beam irradiation, and the oblique curves indicate grain boundaries. As described above, since it is not possible to grow large crystal grains with a normal Gaussian beam, the countermeasures are to shape the beam or, if a laser is used, to add a layer on top of the semiconductor film 3. Large crystal grains are formed by creating a temperature distribution as shown in FIG. 2b by attaching the material and changing the transmittance of laser light.
In other words, since the temperature near the center is low, crystal growth occurs from the center and grows outward, causing the second crystal to grow.
As shown on the right side of Figure b, large crystal grains can be grown. However, even with this method, there is a wide range of
To form an SOI, the beams are superimposed,
When SOI is formed, problems arise such as the crystal axes of each crystal grain being different, and the overlapping portions becoming uneven and producing many defects. It has traditionally been difficult to form a wide SOI.
一方、幅の広いSOIを形成する手段として、幅
の広いカーボンヒーターを加熱源として用い、広
い範囲にわたり、表面の半導体を溶融し、大面積
のSOIを形成する方法も、従来、報告されてい
る。第２図ｃに、この方法の場合の温度分布、お
よび、SOI形成後の結晶粒の様子を示してある
が、この場合には、幅方向に、結晶核が多数発生
するために多くの、粒界（サブバウンダリーと呼
ばれている）が存在しており、この場合は、必ず
しも、単結晶とはいえず、このサブバウンダリー
を除去することが、この方法の重要な問題となつ
ている。 On the other hand, as a means of forming a wide SOI, a method has been previously reported in which a wide carbon heater is used as a heating source to melt semiconductors on the surface over a wide area and form a large-area SOI. . Figure 2c shows the temperature distribution in this method and the appearance of crystal grains after SOI formation.In this case, many crystal nuclei are generated in the width direction, so many Grain boundaries (called sub-boundaries) exist, and in this case it cannot necessarily be said that it is a single crystal, and the removal of these sub-boundaries is an important problem with this method. There is.
本発明の目的は、上述の如き、従来の欠点を大
幅に改善し、粒界がほとんど発生せず、しかも、
大面積の単結晶半導体薄膜を形成する方法を提供
することである。 The purpose of the present invention is to significantly improve the conventional drawbacks as described above, to generate almost no grain boundaries, and to
An object of the present invention is to provide a method for forming a large-area single-crystal semiconductor thin film.
本発明は、少なくとも表面に非晶質絶縁体層が
形成された基板の前記絶縁体層上に非晶質あるい
は多結晶半導体膜を形成し、次いでその上に絶縁
膜を、後に前記半導体膜を再結晶化させるときの
核となるべき微小領域と広い面積で再結晶化させ
る領域とをテーパ状に結合させたパターンを備え
しかも該パターンの内と外で光学距離が変わるよ
うに形成し、次いで電子ビームとレーザ光を同時
に前記微小領域から前記広い面積の領域へ向かつ
て前記パターン外の領域を含めて照射していくこ
とにより前記パターン内の半導体膜を再結晶化さ
せることを特徴とする単結晶半導体薄膜の製造方
法を提供する。 In the present invention, an amorphous or polycrystalline semiconductor film is formed on the insulating layer of a substrate having an amorphous insulating layer formed on at least the surface, and then an insulating film is formed thereon, and then the semiconductor film is formed on the insulating film. It is provided with a pattern in which a micro region to be a nucleus during recrystallization and a region to be recrystallized in a large area are combined in a tapered shape, and the optical distance is changed inside and outside the pattern, and then The semiconductor film within the pattern is recrystallized by simultaneously irradiating an electron beam and a laser beam from the small area to the wide area, including areas outside the pattern. A method for manufacturing a crystalline semiconductor thin film is provided.
本発明によれば、半導体薄膜を溶融するのに大
出力のとれる電子ビームを用い、また、結晶成長
時の周辺からの核発生を抑制するために、周辺の
温度を高くするような温度勾配を付けるため、電
子ビームと同程度あるいは、それ以上の領域を加
熱することが必要である。そのための加熱源とし
ては、レーザ光を用いており、電子ビームとレー
ザ光の出力をそれぞれ独立に制御できるため、結
晶成長の制御が容易である。 According to the present invention, a high-output electron beam is used to melt a semiconductor thin film, and a temperature gradient is created to increase the temperature of the surrounding area in order to suppress the generation of nuclei from the surrounding area during crystal growth. In order to attach the electron beam, it is necessary to heat the area to the same extent or more than the electron beam. Laser light is used as a heating source for this purpose, and since the outputs of the electron beam and laser light can be controlled independently, crystal growth can be easily controlled.
また、本発明によれば、平担な絶縁薄膜上の小
さな領域をまず単結晶とし、これをシードとし
て、大面積のSOIを形成しているために、グレイ
ンあるいは、サブグレインの発生のない大面積の
単結晶半導体薄膜を形成できる。 In addition, according to the present invention, a small area on a flat insulating thin film is first made into a single crystal, and this is used as a seed to form a large area SOI, so there is no generation of grains or subgrains. It is possible to form a single crystal semiconductor thin film with a large area.
以下、一実施例をもとに、より詳細な説明を行
なう。第３図には、本実施例に用いた試料の平面
図ａおよび、断面図ｂをそれぞれ示す。まず、平
面図ａにおいて、１３はSOIを形成する領域を示
し、１４は、SOI形成領域のマスクとなる領域を
示し、また、１０は、大面積のSOIを形成するた
めのいわゆるシードとなるべき領域であり、１１
は、SOIを大面積にするためのテーパー部分であ
り、１２は、実際にデバイスを形成するために使
用するSOI領域である。ｂは試料の断面図を示し
てあり、シリコン基板１５上に、酸化膜１６を形
成後、多結晶シリコン膜１７を付着させる。その
後、１３と１４の領域で異なつた厚みの酸化膜１
８を付着させ、さらに、１３の領域のみ、窒化膜
１９を付着させた。本実施例においては、多結晶
シリコン膜１７の膜厚は、0.5μｍ、酸化膜１８の
膜厚は、１４の領域で0.25μｍまた、１３の領域
で0.17μｍ、窒化膜１９の厚みは、0.12μｍとし
た。 A more detailed explanation will be given below based on one embodiment. FIG. 3 shows a plan view a and a cross-sectional view b of the sample used in this example. First, in the plan view a, 13 indicates a region where SOI is to be formed, 14 indicates a region that serves as a mask for the SOI formation region, and 10 indicates a so-called seed for forming a large-area SOI. area, 11
is a tapered portion for increasing the area of SOI, and 12 is an SOI region used to actually form a device. b shows a cross-sectional view of the sample. After forming an oxide film 16 on a silicon substrate 15, a polycrystalline silicon film 17 is attached. After that, oxide film 1 with different thickness in regions 13 and 14 is formed.
Further, a nitride film 19 was deposited only on the region 13. In this embodiment, the thickness of the polycrystalline silicon film 17 is 0.5 μm, the thickness of the oxide film 18 is 0.25 μm in the region 14, 0.17 μm in the region 13, and the thickness of the nitride film 19 is 0.12 μm. It was set as μm.
上記構造の試料に対して、多結晶シリコン膜１
７を溶融させ、単結晶化を行なうための加熱法と
しては、線状の、電子ビームとレーザ光を同時
に、同一領域に照射する方法を用いた。第３図ｂ
に示した断面構造の試料に対して、１３と１４の
領域全体に、電子ビームの照射と同時に、Arレ
ーザを照射する。この時、酸化膜１８と窒化膜１
９の膜厚を変える。即ち領域１３と１４で絶縁膜
の光学距離を変えることにより、多結晶シリコン
膜１７に達するArレーザのパワーを変化させる
ことが出来る。本実施例の場合、１３の領域で
は、入射パワーの約50％が、多結晶シリコン膜１
７に達し、１４の領域では、入射パワーの約95％
が多結晶シリコン膜１７に達した。従つて、１３
と１４の領域においては、Arレーザの照射によ
り多結晶シリコン膜１７の加熱状態は異なり、１
４の領域の方が高温になる。この時、多結晶シリ
コン膜１７は、溶融していない。次に、このAr
レーザの照射と同時に、１３と１４の領域全面
に、電子ビームの照射を行ない、多結晶シリコン
膜１７を１３と１４の領域において、溶融させ
る。この時の溶融された多結晶シリコン膜１７の
温度は、１４の領域の方が、１３の領域に比べ
Arレーザと電子ビームの全パワーが大きいため、
高くなり、Arレーザと電子ビームの照射を止め
た後の溶融した多結晶シリコン膜１７は、１３の
領域の中心から１４の領域に向うように冷却され
固化する。また、Arレーザと電子ビームの形状
は線状とし、最初は第３図ａに示した微小領域１
０に同時に照射してこの部分及び周辺の多結晶シ
リコン膜１７を溶融する。微小領域１０は幅20μ
ｍ長さ50μｍと小さくしてあるためこの領域は容
易に単結晶化する。次にこの領域１０を核として
照射部分を領域１１から領域１２へ移していく。 For the sample with the above structure, polycrystalline silicon film 1
As a heating method for melting 7 and performing single crystallization, a method was used in which a linear electron beam and a laser beam were simultaneously irradiated onto the same area. Figure 3b
For the sample having the cross-sectional structure shown in , the entire regions 13 and 14 are irradiated with an Ar laser at the same time as the electron beam is irradiated. At this time, the oxide film 18 and the nitride film 1
Change the film thickness in step 9. That is, by changing the optical distance of the insulating film in regions 13 and 14, the power of the Ar laser that reaches the polycrystalline silicon film 17 can be changed. In the case of this example, in the region 13, approximately 50% of the incident power is transmitted to the polycrystalline silicon film 1.
7 and in the region of 14, about 95% of the incident power
reached the polycrystalline silicon film 17. Therefore, 13
In the regions 1 and 14, the heating state of the polycrystalline silicon film 17 is different due to the Ar laser irradiation.
Area 4 has a higher temperature. At this time, polycrystalline silicon film 17 is not melted. Then this Ar
Simultaneously with the laser irradiation, the entire areas 13 and 14 are irradiated with an electron beam to melt the polycrystalline silicon film 17 in the areas 13 and 14. At this time, the temperature of the melted polycrystalline silicon film 17 is higher in the region 14 than in the region 13.
Because the total power of the Ar laser and electron beam is large,
The melted polycrystalline silicon film 17 is cooled and solidified from the center of the region 13 toward the region 14 after the irradiation of the Ar laser and electron beam is stopped. In addition, the shape of the Ar laser and electron beam is linear, and initially the micro area 1 shown in Figure 3a is used.
0 at the same time to melt this portion and the surrounding polycrystalline silicon film 17. Micro area 10 has a width of 20μ
Since the m length is as small as 50 μm, this region can easily become a single crystal. Next, using this region 10 as a core, the irradiated portion is transferred from region 11 to region 12.
領域１０と同様に多結晶シリコン膜１７は溶融
し、その後冷却するとき領域１０の結晶方位をう
けつぐため、領域１１から領域１２という広い面
積にわたつて単一の結晶方位を有するシリコン膜
を得られる。 Similar to region 10, polycrystalline silicon film 17 is melted and then inherits the crystal orientation of region 10 when it is cooled, so that a silicon film having a single crystal orientation can be obtained over a wide area from region 11 to region 12. .
本実施例に用いたArレーザは、出力13Wであ
りビームは、幅50μｍ、長さ1.4mmとなるように、
レンズ系を用いて、整形を行なつた。また、電子
ビームは、15K.V.の加速電圧を有し、パワー密
度は25KW／cm2、ビームの走査速度は、10cm／
sec、ビームサイズは、幅0.5mm、長さ２mmであつ
た。この時、第３図ａの各部分の寸法は、１０の
領域は、幅20μｍ長さ50μｍ、１１の領域の長さ
は、0.1mm、１２の領域は、一辺が、１mmの正方
形とした。この様な条件で試料を作製した結果、
グレインあるいは、サブグレインの粒界のない１
mm角の正方形を有するSOIが形成できた。この
時、SOIの表面は、酸化膜１８と、窒化膜１９で
被われているため、なめらかであり通常のMOS
デバイスを作製する上でその表面の凹凸は、特に
問題に、ならなかつた。 The Ar laser used in this example has an output of 13 W, and the beam has a width of 50 μm and a length of 1.4 mm.
Plastic surgery was performed using a lens system. The electron beam has an accelerating voltage of 15K.V., a power density of 25KW/cm 2 , and a beam scanning speed of 10cm/cm 2 .
sec, the beam size was 0.5 mm in width and 2 mm in length. At this time, the dimensions of each part in FIG. 3a are as follows: region 10 has a width of 20 μm and length of 50 μm, region 11 has a length of 0.1 mm, and region 12 is a square with a side of 1 mm. As a result of preparing samples under these conditions,
1 without grain or subgrain boundaries
SOI with a square mm square was formed. At this time, the surface of SOI is covered with oxide film 18 and nitride film 19, so it is smooth and normal MOS
The unevenness of the surface did not pose any particular problem in manufacturing the device.
上述した実施例においては、Arレーザーの多
結晶シリコン膜１７への透過量を制御するため
に、酸化膜と窒化膜を用いたが、これは、第４図
に示す様に、単に、酸化膜の厚みを変化させるだ
けでも、可能であつた。第４図において、１００
はシリコン基板、１０１は酸化膜、１０２は多結
晶シリコン膜、１０３は酸化膜である。この時、
酸化膜１０３の膜厚は、１３の領域で0.17μｍ、
１４の領域で0.25μｍとした。この時、Arレーザ
が酸化膜１０３を透過し、多結晶シリコン膜１０
２に達する割合は、照射パワーに対し、１３の領
域で70％、１４の領域で95％であつた。第３図ｂ
の構造に比べて、１３と１４の領域でのパワーの
透過量の差は小さいが、第４図の構造でも、粒界
の存在しない大面積のSOIを形成できた。 In the embodiment described above, an oxide film and a nitride film were used to control the amount of Ar laser transmitted through the polycrystalline silicon film 17, but as shown in FIG. It would have been possible to do so simply by changing the thickness of the material. In Figure 4, 100
101 is a silicon substrate, 101 is an oxide film, 102 is a polycrystalline silicon film, and 103 is an oxide film. At this time,
The thickness of the oxide film 103 is 0.17 μm in the region 13.
The thickness was set to 0.25 μm in 14 regions. At this time, the Ar laser passes through the oxide film 103 and the polycrystalline silicon film 10
The ratio of reaching 2 was 70% in the 13th region and 95% in the 14th region with respect to the irradiation power. Figure 3b
Although the difference in the amount of power transmission in regions 13 and 14 is smaller than that in the structure shown in FIG. 4, the structure shown in FIG.
なお、前記実施例では単結晶化させる膜として
多結晶シリコンを用いたが、非晶質シリコンでも
よい。 In the above embodiment, polycrystalline silicon was used as the film to be made into a single crystal, but amorphous silicon may also be used.
第１図は、SOIの代表的な形成法を説明するた
めの図で試料の断面構造を示す図である。１は単
結晶半導体、２は絶縁膜、３は半導体、４はシー
ド部をそれぞれ示す。第２図は、シード部を有さ
ないSOIの形成において、(a)通常のガウスビーム
を用いた場合、(b)温度分布を制御した場合、(c)ス
トリツプヒーターを用いた場合のそれぞれ代表的
な結果を示す図。左側の図は、ビーム強度又は、
温度の分布を示し右側の図は、結晶成長後の粒界
の分布を示してある。第３図は、シード部を有さ
ないSOIの形成における試料の(a)平面図及び(b)断
面図を示す。１０は、大面積のSOIを形成するた
めのシードとなるべき領域、１１はSOIを、大面
積にするためのテーパ部、１２は実際に使用する
SOIの領域、１３は、SOIを形成する領域、１４
はSOIを形成するマスクとなるべき領域をそれぞ
れ示す。さらに、１５はシリコン基板、１６は酸
化膜、１７は多結晶シリコン膜、１８は酸化膜、
１９は窒化膜をそれぞれ示す。
第４図は、試料の断面構造を示す図であり、１
００は、シリコン基板、１０１は酸化膜、１０２
は多結晶シリコン膜、１０３は酸化膜をそれぞれ
示す。
FIG. 1 is a diagram for explaining a typical SOI formation method and is a diagram showing a cross-sectional structure of a sample. 1 is a single crystal semiconductor, 2 is an insulating film, 3 is a semiconductor, and 4 is a seed portion. Figure 2 shows the results of forming SOI without a seed: (a) using a normal Gaussian beam, (b) controlling the temperature distribution, and (c) using a strip heater. Figures showing representative results. The figure on the left shows the beam intensity or
The figure on the right side showing the temperature distribution shows the distribution of grain boundaries after crystal growth. FIG. 3 shows (a) a plan view and (b) a cross-sectional view of a sample in the formation of SOI without a seed portion. 10 is a region to be a seed for forming a large-area SOI, 11 is a tapered portion for making the SOI large-area, and 12 is an area to be actually used.
SOI region, 13, SOI forming region, 14
indicate the regions that should serve as masks for forming SOI. Furthermore, 15 is a silicon substrate, 16 is an oxide film, 17 is a polycrystalline silicon film, 18 is an oxide film,
Reference numeral 19 indicates a nitride film. FIG. 4 is a diagram showing the cross-sectional structure of the sample, 1
00 is a silicon substrate, 101 is an oxide film, 102
103 indicates a polycrystalline silicon film, and 103 indicates an oxide film.
Claims (1)
た基板の前記絶縁体層上に非晶質あるいは多結晶
半導体膜を形成し、次いでその上に絶縁膜を、後
に前記半導体膜を再結晶化させるときの核となる
べき微小領域と広い面積で再結晶化させる領域と
をテーパ状に結合させたパターンを備えしかも該
パターンの内と外で光学距離が変わるように形成
し、次いで電子ビームとレーザ光を同時に前記微
小領域から前記広い面積の領域へ向かつて前記パ
ターン外の領域を含めて照射していくことにより
前記パターン内の半導体膜を再結晶化させること
を特徴とする単結晶半導体薄膜の製造方法。1 Forming an amorphous or polycrystalline semiconductor film on the insulator layer of a substrate having an amorphous insulator layer formed on at least the surface, then forming an insulating film thereon, and recrystallizing the semiconductor film later. A pattern is formed in which a micro region to be a nucleus for crystallization and a region to be recrystallized in a wide area are combined in a tapered shape, and the optical distance is changed inside and outside the pattern. A single-crystal semiconductor thin film characterized in that the semiconductor film within the pattern is recrystallized by simultaneously irradiating laser light from the micro region to the wide area, including areas outside the pattern. manufacturing method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58047958A JPS59175116A (en) | 1983-03-24 | 1983-03-24 | Manufacture of single crystal semiconductor thin film |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58047958A JPS59175116A (en) | 1983-03-24 | 1983-03-24 | Manufacture of single crystal semiconductor thin film |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59175116A JPS59175116A (en) | 1984-10-03 |
| JPH0449250B2 true JPH0449250B2 (en) | 1992-08-11 |
Family
ID=12789853
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58047958A Granted JPS59175116A (en) | 1983-03-24 | 1983-03-24 | Manufacture of single crystal semiconductor thin film |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59175116A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS634607A (en) * | 1986-06-25 | 1988-01-09 | Agency Of Ind Science & Technol | Manufacture of soi substrate |
| JPS6355925A (en) * | 1986-08-26 | 1988-03-10 | Seiko Instr & Electronics Ltd | Recrystallization of semiconductor thin film |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57113267A (en) * | 1980-11-19 | 1982-07-14 | Ibm | Method of producing semiconductor device |
| JPS57133626A (en) * | 1981-02-13 | 1982-08-18 | Toshiba Corp | Manufacture of semiconductor thin film |
-
1983
- 1983-03-24 JP JP58047958A patent/JPS59175116A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57113267A (en) * | 1980-11-19 | 1982-07-14 | Ibm | Method of producing semiconductor device |
| JPS57133626A (en) * | 1981-02-13 | 1982-08-18 | Toshiba Corp | Manufacture of semiconductor thin film |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS59175116A (en) | 1984-10-03 |
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