JPH0449080B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a timekeeping device that measures time. The purpose of the present invention is to freely input and output timekeeping information to the outside, and to enable a series of timekeeping functions such as clocks, stopwatches, timers, and alarms by combining it with a microcomputer (hereinafter referred to as a microcomputer) of an external device, and to enable a series of timekeeping functions such as clocks, stopwatches, timers, and alarms. By effectively utilizing the signals sent to the microcomputer and notification means, the burden on the microcomputer is lightened and the number of peripheral devices is reduced. Another object of the present invention is to input and output data to and from a microcomputer in addition to timekeeping information, thereby increasing multi-functionality. A further object of the present invention is to integrate a timekeeping device into a one-chip circuit using low power elements such as C-MOS, so that timekeeping can be continued for a long time even when the main power of the microcomputer is cut off. With the program store method, microcontrollers that enable specification changes and multi-function processing are rapidly expanding in popularity. However, performing the timekeeping function with a microcomputer requires a timer calculation method, and during this time, it is impossible to perform any calculations other than the timekeeping function, so it is an impossible method to make it multifunctional. As another calculation method, it is possible to interrupt and input a periodic and accurate clock to perform time measurement processing each time. However, with this method, the CRU is always occupied for timekeeping processing at a constant duty, and timekeeping interrupts occur during real-time processing, making real-time control operations inaccurate. An even bigger drawback is that a microcomputer that consumes a lot of power is likely to be turned on and off when the main switch is turned on and off, and also turned on and off when moving, and time information will evaporate during this time. Therefore, electronic circuits with timekeeping functions are desired to have low power and low voltage so that they can operate for long periods of time even with small-capacity batteries. Another requirement is to simplify the input and output of information to and from the microcontroller. It can be easily accessed in the same way as 1/O or memory through a system bus or the like. The present invention will be explained below with reference to the drawings. FIG. 1 is a block diagram of an embodiment of the invention. 1 is a 4.0MHz crystal oscillator, 2 is an oscillation circuit, 3
1 is a frequency dividing circuit, 4 to 7 are counters, 8 is a latch circuit for a write data bus, 9 is a latch circuit for a selected data bus, and 10 is a switching circuit for switching between address information and data information. 11 is a control circuit that controls the switching circuit 10 and latch circuits 8 and 9; 12 is a read data bus; 13 is a write data bus; 14 is a selection data bus; and 15 is address data for transmitting and receiving data with an external device (microcomputer). bus, 16
is a control circuit control signal sent from an external device to the control circuit 11, 17 is a buzzer drive control circuit,
18 is a buzzer driving circuit, and 19 is an interlab signal generating circuit. A counter is omitted between counters 5 and 6, and each counter has a BCD 4-bit configuration. The hour and month digits are in decimal numbers 1 to 12. Counters 4 to 6, buzzer drive control circuit 17
And the interlace signal generation circuit 19 uses the selection data bus 14 ( _SB0 to _SB3 ). Addresses are assigned to each and are shown in Table 1.

【table】

[Table] Counters 4 to 6, buzzer drive control circuit 17, and interlace signal generation circuit 19 have built-in decoders that decode data sent from the selection data bus, and two or more digits are selected at the same time. There's nothing to do. The address/data bus 15 is connected to the switching circuit 10 as a common input/output for digit addresses, time data, interlab data, and buzzer data.
and selectively leads to the read data bus 12, write data bus 13, and selection data bus 14.
By inputting and outputting address information and data information through a common bus, the number of pins is reduced, which is extremely advantageous in terms of cost. The latch circuit 8 holds the write data and outputs it to the write data bus 13. Latch circuit 9 holds address data and outputs it to selection data bus 14. As shown in FIG. 5, the control circuit 11 receives and outputs a chip select CS, a read signal RD, a write signal WR, and a switching control signal S/D between address information and data information. Switching control signal S/
The configuration is such that when D is high level, it is an address, and when D is low level, it is data selection. The output signals of the buzzer drive control circuit 17 and the interlude signal generation circuit 19 can be changed by external equipment, and these two circuits serve as signal synthesis means. The 2MHz signal output from the frequency dividing circuit 3 is used as a clock signal for external equipment. FIG. 2 shows the counter 5 of FIG. 1, and is a circuit diagram of 1/10 second digit. BCD decimal code
0000~1010 consists of D type FF24~27 and is a game
At gate 33, code 1010 is latched to master-only FF 32, and at gates 35 and 34, FFs 24 to 27 are reset to return to code 0000. At this time gate 3
Set priority set reset consisting of 6 to 39
Set FF and carry to the upper digit. When modifying a counter, select the address information as the digit to be modified. In this case, 1/10 second digit (code 0001)
is sent via the address/data bus. At the same time, the switching control signal S/D, chip select signal CS, and write signal WR are set to high level. Therefore, the latch signal LA becomes high level and the latch circuit 9 holds 0001. This operation opens the gate 42, turns on the output buffers 28-31, and sends the contents of the counter (time data) to the switching circuit 10 via the read data buses ( _RB0 - _RB3 ). Therefore, by next setting the read signal RD and the chip select signal CS to high level, time data can be read externally from the address/data bus 15. When modifying the counter, the address data bus 15 is
Send correction data (for example, 0010), set the switching control signal S/D to low level, and set the chip select signal to
When CS and write signal WR are set to high level, the signal
_W1 becomes high level and data is held in the latch circuit 8. Then gates 40 and 34 open and FF2
Reset 4 to 27. When the reset is completed, the signal _W2 goes high and the set signal (0010) from the write data bus is set to the FFs 24-27 by the gates 20-23. Therefore, the content of the 1/10 second digit is 2 (0010). As described above, the counter can be easily and quickly corrected and read from the outside. FIG. 3 is a circuit diagram of the interlace signal generating circuit 19 of FIG. 1. Interlove (below)
INT) digit address (1101) is sent from the address/data bus 15, and at the same time a control circuit control signal (S/D, CS, WR) is sent to the control circuit 11.
is sent and held in the latch circuit, thereby opening the gate 49. Next, the INT signal selection data is sent via the address/data bus 15, and at the same time the control circuit control signal (S/
D, CS, WR) are sent and the data is held in the latch circuit 8. The data held in latch circuit 8 is sent to latch circuit 43 via write data bus 13 (WB ₀ -WB ₃ ). Next, the signal _W2 is generated and the latch signal generated by the gate 48 causes the latch circuit 43 to hold the data on the write data bus 13. INT signal selection data is 500 when code is 0000.
Hz, 200Hz at 0010, 100Hz at 0100, 50 at 1000
There are four types of Hz. For example, when the INT signal selection data 0010 is sent, TG4 of transmission gates TG44 to TG47
5 is selected. Therefore, 200Hz is output as the INT signal. 200Hz signal is FF50, gate 51
It is differentiated by a differentiator circuit consisting of. It is desirable that the differential width be a relatively short pulse width such that the INT signal ends while the interlude is being executed. By changing the software of the external device, it is possible to select the interleaved signal required by the external device.
In the embodiment, since the data consists of 4 bits, a maximum of 16 types of INT signals can be selected. It is also possible to configure the differential width to be selected based on a similar idea. INT output from the interlove generator circuit
The signal can be used in various ways, such as as a reference signal for a timer in an external device, or as a key scan signal. FIG. 4 is a circuit diagram of the buzzer drive control circuit and buzzer drive circuit of FIG. 1. When address information 1111 (BUZ2) is sent from the address/data bus 15, the gate 52 opens in the same manner. Next, when data information is sent from the address/data bus 15, a latch signal generated from the gate 53 causes the latch circuit 54 to connect the write data bus 15.
(WB ₁ to WB ₃ ) data is retained. The output of latch circuit 54 is connected to TGs 55-57.
When 001X (second bit is high), TG57 is on; when 010X (third bit is high), TG56 is on.
is on, TG when 100X (4th bit is high)
55 is turned on. TG55-57
The drive frequency (tone) of the buzzer can be changed. A write data bus (WB ₀ ) is connected to the gate 58, and its output is connected to the FF 59. This is XXX1 (1st bit high)
Turn on the buzzer when . When XXX0 (1st bit is low), the buzzer is off. FF59
The Q output of TG55-57 is connected to gate 70.
control the output signal of As described above, when using the address information 1111, it is possible to select whether to turn the buzzer on or off and to select the buzzer drive frequency. Address information from address/data bus 15
When 1110 (BUZ1) is sent, gate 6 is sent in the same way.
0 opens. Next, when data information is sent from the address/data bus 15, the latch circuit 62 holds the data on the write data bus 13 (WB ₀ , WB ₃ ) in response to a latch signal generated from the gate 61 in the same manner. The output of the latch circuit 62 is TG63~6
6 is directly connected. . When the code is 0001 (1st bit high), TG63 is on, and when it is 0010, the TG63 is on.
TG64 on, when 0100, TG65 on, 1000
TG66 is turned on when .
Outputs of TG63-66 are sent to shift registers 67-6
The Q output of the shift register 69 is connected to the reset terminal of the FF 59. The shift registers 67 to 69 are timers that determine the driving time of the buzzer.As described above, when the address information 1110 (BUZ1) is used, the ON time of the buzzer can be selected. FIG. 5 shows a timing chart of control circuit control signals. Address/data bus A/D, chip select signal CS, switching control signal S/D, read signal RD, write signal WR,
Signal W ₁ , Signal W ₂ , Latch signal 2A. As described above, the present invention freely inputs and outputs time information to and from external devices, thereby enabling a timekeeping function. Furthermore, since the timekeeping device of the present invention is handled by an external device as, for example, an I/O port, the timekeeping means consisting of a counter or the like can be initialized by a command from the external device, eliminating the need for a correction switch as a timekeeping device and simplifying the configuration. It becomes very easy. Moreover, it has means for outputting a time signal obtained by timekeeping to an external device, which reduces the burden on the external device and allows the external device to change the output signal. It deepens the connection between external devices and timing devices, and is effective in multi-functioning with external devices. Further, the timekeeping device according to the present invention has an interrupt signal supplying means equipped with an interrupt signal selection section, and can supply a signal serving as a reference for time information from the device to an external device such as a microcomputer. It is also possible to change the timing of this reference signal using software of an external device. Therefore, by using the timekeeping device according to the present invention, it is possible to significantly reduce the burden on external equipment, and it can greatly contribute to increasing the functionality and improving the performance of external equipment.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention. FIG. 2 is a circuit diagram of the counter shown in FIG. 1. FIG. 3 is a diagram of the interlove signal generation circuit shown in FIG. 1. FIG. 4 is a diagram of the buzzer drive control circuit and buzzer drive circuit of FIG. 1. Figure 5 is a timing chart of the control circuit.

Claims (1)

[Claims] 1. A time reference signal generating means that divides the frequency of the reference signal from the oscillation means and outputs a time reference signal, at least one counter unit that measures time based on this time reference signal, and is capable of inputting and outputting time data of this counter unit. input/output data transmitting means; selection signal transmitting means capable of transmitting and receiving a signal for controlling input/output of the time data of the counter unit; and an interface capable of supplying an interrupt signal instructing a predetermined timing based on the time reference signal. It has an interrupt signal supply means, and the interrupt signal supply means includes:
A timekeeping device comprising an interrupt signal selection section that can control the timing from the outside.