JPH0448493A - Semiconductor integrated circuit device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device, for example, a multi-stage logic block and a clocked static RAM (
The present invention relates to a technique that is particularly effective when used in a memory with a logical function, etc. equipped with a random access memory (random access memory).

[Conventional technology.

Multi-a stage logic block and clocked static type RA
There is a memory with logical function having M.

In this memory with logic function, clocked state,
The digital RAM includes an input latch that captures and holds an input signal according to a predetermined clock signal. This suppresses the skinny of the input signal and speeds up the access time of the clock-to-state RAM.

For example, regarding a memory with 4 logical functions that includes a logic block and a clock-to-state RAM, there is
It is described in Publication No. 219300 and the like.

[Problem to be solved by the invention]

Prior to this invention, the inventors of the present invention developed a multi-layered garlic! We have developed a memory with logical functions as shown in Figure 4, which is equipped with a logical block and clocked static type RAM. That is,
In FIG. 4, the memory with logic functions includes three stages of logic blocks LBI-LB3 that are substantially serially arranged and their logic processors.

The latch groups LGI and LG2 are provided between the latch groups LGI and LG2, and further includes a random access memory section RAM and an input latch I.
It is equipped with a clocked static RAM (CSR) including L and output runner OL.

In this memory with logic function, seven groups LG1 and L
G2 outputs test data supplied via scan-in pad Sll or SI2 to timing signals φsl and φS.
It has a function to scan in according to 2 and scan out the retained data via scan out pad SQL or SO2. Furthermore, control signals such as a chip selection signal C5 and a write enable signal WE, and address signals AO
A plurality of test pads (not shown) are provided for inputting ~AJ, input data DIO~Dlk, etc. to the clocked static RAM in parallel. As a result, the diagnosability of the memory with logical functions is improved, the testing cost thereof is reduced, and the failure detection rate of the memory with logical functions is increased, so that its reliability is improved.

In addition, in the above memory with logic function, the input signal IL for taking in and holding an input signal is provided in the curve of the random access memory section, so that the actual access time as a clocked static type RAM is shortened.

In addition, by inputting test data in parallel via multiple test pads, clocked static RAM
The circuit configuration of the input section is simplified, and the transmission delay time of the input signal is reduced.

However, the inventors of the present application have discovered that the above-mentioned memory with logical functions still has the following problems. That is, in the memory with logic function shown in FIG. 84, the input latch I of the clock static type RAM
There is no means for monitoring the input data held in L by an external test device, etc. Therefore, it is not possible to accurately identify a fault that has occurred in the final stage logic block LB3. The failure detection rate of the memory with logical functions decreases, and its reliability decreases.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor integrated circuit device, such as a memory with a logic function, which improves failure detection rate while suppressing an increase in the number of circuit elements and the transmission delay time of an input signal.

The above and other objects and novel features of this invention include:
It will become clear from the description in this document and the attached drawings.

[Means for solving problems.

A brief overview of typical inventions disclosed in this application is as follows.

That is, in a predetermined test mode, a slave latch in the form of a shift register is added together with each bit of an input latch to a memory with a logic function that includes multiple stages of logic blocks and a clocked state RAM, and While in test mode, add a path that directly couples the output terminal of the input latch to the input terminal of the corresponding output latch.

[For production]

According to the above means, since the input signal held in the input latch can be monitored by an external test device, it is possible to accurately identify a failure in the logic block provided at the front stage of the clocked static RAM. As a result, while suppressing the increase in the number of circuit elements and input signal transmission delay time, it is possible to improve the diagnosability of memory with logic functions and reduce its test cost. You can increase your sexuality.

[Embodiment 2] FIG. 1 shows a block diagram of an embodiment of a memory with logic functions to which the present invention is applied.

Further, FIG. 2 shows a circuit diagram of an embodiment of the input latch IL and the output latch OL included in the clocked static RAM (csR)t,=the memory with logic function in FIG. The figure shows a timing diagram of one embodiment. Based on these figures, an overview of the configuration and operation of the memory with logic functions of this embodiment and its characteristics will be explained.

Note that each circuit element in FIG. 2 and the circuit elements constituting each block in the gi4i diagram are formed on one semiconductor substrate such as single-crystal silicon, although this is not particularly limited. The MOSFET (gold/N oxide semiconductor field effect transistor; hereinafter, in this specification, MOSFET will be referred to as a general term for insulated gate field effect transistor) shown in the figure below is either not particularly limited or all h It is a Nayannel MO5FET.

In FIG. 1, the memory with logic functions of this embodiment includes, although not particularly limited to, three stages of logic blocks LBI to LB3 that are substantially in series, and a clocked static block provided at a stage subsequent to these logic blocks. Type RAM (
C3R), and further includes logic blocks LBI and LB
Two groups LGI and LG2 are provided between Z and between logic blocks LB2 and LBa.

Among these, the first stage logic block LBI is supplied with a predetermined input signal via input terminals ISL to ISi, although not particularly limited, and its output signal is supplied to the latch group LGl.
The signal is transmitted to the next stage logic processor 7 or LB2 via. A timing signal φcl is supplied to the latch group LGI from a control section (not shown) of the memory with logic function.

The logic block LBI performs predetermined logical operation processing based on the human input signals supplied through the input terminals IS1 to lsi, and outputs the result to the latch group LG1. Also,
The latch group LGI takes in and holds the output signal of the logic block LB1 in accordance with the timing signal φC1, and transmits it to the next stage logic processor 7 and LB2.

In this embodiment, the latch group LGI includes, although not particularly limited to, a plurality of latch circuits provided corresponding to each hint of the output signal of the logic block LBI. When placed in test mode, it is selectively placed in soft register form. At this time, the latch group LGI receives the test clock signal φsl.
and φS2, it has a function of scanning in the test data supplied via the scan invant Sll, and scanning out the retained data from the SQL. As a result, logical block L
The output signal of SI can be monitored from an external test device, and arbitrary test data can be supplied to logic block LB2. As a result, logical block LBI
and the normality of LB2 can be efficiently confirmed.

Next, the output signal of the logic block LBI is supplied to the 52-stage logic block LB2 via the latch group LGI, as described above, and the output signal is sent to the next-stage logic block via the latch group LGZ. It is transmitted to LB3. The latch group LG2 includes a control A (not shown) of the memory with logic function.
Timing signal φC2 is supplied from tjE.

Although not particularly limited, the logic block LB2 performs a predetermined logical operation process based on the output signal of the logic block LBI, and outputs the result to the latch group LG2. Also,
In accordance with the timing signal φC2, the group LG2 takes in and holds the output signal from the logic block 7 to LB2, and transmits it to the next stage logic block 07 to LB3.

In this embodiment, the latch group LG2, like the latch group LGL described above, includes a plurality of latch circuits provided corresponding to each gate of the output signal of the logic block LB2.

These latch circuits are selectively used as shift registers when the memory with logic function is placed in a predetermined test mode. At this time, the latch group LG2 receives the clock signal φs.
1 and φS2, it has a function of scanning in the test data supplied via the scan-in pad S12 and scanning out the retained data from the scan-out puff F'SO2. This allows the output signal of the logic block LB2 to be monitored from an external test device, and also allows the logic processor 7 to supply urgent test data to LB3. As a result, the correctness of the logic blocks LB2 and LB3 can be efficiently confirmed.

Similarly, @3 stage logic pro 7 LB3 has latch group L.
The output signal of the logic block LB2 is supplied via G2, and the output signal is directly connected to the clocked static type RA.
Supplied to M.

Logic block LB3 performs predetermined logical operation processing based on the output signal of logic processor 7 or LB2, and outputs the result to chip selection signal C5 and another input signal, although not particularly limited. As full signal WE, address signals AO to AJ and input data DIO-Dlk,
Supplied to clocked static type RAM.

In this embodiment, between the logic block LB3 and the clocked static RAM, although not particularly limited, each of the output signals of the logic processor 7 and LB3, ie, the block selection signal C5 and the write enable signal WE. , address signal AO-Aj and input data DIO-Dl
A plurality of test pads are provided corresponding to k. These test pads are supplied with predetermined test data in parallel when the memory with logic function is in a test mode. This makes it possible to efficiently input test data for the black state ink type RAM and efficiently perform its functional test.

On the other hand, the clocked static type RAM has a basic configuration of a random access memory section RAM consisting of a CMO5 (complementary type MO5), although it is not particularly limited, and further includes an input carafner IL and an output latch OL. The random access memory unit RAM receives an input signal, that is, a chip selection signal CS, from the logic block LB3 via the input latch IL.

Life full signal WE, address signal AO~A
J and input data DIO~Dlk are supplied, and the output signal is sent from the output latch OL to the output terminals OSO~O3.
k. Enter empty.

Timing signals φc3 and φc are applied to the output latch OL and the output latch OL from a control section (not shown) of the memory with logic function.
4 are supplied respectively.

The input latch IL is not particularly limited, but as shown in FIG.
These master latches, including a plurality of master latches ML provided corresponding to E and address signals AO to AJ, are connected by a pair of CMOS inverter circuits whose input terminals and output terminals are cross-coupled to each other, although not particularly limited thereto. configured. Between the logic block LB3 and the input node of each master latch ML of the input Karafuner IL, there are provided Henna channel MOSFETs Q1 whose gates receive the timing signal φ03. As a result, the output signal of the logic block LB3 is taken into the corresponding master latch ML of the input latch IL by setting the timing signal φc3 to high level, and is further transmitted to the random access memory unit RAM.

In this embodiment, the input carafner IL further includes a plurality of slave latches SL provided corresponding to the input signals, that is, the chip selection signal CS, the write enable signal WE, and the address signals AO-AJ. The input nodes of these slave latches SL are h-channel MO5Fs that receive a test timing signal φs1 at their gates.
Through ETQ2, the corresponding previous stage master latch ML
The output node is connected to the subsequent master latch M via an N-channel MO3FET Q3 which receives a test timing signal φ32 at its gate.
It is coupled to the input node of L. The input node of the master latch %AL corresponding to the chip selection signal C5 is coupled to the scan-in pad SI3 via the N-channel MO3FET Q3, and the output note of the slave latch SL corresponding to the address signal Aj is directly scanned. Coupled to outpad SO3.

As a result, the master latch ML and slave latch SL constituting the input latch xL-1r can be selectively configured into shift registers on the condition that the memory with logic function is in a predetermined test mode and the timing signals φS1 and φS2 are supplied. The test data supplied via the scan-in pad SI3 is scanned in. Further, as illustrated in FIG. 3, for example, a number selection signal C5 and a write enable signal W are supplied from the corresponding test pad.
After taking in E and address signals AO to Aj by the timing signal φC3, the timing signal φS
It is also possible to scan out from the scanout pad SO3 according to 1 and φS2. As a result, arbitrary test data can be supplied to the random access memory and dRAM, and the chip selection signal C5, write enable signal WE, and address signals AO to AJ held by the input latch IL can be monitored from an external test device. I can do it.

The clocked static RAM input runner IL of this embodiment further includes a k+L input data runner DI provided corresponding to the input data DIO to Dlk.
The inputs of these input cheater rafts, including L, are coupled to the corresponding theta input terminals DIO-Dik via the MO3FETQI, and their output nodes are coupled to the corresponding input terminals of the random access memory section RAM. be done.

As a result, input data 010 to Dlk supplied via the logic block LB3 when the memory with logic function is in the normal operation mode is taken into the corresponding input data latch DIL of the input latch IL in accordance with the timing signal φC3. The data is transmitted to the random access memory unit RAM.

On the other hand, output runner OL of clocked static type RAM
is not particularly limited, but as illustrated in Figure 2,
11 provided corresponding to output data O8O to ○Sk
The input nodes of these output data latches, including the output data runners DOL, are coupled to the corresponding output terminals of the random access memory section RAM via the common channel MO3FETQ4 which receives the timing signal φC4 at its gate, and the output nodes thereof are coupled to corresponding data output terminals O8O to O3k. As a result, when the memory with logic function is placed in the normal operation mode, the output signal of the random access memory section RAM is taken into the corresponding output data latch DOL of the output latch OL according to the timing signal φC4, and the corresponding data It is sent out via output terminals O5O to O5k.

In this embodiment, although the input node of each output data latch DOL of the output latch OL is not particularly limited, the corresponding input data latch DIL of the input latch IL is connected via an N-channel MO5FETQ5 that receives a timing signal φsl at its gate. is connected to the output node of As a result, when the memory with logic function is put into a predetermined test mode, the input data of the input latuna IL
The input data held at L is transmitted to the corresponding output data latch DOL of the output latch OL, and further sent to the test equipment via the output terminals OSO to O3k.

In other words, the test device connected to the memory with logic function of this embodiment can set the memory with logic function to a predetermined test mode to test pads C3WE, AO~A'', DO~Dk, or scan-in pad SI3. Any test data is supplied to the random access memory section RAM of the clocked static type RAM through the output latch OL and the output terminals O5O to O3k.
It is possible to monitor the input signal held by the input latch IL via the scan out pad S03 or the output terminals OSO to O5k. Therefore, without adding many circuit elements or adding new circuit elements to the normal signal transmission path,
In addition to efficiently checking the normality of the random access memory RAM, you can
It is possible to accurately identify a fault occurring in the preceding stage circuit of M, that is, the logic processor, LI33. As a result, it is possible to suppress the increase in the number of circuit elements and the transmission delay time of input 1, improve the diagnosability of memory with logic functions, reduce its test cost, and improve the failure detection rate of logic @ functional memory. and its reliability.

As shown in the above examples, by applying this invention to a semiconductor integrated circuit device such as a memory with a logic function equipped with a multi-stage logic processor and a single static RAM, the following can be achieved. You can obtain effective effects. In other words, a logic block with multiple stages of mountains and a clocked static type R
A slave roughener is added to a memory with a logic function equipped with AM in the form of a 7-foot register along with each bit of the input latch in a predetermined test mode, and the output terminal of the input latch is set to 8 in the specified test mode. By adding a path that connects the signal directly to the input terminal of the corresponding output carafna, it is possible to avoid adding many circuit elements and without adding new circuit elements to the normal signal transmission path. This has the advantage that the input signal to be measured can be monitored by an external test device.

(2) Due to the above-mentioned mountaintop, it is shaped like a clock,...
The logic processor provided before the AM has the effect of being able to accurately identify damage.

<3) With the above-mentioned peak and item (2), it is possible to suppress the increase in the number of circuit elements and the transmission delay time of human input signals, improve the diagnosability of the memory with logic function, reduce its test cost, and improve the memory with logic function. This has the effect of increasing the failure detection rate and reliability of the system.

Although the invention made by the present inventor has been specifically explained based on examples, it is understood that this invention is not limited to the above-mentioned examples, and that various changes can be made without departing from the gist of the invention. Needless to say. For example, in FIG. 1, the number of stages of logic blocks provided in the memory with logic functions is arbitrary, and the clock-to-state RAM
The number of installations is also arbitrary. Further, the logic block can be provided at the subsequent stage of the clocked static type RAM, and the logic block and the clocked static type RAM
Various combinations of M may be considered. A test pad for inputting test data in parallel may be provided before the latch groups LGI and LG2, or the scan-in function can be removed by ~X from these latch groups and the clocked static RAM input latch IL. The combinations of test pads and external terminals that may be used are not limited by this embodiment. Furthermore, each part of the memory with logic function may be configured based on bipolar transistors, or may be configured by combining bipolar transistors and CMO3.

In FIG. 2, the input latches IL may perform scan-in including the input data latches DIL of k11 fil. The specific circuit configurations of the input latch IL and the output latch OL are not restricted by this embodiment. Furthermore, the order of the signals to be scanned in or scanned out is arbitrary, and the combination of the input signal and the output signal δ of the clocked state-controlled RAM is also arbitrary. It is.

In the above explanation, the invention made by the present inventor was mainly applied to a memory with logical functions, which is the field of application for which the invention was made, but it is not limited thereto. Static type RA
It can also be used in general purpose gate array 11 circuits including those used in half as M, clock to state RAM, and various dedicated digital circuits. The present invention can be widely applied to a clocked-state RAM having at least an input capacitor and a semiconductor integrated circuit device including such a locked static RAM.

[Effects of the Invention] A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows. That is, in a predetermined test mode, a slave latch in the form of a shift register is added to a memory with logic functions that includes multiple stages of logic blocks and clocked static RAM, and By adding a path that directly connects the output terminal of an input latch to the input terminal of the corresponding output latch in the above test mode, the input signal held in the input latch can be monitored by external test equipment. It is possible to accurately identify failures in logical blocks provided in the preceding stage of type RAM. As a result, while suppressing the increase in the number of circuit elements and the transmission delay time of input signals, it is possible to improve the diagnosability of memory with logic functions and reduce its test cost. Reliability can be increased.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a memory with logic functions to which the present invention is applied. $2 is a clone of the memory with logic functions in FIG. FIG. 3 is a circuit diagram showing an embodiment of the input connector, the output connector, and the output connector included in the Kudostate F-type RAM.
FIG. 4 is a block diagram showing an example of a logic machine burn-in memory developed by the present inventors prior to the present invention. LBI-LB3...Logic block, LGI-LG2.
...7th group, C3R...clocked static type RAM, IL...input latch, RAM...random access memory section, OL...output U, CH. ML...master latch, SL...slave latch, DIL...input data latch, DOL...output data roughage, Ql-Q5...N channel MO3FE
T.

Claims (1)

[Claims] 1. A semiconductor comprising a clocked static RAM including a random access memory section and an input latch, and capable of outputting a holding signal of the input latch to the outside in a predetermined test mode. Integrated circuit device. 2. The semiconductor according to claim 1, wherein in the test mode, the holding signal of the input latch is scanned out from a predetermined pad or external terminal in accordance with a predetermined clock signal. Integrated circuit device. 3. The input latches include a plurality of master latches that hold predetermined input signals and transmit them to the random access memory section in the normal operation mode, and a shift register form together with the master latches in the test mode to receive the input signals. 3. The semiconductor integrated circuit device according to claim 1, further comprising a plurality of slave latches that scan out from the pad or external terminal force. 4. The input latch includes an input data latch that holds input data and transmits it to the random access memory section, and the clocked static RAM further holds output data of the random access memory section and transmits it to the subsequent circuit. In the test mode, the input data held in the input data latch of the input latch is:
Claims 1 and 2 are characterized in that the data is output in parallel from the corresponding output data latch of the output latch via the corresponding pad or external terminal.
The semiconductor integrated circuit device according to item 1 or 3.