JPH0447588A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To suppress the occurrence of a defective product due to the excess of specification value of power consumption in standby time by activating a pre-charge signal synchronizing with a control signal for a constant period before activating a word line. CONSTITUTION:Such constitution that the pre-charge signal EQ2 is activated synchronizing with the control signal for the constant period before performing the activation of the word line WL is employed, thereby, a period to activate the pre-charge signal can be reduced. Therefore, when short-circuit between the word line WL and bit lines BL, the inverse of BL occurs, a current that flows from reference potential VR to a ground potential Vss side in the activating period of the pre-charge signal can be remarkably reduced. Thereby, it is possible to precisely prevent the defective product manufactured due to the excess of the specification value of the power consumption in the standby time even when the short-circuit occurs between the word line WL and the bit lines BL, the inverse of BL.

Description

Detailed Description of the Invention (Field of Industrial Application) The present invention is applicable to semiconductor storage devices such as dynamic RAM (random access memory), especially during standby (short circuit) caused by short circuits between word lines and bit lines.
The present invention relates to a semiconductor memory device that suppresses an increase in power consumption during a period of time.

(Prior Art) Conventionally, as this type of semiconductor memory device, there has been one as shown in FIG. 2, for example. The configuration will be explained below using figures.

FIG. 2 is a circuit diagram of a main part showing an example of the configuration of a conventional semiconductor memory device, for example, a dynamic RAM.

This semiconductor memory device includes a plurality of word lines WLI, WL2 . ... and a plurality of pairs of bit lines BL1, r, ... arranged to intersect therewith, and a plurality of memory cells 1-1 at each intersection point.
．． 1-2. ... are connected to each other.

Word lines WLI, WL2. . . . are connected to word line drive circuits 10, respectively. For example, word line W
In the word line drive circuit 10 connected to LI, the word line WL1 is connected to the power supply potential VCC via an N-channel type MO8)-transistor (hereinafter referred to as NMO3) 11.
is connected to the ground potential V through the NMO312.
Connected to SS. The gate of NMO3II is connected to the selection signal XD which is the output of the row address decoder, and the gate of NMO3II is connected to the selection signal
Connected to 12 gates.

Each bit line pair BLI, BLI, . . . has a plurality of sense amplifier circuits 20. activated (operated) by sense amplifier activation signals SAN, SAP. ... are connected, and each pit line pair BLI,
BL1. A plurality of precharge circuits 21 are connected to precharge each of . . . to a reference potential VR.

Further, each pit line pair BLI, BLI, . . . is connected to complementary data lines DB, D Each one is connected to a hundred.

FIG. 3 is an operational waveform diagram of FIG. 2, and the operation of the semiconductor memory device shown in FIG. 2 will be explained with reference to this diagram.

For example, data “1′° stored in memory cell 1-1
The read operation will be explained below.

When the control signal RAS falls, the precharge signal EQ falls and the precharge circuit r420 turns off.
Bit line pair BL1. BLI is disconnected from reference potential VR. Furthermore, with the fall of the control signal πXK, the selection signal XD of the row address decoder turns off the NMO812, turns on the NMO3II, and connects the word line WLI to the power supply potential ■CC, so that the word line WLI stands up. Then, a small potential difference is generated between the bit line pair BLI and "[T" due to the data buffer of the memory cell 1-1.

Next, when the sense amplifier activation signal SAN goes to "L" level and the sense amplifier activation signal SAP goes to "H" level, the sense amplifier circuit 20 is activated, and the sense amplifier circuit 20 activates the bit line pair BLI, Then, the transfer circuit 22 is turned on by the selection signal YD of the column address decoder, and the amplified potential difference on the bit line pair BL1. , [)100, and the data of the memory cell 1-1 is read.

(Problems to be Solved by the Invention) However, the apparatus with the above configuration has the following problems.

In the standby state where the control signal RAS is at the H level, the precharge signal EQ is at the H level, and the precharge circuit 21 sets the bit line pairs BLI, BLI, . . . to the reference potential VR.

Therefore, for example, if a short circuit occurs between the word line WLI and the bit line BL1, as shown by the broken line in FIG. Then, a current I flows from the reference potential VR to the ground potential SS, increasing power consumption during standby.

When such a short circuit occurs between the bit line BLI and the word line WLI, the memory cell 1-1 connected to it
．． ... becomes a defective memory cell, making it impossible to access accurate data. Therefore, in order to relieve such defective memory cells, usually a plurality of redundant memory cells are provided in advance, and the defective memory cells 1-1 . When .

However, when a short circuit occurs between a bit line and a word line, it usually causes an increase in power consumption of about 200 μA to 1 mA, so if multiple short points occur, the standard value of current consumption during standby (for example, about 1 mA>, and the semiconductor memory device itself becomes a defective product.Even if a redundant relief circuit as described above is provided to relieve the defective memory cell, the current ■Route remains.

Therefore, even if a defective memory cell is rescued by a redundant rescue circuit and the memory cell itself does not become defective,
Due to the short circuit, the current consumption exceeds the standard value, and the semiconductor memory device itself is treated as a defective product.

The present invention provides a semiconductor memory device that solves the problem of the prior art, which is increased power consumption due to short-circuits between bit lines and word lines.

(Means for Solving the Problems) In order to solve the above problems, the present invention includes a plurality of word lines activated based on a control signal, a plurality of bit line pairs arranged to cross the word lines, A plurality of memory cells connected to the intersections of each of the word lines and bit line pairs, and a plurality of memory cells connected to each of the bit line pairs and detecting and amplifying the potential difference between the bit line pairs using a sense amplifier activation signal. a sense amplifier circuit; and a plurality of precharge circuits that precharge each of the bit line pairs to a reference potential using a precharge signal. The precharge signal is activated in synchronization with a control signal.

(Function) According to the present invention, since the semiconductor memory device is configured as described above, when the precharge signal is activated in synchronization with the control signal when reading data from a memory cell, the precharge circuit is activated. The bit line pair is disconnected from the reference potential. Thereafter, the word line is activated and data in the memory cells connected to the word line generates a minute potential difference on the bit line crossing the word line. Then, this minute potential difference is detected and amplified by a sense amplifier circuit operated by a sense amplifier activation signal, and output to a data line via a transfer gate or the like.

Here, since the precharge signal is activated for a certain period of time before activating the bit line, the current path flows from the reference potential to the ground potential side via the precharge circuit, bit line, and word line. Since the current path does not always exist, that is, the current path occurs only during the above-mentioned fixed period, the occurrence of defective products due to exceeding the power consumption standard value during standby is suppressed, and the yield can be improved. Therefore, the above problem can be solved.

(Embodiment) FIG. 1 is a circuit diagram of a main part of a semiconductor memory device, for example, a dynamic RAM, showing an embodiment of the present invention.

This semiconductor memory device includes a plurality of word lines WLI.

WL2. . . . and a plurality of bit line pairs BLI, 100L1 . . . . and at each intersection point there is, for example, a one-transistor type memory cell 40-1.
．． 40-2. ... are connected to each other. Each memory cell 40-1.40-2. ... have drains or sources and gates connected to bit line pairs BL1, BL1, ... and word lines WLI, WL2, . NMO connected to...
341 and f7) a capacitor 42 connected to the source or drain of the NMO 841 and a reference potential VR (for example, 1/2·VCC).

Each word line WLI, WL2 . . . are connected to word line drive diagrams 850, respectively. The word line drive circuit 50 controls each word line WLI, WL2 . ...is a circuit that activates each. For example, the word line drive diagram I@50 connected to the word line WLI is connected to the word line WLI and the power supply potential VCC.
NMO351 connected between the word line WLI
and a ground potential VSS. The gate of the NMO 351 is connected to the selection signal XD and is also connected to the inverter 53 for signal inversion.
It is connected to the gate of NMO852 via.

Each bit line pair BLI, BL1 . . . . includes a sense amplifier circuit 60 that detects and amplifies the potential difference on the bit line pair.
are connected to each other. For example, bit line pair BLI
, BLI, the sense amplifier circuit 60 connected to NMO
861, 62 and a P-channel MOS transistor (hereinafter referred to as PMO8 with >63.64.NMO
361 is connected between bit line BLI and node N1, and N is connected between node N1 and bit line BLI.
MO862 is connected. Similarly, bit line BLI
A PMO363 is connected between the node N2 and the bit line 10L1, and a PMO363 is connected between the node N2 and the bit line 10L1.
64 are connected. The gate of NMO361 is PM
The gate of the NMO 362 is connected to the gate of the O863 and the bit line BLI, and the gate of the NMO 362 is connected to the gate of the PMO 864 and the bit line BLI.

The node N1 is connected to the sense amplifier activation signal SAN via the NMO 865 and to the reference potential VR (for example, 1/2·VCC) via the NMO 866. Similarly, node N2 is connected to sense amplifier activation signal SAP via NMO367, and
It is connected to the reference potential VR via MO368. N
The gates of MOs 365 and 67 are commonly connected and connected to precharge signal EQ2 via inverter 69. The precharge signal EQ2 is commonly connected to each gate of 8MO366 and 8MO68.

Each bit line pair BLI, BL1 . . . . are connected to NMOs 370 for equalization, which are turned on and off by the equalization signal EQ1. Furthermore, each bit line pair BL1. li go.

. . are activated by the precharge signal EQ2, and the corresponding bit line pair BLI, BL1 . ... as the reference potential VR
A precharge circuit 80 is connected to each of them. For example, bit line pair BLI.

■The precharge circuit 80 connected to the node N
1 and the bit line BLI, and an NMO 882 connected between the node N1 and the bit line BLI, and the NMOs 881 and 82 are turned on by the precharge signal EQ2. It is configured to operate off.

Each bit line pair BLI, BL1 . ... are connected to complementary data lines DB, [)100, respectively, via a transfer circuit 90. For example, pit line pair BLI, BL
The transfer circuit 90 connected to the bit line BL
NMO891 connected between I and data line DB,
NMO connected between bit line BLI and data line ■
892, whose NMOs 891 and 92 are turned on and off by a selection signal YD of a column address decoder.

FIG. 4 is an operational waveform diagram of FIG. 1, and the operation of the semiconductor memory device shown in FIG. 1 will be explained with reference to this diagram.

For example, data "1" is stored in the memory cell 40-1, and the read operation of the data "1" will be described below.

During standby, the control signal πAs is II HII
When the equalization signal EQI is at the "H1+ level", the equalization NMO 870 is turned on, and the bit lines BLI and "T are in a conductive state and maintained at approximately the reference potential VR.

When the control signal RAS falls, the precharge signal EQ2 becomes "H" level for a short time in synchronization with the fall, and a row address decoder (not shown) operates. When precharge signal EQ2 reaches 11 HI+ level, N
As MO865 and 67 turn off, NMO86
6 and 68 are turned on, and nodes Nl and N2 are connected to reference potential VR. Then, the bit lines BLI, BLI
A reference potential VR is applied to the bit line pair BLI, 10T
D is set to the initial state.

The reason for this initial setting is that the equalize signal EQ1 is
” level and turn on the equalizing NMO 870, the bit line potential may deviate from the reference potential VR due to parasitic capacitance etc. A reference potential VR is applied using a charge signal EQ2 to correct the deviation.

In addition, nodes Nl and N
When the reference potential VR is applied to the sense amplifier circuit 6
0 is inactivated, and malfunction of the sense amplifier circuit 60 is prevented.

When the precharge signal EQ2 falls to the 11 L I+ level, the equalizing signal EQI goes to the °L'°L'° level, the equalizing NMO 370 is turned off, and the pit lines BLI and r are separated. Thereafter, by the selection signal XD of the row address decoder (not shown), the NMO 851 in the word line drive circuit 50 is turned on, the NMO 852 is turned off, and the word line WLI is set to 1.
1 Rise to H11 level.

When word line WLI rises, memory cells 40-1 . ...NMO341 within
turns on, and the data II II stored in the capacitor 42 is transferred to the bit line BL1. . . , and a minute potential difference is generated between the bit line pairs BLI, 100T go, . At this time, the precharge signal EQ2 at the 11 L I+ level causes the NMO36 to
5 and 67 are in the on state.

Therefore, the sense amplifier activation signal SAN is
When the I+ level falls, the node N1 also falls to the "Lll" level via the NMO 865, and the sense amplifier circuit 6
The potential of the bit lines BLI, . . . is lowered through the NMO 862 in 0. Then, when the sense amplifier activation signal SAP rises to the HIT level, the NMO36
7, the potential of node N2 is pulled up via PMO 363 in sense amplifier circuit 60, and bit line BLI
, ... are also raised.

Due to such amplification operation of the sense amplifier circuit 60, when the potential difference between the bit line pair B L 1 , T, . A column address decoder (not shown) operates, and the selection signal Y of the address decoder
D is at “H゛°° level.

Then, the NMO 891°92 in the transfer circuit 90
turns on, bit line pair BL1. The amplified potential difference over 100πT is output to the data lines DB and 100,000, and data is read out.

After that, the equalize signal EQI becomes the "H° level" and the NMO870 is turned on, and the bit line BLI and the 77
The two terminals are connected and have the same potential. At this time, if only the NMO 370 is turned on, even if the potentials of the bit lines BLI and BLI become equal, they may deviate from the reference potential VR. Therefore, in order to correct this deviation, the precharge signal EQ is synchronized with the rise of the equalize signal EQ1.
2 also goes to II HI+ level for a short time, and the bit line BLI
.

A reference potential VR is applied to the 100T go.

In FIG. 1, for example, word line WLI and pit line BL
Consider the case where there is a short circuit between I and I.

If word line WLI and bit line BLI are short-circuited,
During standby, precharge signal EQ2 is “H”.
" level, as shown by the broken line in FIG. S
A current Ia flows to S. However, the precharge signal E
The period during which Q2 is at the "HT+ level" is limited to a certain short period (eg, 1/10 or less compared to the conventional one) before the word line WL1 reaches the "H1 level."

Therefore, in this embodiment, the increase in power consumption due to short-circuits between word lines and bit lines is extremely small compared to the conventional case. Therefore, even if a plurality of word line/bit line short circuits occur, the power consumption does not exceed the standard value as in the prior art, thereby reducing the number of defective products and improving yield. In particular, the longer the period in which the precharge signal EQ2 is at the HIGH level, the less power consumption is caused by word line/bit line shorts, which increases the number of word line/bit line shorts that can be tolerated. Yield is further improved.

Note that the present invention is not limited to the illustrated embodiment, and various modifications are possible. Examples of such modifications include the following.

(a> The precharge circuit 80, which is turned on and off by the precharge signal EQ2, may be configured using other transistors.
2, use NMO365 to 68 for driving the sense amplifier.
On/off control is performed, but the precharge signal E
The sense amplifier circuit 60 may be turned on and off using a signal separate from Q2.

(b) In the embodiment described above, initial setting is performed by turning on and off the equalizing NMO 870 using the equalizing signal EQI to bring the bit lines BLI and 100Tgo to the same potential. When such equalizing means is provided, as shown in FIG. 4, the equalizing signal EQI is L'.

At the time of rising from the level to the I Hl level,
It is not necessary to set the precharge signal EQ2 to the "H" level for a short period of time.

That is, if the precharge signal EQ2 is not raised to the "H" level, the bit line BL is
Even if the potentials of I and 100Ll become equal and the potential deviates from the reference potential VR, the precharge signal EQ2 will be activated for a short time in synchronization with the fall of the control signal ■Wmi during the next read operation, etc. During this period, it is at IIHI+ level, so that the deviation from the reference potential VR can be corrected by the "H" level. Therefore, in the latter stage of the read operation, the precharge signal EQ2 is not necessarily set to "H" for a short period of time.
There is no need to make it a par level.

Further, bit line BL1.
After setting the potential between U”t7 to the same potential, precharge signal EQ2
Since the configuration is such that the reference potential VR is applied by , the equalizing NMO 870 can be omitted if the parasitic capacitance of the bit lines B L 1 , iT, . . . can be reduced.

(C) Memory cell 40-1.40-2. ···teeth,
Although the cell is a one-transistor type, it may be configured with other circuits such as a two-transistor type, and the sense amplifier circuit 60 can also be modified to other transistor configurations. Also, bit line pair B between sense amplifier circuit #160 and memory cell 40-1.40-2°...
LI, BLI, 11. By providing a switch means and separating the sense amplifier circuit 60 from the memory cell side by the switch means, the sense amplifier circuit 60 is disconnected from the memory cell side.
It is also possible to speed up the sensing operation.

(Effects of the Invention) As described above in detail, according to the present invention, the precharge signal is activated in synchronization with the control signal for a certain period before activating the word line. Therefore, by shortening the activation period of the precharge signal, when the word line and bit line are shorted, the current flowing from the reference potential to the ground potential side during the activation period of the precharge signal can be significantly reduced. I can do it. Therefore, even if a short occurs between the word line and the bit line as in the past, it is possible to accurately prevent the power consumption during standby from exceeding the standard value and resulting in a defect, thereby suppressing the occurrence of defective products. A semiconductor memory device with high yield can be provided.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a main part of a semiconductor memory device showing an embodiment of the present invention, FIG. 2 is a circuit diagram of a main part of a conventional semiconductor memory device, and FIG. 3 is an operation waveform diagram of FIG. FIG. 4 is an operational waveform diagram of FIG. 1. 40-1.40-2...Memory cell, 50...
...Word line drive circuit, 60...Sense amplifier circuit, 70...NMO8, 8 for equalization
0...Precharge circuit, BLI, BLI...
...Bit line, EQl...Equalize signal, EQ2...Precharge signal, SAN, SA
P...Sense amplifier activation signal, ■CC...
...Power supply potential, VR...Reference potential, ■SS・
...Ground potential, WLI, WL2...Word line.

Claims (1)

[Claims] A plurality of word lines activated based on a control signal, a plurality of bit line pairs arranged to intersect with the word lines, and a plurality of memory cells respectively connected to the intersections of the word lines and the bit line pairs. , a plurality of sense amplifier circuits connected to each of the bit line pairs, each detecting and amplifying the potential difference between each of the bit line pairs using a sense amplifier activation signal; A semiconductor memory device comprising a plurality of precharge circuits for precharging, characterized in that the precharge signal is activated in synchronization with the control signal for a certain period of time before activation of the word line. A semiconductor storage device.