JPH0445568A - Manufacture of mos ic - Google Patents

Abstract

PURPOSE:To prevent the deterioration of a gate insulating film by implanting ions of impurities for punch through prevention and/or threshold voltage adjustment through a double-layer. CONSTITUTION:A pad silicon oxide film 2, a pad polysilicon film 3, and a silicon nitride film 4 being an oxidation-resistant film are formed selectively on the surface of a semiconductor substrate 1, and with this as a mask, the surface of the semiconductor substrate 1 is oxidated by heating to form a field insulating film 5. Next, the nitride film 4 and the pad polysilicon film 3 are removed, and the substrate 1 is masked selectively with a resist film PR. In that condition, the ion implantation of impurities for punch through prevention and/or threshold voltage adjustment is performed. Furthermore, by heating and oxidating the surface of the substrate 1, a gate insulating film 6 is formed. By doing it this way, the gate electrode can be deposited immediately after formation of the gate insulating film, so deterioration can be prevented.

Description

[Detailed description of the invention] The present invention will be described in the following order.

A. Industrial field of application B1 Overview of the invention C1 Prior art [Figure 5] B6 Problems to be solved by the invention E1 Means for solving the problems F0 Effects G. Examples [Figures 1 to 4 [Figures] a. One embodiment [Figures 1 and 2] b. Other embodiments [Figures 3 and 4] H1 Effects of the invention (A. Industrial application field) The present invention is based on MOSIC. The manufacturing method, especially M, can reduce the deterioration of the gate insulating film (or reduce the spacing between semiconductor wells with circuit systems driven by different power supply voltages).
The present invention relates to a method for manufacturing an OSIC.

(B. Summary of the Invention) In a MOSIC manufacturing method, the present invention provides a pad silicon oxide film that is the base of an oxidation-resistant film used as a mask when forming a field insulating film in order to reduce deterioration of a gate insulating film. Punch-through prevention and/or through the two-layer film of pad silicon oxide film and pad silicon film.
Alternatively, impurity ions are implanted to adjust the threshold voltage, and then a gate insulating film is formed. A semiconductor region having the same conductivity type as the substrate and having a higher impurity concentration than the substrate is formed between the wells simultaneously with another semiconductor well having the same conductivity type as the semiconductor substrate, which is selectively formed on the surface of the semiconductor well. It is something that forms.

(C, Prior Art) [Figure 5] In MOSIC manufacturing, it is essential to implant impurity ions into the active area in order to adjust the threshold voltage of the MoS transistor and prevent punch-through. Ion implantation of impurities to prevent punch-through and adjust threshold voltage has been performed through the gate insulating film after the gate insulating film is formed.

Recently, as shown in Fig. 5, MOSFETs have been developed in which transistors driven by different power supply voltages are mixed in one IC.
SIC is increasing. In FIG. 5, a is a p-type semiconductor substrate, b and c are n-type semiconductor substrates selectively formed on the surface of the semiconductor substrate a, and a semiconductor well b is 3.3 mm wide.
The semiconductor well C is biased at 5.5. P-type semiconductor wells d and e are selectively formed on the surface portions of semiconductor wells b and c, respectively. The n-type semiconductor wells b and c and the p-type semiconductor wells d and e each have a p channel or an n
A channel MO3I-transistor is formed.

(D. Problems to be Solved by the Invention) By the way, conventional MOSIC manufacturing involves implanting impurity ions through the gate insulating film to prevent punch-through and adjust the threshold voltage after forming the gate insulating film. According to this method, a problem arises in that the breakdown voltage of the gate insulating film decreases. This is because various processes such as the photoresist process, post-treatment, and pre-treatment are performed with the gate insulating film exposed on the surface, and the thickness of the gate insulating film itself has become thinner as devices become smaller. Because there is.

Furthermore, in the MOSIC shown in FIG. 5, it was necessary to increase the distance between the n-type semiconductor wells 0 to electrically isolate them. This is because the amount of depletion layer extending from wells b and c becomes large due to the reverse bias voltage.
There was a problem in that the degree of integration of the IC was restricted.

The present invention has been made to solve these problems; one purpose is to prevent deterioration of the gate insulating film, and another purpose is to prevent deterioration of the gate insulating film, and another purpose is to prevent the deterioration of the gate insulating film. The goal is to narrow the spacing between semiconductor wells.

(E. Means for Solving Problems) The MOSIC manufacturing method according to claim (1) is characterized in that a pad silicon oxide film or a pad silicon film is used as a base for an oxidation-resistant film used as a mask when forming a field insulating film. Claim (2) characterized in that impurity ions for punch-through prevention and/or threshold voltage adjustment are implanted through the two-layer film of an oxide film and a pad silicon film, and then a gate insulating film is formed. In this MOSIC manufacturing method, a semiconductor region having the same conductivity type as the substrate and having a higher impurity concentration than the substrate is selectively formed on the surface of the semiconductor well between semiconductor wells biased to different power supply voltages. It is characterized in that it is formed simultaneously with another semiconductor well of the same conductivity type as the semiconductor substrate.

(F. Effect) According to the MOSIC manufacturing method of claim (1), the gate insulating film is formed after the ion implantation of impurities for punch-through prevention and/or threshold voltage adjustment is completed. Immediately after forming the insulating film, a step of depositing the gate electrode can be performed. Therefore, there is no risk that the gate insulating film will deteriorate due to impurity ion implantation (
, no drop in breakdown voltage occurs.

According to the MOSIC manufacturing method of claim (2), impurities of the same conductivity type as the semiconductor substrate are doped between the semiconductor wells receiving different power supply voltages, so that the extension of the depletion layer extending from the semiconductor well is suppressed. Therefore, the interval provided between semiconductor wells can be made smaller.

(G. Embodiment) [FIGS. 1 to 4] Hereinafter, the method for manufacturing MO3IC of the present invention will be explained in detail according to the illustrated embodiment.

(a, one embodiment) [Fig. 1, Fig. 2] Fig. 1 (A)
1 to 3(G) are cross-sectional views showing one embodiment of the method for manufacturing MO5IC of the present invention in the order of steps.

(A) Pad silicon oxide film 2 on the surface of the semiconductor substrate 1;
A pad polysilicon film 3 and a silicon nitride film 4, which is an oxidation-resistant film, are selectively formed, and a field insulating film 5 is formed by heating and oxidizing the surface portion of the semiconductor substrate 1 using these as a mask. FIG. 1(A) shows the state after the field insulating film 5 is formed.

(B) Next, as shown in the same figure (B), the above-mentioned silicon nitride film 4 and pad polysilicon film 3 are removed.

(C) Next, as shown in the same figure (C), the semiconductor substrate 1 is selectively masked with a resist film PR, and in that state, for example, punch-through prevention and/or threshold Impurity ions are implanted for voltage adjustment, that is, the impurity ions are implanted through the pad silicon oxide film 2.

(D) Next, as shown in the same figure (D), the resist film PR
selectively mask locations on the semiconductor substrate l that are different from those in step (C), and in that state p-channel MOS
Impurity ions are implanted into the transistor to prevent punch-through and/or adjust the threshold voltage. That is, this impurity ion implantation is also performed through the pad silicon oxide film 2.

(E) Next, as shown in FIG. 3E, the pad silicon oxide film 2 is removed.

(F) Next, as shown in FIG. 2F, the gate insulating film 6 is formed by heating and oxidizing the surface portion of the semiconductor substrate 1.

(G) Thereafter, as shown in FIG. 3(G), a polycrystalline silicon layer 7 that will become a gate electrode is formed on the gate insulating film 6. After that, manufacturing is performed in the same manner as when manufacturing a normal MOSIC.

According to the manufacturing method of this MO3IC, the field insulating film 5
Pad silicon oxide film 2 used as a base for silicon nitride film 4, which is a mask during selective oxidation to form
The pad silicon oxide film 2 is removed, and the gate insulating film 6 is then formed. There is no risk that the gate insulating film 6 will deteriorate and the withstand voltage will drop due to the ion implantation of impurities for adjusting the threshold voltage. By the way, when performing ion implantation, it is necessary to provide an oxide film etc. to prevent channeling, and therefore it is normal to require a process such as oxidation to form the oxide film etc., but the manufacturing method of this MOSIC Since the pad silicon oxide film 2 is used to prevent channeling, no special process such as oxidation is required.

FIGS. 2(A) to 2(D) are cross-sectional views showing a modification of the MOSIC manufacturing method shown in FIGS. 1(A) to (G) in the order of steps.

(A) In the case of step (A) of the example shown in FIG.
Field insulating film 5 is formed by performing selective oxidation in the same manner. FIG. 2(A) shows the state after the field insulating film 5 is formed.

(B) Next, as shown in the same figure (B), only the silicon nitride film 4 is removed. In the embodiment shown in FIG. 1, the silicon nitride film 4 and the pad polysilicon film 3 were removed, but in this method, only the silicon nitride film 4 is removed.

(C), (D) After that, impurity photoresist film PR for punch-through prevention and/or threshold voltage adjustment
Figure 2 (C
) and (D), it is performed through the pad silicon oxide film 2 and the pad polysilicon film 3.

The subsequent steps are carried out in exactly the same manner as in the MOSIC manufacturing method shown in FIG. That is, the pad polysilicon film 3 and the pad silicon oxide film 2 are removed, then the gate insulator 1II6 is formed, and then the polycrystalline silicon layer 7 forming the gate electrode is formed.

It goes without saying that there is no risk of a drop in the withstand voltage of the gate insulating film 6 even with this MO5IC manufacturing method.

(b, Other Examples) [Figures 3 and 4] Figure 3 shows M
FIG. 2 is a cross-sectional view showing an OSIC.

In the figure, 1 is a p-type semiconductor substrate, 8 is an n-type semiconductor well receiving a bias of 3.3■, 9 is an n-type semiconductor well receiving a bias of 5■, and lO is the surface of the semiconductor well 8. a p-type semiconductor well selectively formed in
11 is a p layer selectively formed on the surface of the semiconductor well 9.
− type semiconductor well 12 is a p type semiconductor region formed simultaneously with p − type semiconductor well 10.11 on the surface of the region of semiconductor substrate 1 where semiconductor well 8.9 is not formed. Due to the presence of this region 12, the amount of extension of the depletion layer extending from the semiconductor well 8.9 can be reduced. This is because the semiconductor well 8.9 on the surface of the semiconductor substrate 10
This is because the impurity concentration between them is high.

Therefore, the space that must be provided between the semiconductor wells 8 and 9 for electrical isolation is small, and as a result, the MO'S
It is possible to improve the degree of integration of the IC.

Figures 4 (A), (B), and (C) are MOSIs shown in Figure 3.
FIG. 3A is a plan view showing a mask for selective impurity ion implantation used in manufacturing C, and FIG. 2A is a mask for forming an n-type semiconductor well 8.9. In addition, 13 indicates a light-shielding part on which a mask film of chromium or the like is formed.
A mask for forming a p-type semiconductor region 12 between a type semiconductor well 10.11 and a well 8.9 is shown, and FIG. 3C shows a mask for forming a p-channel stopper.

Note that the p-type semiconductor region 12 between the semiconductor wells 8 and 9 is
Since the - type semiconductor wells 10 and 11 can be formed simultaneously, there is no need to provide a special process for forming the p-type semiconductor region 12. Therefore, high integration can be achieved without increasing the number of processes. .

(H, Effect of the invention) As stated above, the present invention MO3IC of claim (1)
The manufacturing method is to selectively oxidize the semiconductor substrate using a pad silicon oxide film or an oxidation-resistant film formed via a two-layer film of a pad silicon oxide film and a pad silicon film as a mask to form a field insulating film. In a method for manufacturing a MOSIC, impurity ions are implanted for punch-through prevention and/or threshold voltage adjustment through the pad silicon oxide film or through the pad silicon oxide film after the oxidation-resistant film is removed. The gate insulating film is formed after removing the pad silicon oxide film or the two-layer film of the pad silicon oxide film and the pad silicon film. .

Therefore, according to the MOSIC manufacturing method of claim (1), since the gate insulating film is formed after the ion implantation of impurities for punch-through prevention and/or threshold voltage adjustment is completed, the gate insulating film is formed. Immediately thereafter, a step of depositing a gate electrode can be performed. Therefore, there is no risk that the gate insulating film will deteriorate due to impurity ion implantation, and a decrease in breakdown voltage will not occur.

The method for manufacturing a MOSIC according to claim (2) includes forming second conductivity type semiconductor wells that are biased at different voltages on the surface of a low concentration first conductivity type semiconductor substrate, and forming separate second conductivity type semiconductor wells that are biased to different voltages from each other. In a MOSIC manufacturing method in which a first conductivity type semiconductor well having a higher impurity concentration than a semiconductor substrate is selectively formed on the surface of the well, a second conductivity type semiconductor well is simultaneously formed by selectively doping the first conductivity type impurity.
This method is characterized in that impurities of the first conductivity type are also doped between the conductivity type semiconductor wells.

Therefore, according to the MOSIC manufacturing method of claim (2), since impurities of the same conductivity type as the semiconductor substrate are doped between the semiconductor wells receiving different power supply voltages, the extension of the depletion layer extending from the semiconductor well is suppressed. Ru. Therefore, the interval provided between semiconductor wells can be made smaller.

[Brief explanation of drawings]

FIGS. 1(A) to (G) are cross-sectional views showing one embodiment of the method for manufacturing MO5IC of the present invention in the order of steps; FIGS. 2(A) to (D) are cross-sectional views showing a modified example in the order of steps; 3 and 4 (A) to (C) are for explaining other embodiments of the MO3IC manufacturing method of the present invention, FIG. 3 is a cross-sectional view of the manufactured MOSIC, and FIG. ) to (C) are plan views showing the impurity selective ion implantation masks used in manufacturing in order of use, and FIG. 5 is a sectional view of a conventional MOSIC. Explanation of symbols 1... Semiconductor substrate, 2... Pad silicon oxide film, 3...
Pad polysilicon film, 4... Oxidation resistant film, 6... Gate insulating film, 8.9... Second conductivity type semiconductor well, 10.1
1...First conductivity type semiconductor well, 12...
...A region doped with a first conductivity type impurity.

Claims (2)

[Claims] (1) A field insulating film is formed by selectively oxidizing the semiconductor substrate using a pad silicon oxide film or an oxidation-resistant film formed on the semiconductor substrate via a two-layer film of a pad silicon oxide film and a pad silicon film as a mask. MOS
In the method for manufacturing an IC, impurity ions are implanted for punch-through prevention and/or threshold voltage adjustment after the oxidation-resistant film is removed, or through the pad silicon oxide film or between the pad silicon oxide film and the pad silicon film. A method for manufacturing a MOSIC, comprising: forming a gate insulating film after removing the pad silicon oxide film or the two-layer film of the pad silicon oxide film and the pad silicon film. (2) Separately formed second conductivity type semiconductor wells biased to different voltages from each other are formed on the surface of a low concentration first conductivity type semiconductor substrate, and impurities are added to the surface of each second conductivity type semiconductor well from the semiconductor substrate. In a MOSIC manufacturing method for selectively forming semiconductor wells of a first conductivity type with a high concentration, the semiconductor wells are formed by selectively doping the impurity of the first conductivity type, and the first conductivity is also formed between the semiconductor wells of the second conductivity type. A method for manufacturing MOSIC characterized by doping with type impurities