JPH0444271A - Manufacture of semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To reduce the number of thermally diffusing steps at a high temperature for a long time, to shorten a manufacturing time, to decrease a process cost and to further prevent a decrease in a yield due to a thermal distortion by forming a diffused region for isolate and a low concentration diffused region for drain by the same step. CONSTITUTION:P-type impurity such as boron is selectively diffused in high concentration in a P-type substrate 1 to form a buried region 4 for element isolation. Then, an oxide film 3 is formed, coated with resist 5, and the resist 5 on the element isolation region and a low concentration drain region is re moved by a photolithogrpahy method. Further, with the patterned resist 5 as a mask the film 3 is etched by using an etchant. Thereafter, with the resist 5 and the film 3 as masks P-type impurity such as boron or the like is ion- implanted to form a drain impurity ion implanting region 6 and an impurity ion implanted region 7 for isolation. The resist 5 is removed, a thermally diffus ing step is conducted, and a low concentration diffused region 8 for drain and a diffused region 9 for isolation are formed.

Description

[Detailed Description of the Invention] [Industrial Applications 1] The present invention is applicable to voltage regulators, motor controls,
The present invention relates to a method for manufacturing an integrated circuit including a field effect semiconductor device (hereinafter abbreviated as DMO 5) using a double diffusion type 1 capable of driving with high power and used in audio amplifiers and the like.

[Summary of the Invention] The DMO 5 is a transistor in which a base region and a source region are formed by self-alignment using a gate electrode as a mask, and the base region under the gate electrode functions as a channel. In DMO5, the channel length is determined by the difference in lateral diffusion between the base region and the source region, compared to a normal MOS whose channel length is determined by the width of the gate electrode.

When manufactured using the same design rules, they have short channel lengths, high values, and low on-resistance, making them suitable for high power drive. The drain region of the DMOS includes a low concentration diffusion region surrounding the base region and the source region, and a wiring electrode arranged on the low concentration diffusion region to be separated from the source region for making ohmic contact. The present invention, which is composed of a high concentration diffusion region, simplifies the manufacturing process by performing thermal diffusion of the low concentration diffusion region for the drain and the diffusion region for element isolation in the same process.

[Prior Art] A conventional method for manufacturing a semiconductor integrated circuit is shown in Fig. 2 (a).
) to (e).

In FIG. 2(a), a P-type buried region 4 is selectively formed on a P-type substrate 1, an N-type epitaxial layer 2 is formed by epitaxial growth, and the surface of the epitaxial layer 2 is oxidized. This is a cross-sectional view of the integrated circuit after the step of forming oxide 1 [13] Next, the oxide film 3 is selectively etched using the resist 5 as a mask, and the isolation P is etched using the resist 5 and the oxide film 3 as a mask. Type impurity ions are selectively implanted onto the N type epitaxial layer 2 (FIG. 2(b)), and then,
In order to diffuse the impurity ions for isolation, heat treatment is performed at high temperature and for a long time to connect the isolation diffusion region 9 to the buried region 4 (FIG. 2(c)). Although it depends on the thickness and the degree of autodoping into the epitaxial layer of the buried region 4, it is usually 5 to 10
When forming an epitaxial layer with a thickness of 110 μm,
Next, the oxide film 3 is selectively etched using the resist 5 as a mask, and P-type impurity ions for the drain are etched using the resist 5 and the oxide film 3 as a mask. is selectively implanted onto the N-type epitaxial layer 2. (FIG. 2(d)), Next, 100 to 12
Heat treatment is performed at 00°C (Fig. 2(e)).

[Problems to be Solved by the Invention] As described above, in the conventional method, the heat treatment for forming the isolation diffusion region and the heat treatment for forming the low concentration expanded #1 region for the drain are performed in different steps. Both of the two heat treatments described above require several hours of processing time, which is longer than other processes, and are a major factor in increasing the manufacturing time of integrated circuits.

[! ! Means for Solving the Problem] It was decided that the isolation diffusion region and the drain low concentration diffusion region were formed in the same process. In order to optimize the characteristics of a semiconductor integrated circuit, it is necessary to make the diffusion profile of the isolation diffusion region and the train diffusion region different from each other. It was decided to use different ion implantation conditions for impurity introduction, and to perform at least the heat treatment for forming the diffusion region 1 in the same process.

[Function] Since one or two high-temperature, long-time heat treatment steps can be omitted, the manufacturing time of integrated circuits can be shortened.

[Embodiment 1] A first embodiment of the method for manufacturing a semiconductor integrated circuit according to the present invention will be described using sequential cross-sectional views of the manufacturing steps shown in FIGS. 1(a) to 1(d). In FIG. 1(a), a buried region 4 for element isolation is formed by selectively diffusing P-type impurities such as boron to a high concentration on a P-type substrate l, and then N-type impurities such as phosphorus are diffused onto the P-type substrate l. 1
0"-10cm-" doped epitaxial layer 2
The surface of the epitaxial layer 2 is oxidized by a thermal oxidation method to a thickness of 3000 to 500 μm!
113, which is a cross-sectional view of the integrated circuit after forming 113,
A resist 5 is applied on the oxide 1113, and the resist 5 on the element portion Ii region and the low concentration drain region is removed using a photolithography method. Furthermore, the oxide film 3 is etched using an etching solution containing hydrofluoric acid using the paquerated resist 5 as a mask. By controlling the etching conditions so that the oxide film in the portion to be etched is etched several hundred times over the epitaxial layer 2, the damage to the surface of the epitaxial layer caused by the subsequent ion implantation process is alleviated. P-type impurity such as boron is ion-implanted using 113 as a mask to form an impurity ion-implanted region 6 for the drain and an impurity ion-implanted region 7 for isolation (FIG. 1(b)). Next, the resist 5
is removed and subjected to a thermal diffusion process for 5 to 10 hours at a temperature of 1100 to 1200°C to form a low concentration diffusion region for drain t! i8
, and forming the isolation diffusion region 9 (FIG. 1(C))
, the ion implantation conditions and the thermal diffusion conditions are such that the isolation diffusion region 9 and the isolation buried region 4 are electrically conductive, and the drain low concentration diffusion region 8 is not electrically conductive with the substrate l. Optimized as follows. Figure 1(d) is
), the DMOS gate electrode 14, base region 11, source region 12 . 6 is a cross-sectional view of an integrated circuit in which a high concentration diffusion region 13 for a drain is formed.According to the first embodiment of the present invention, the ion implantation process and the thermal diffusion process can be omitted, respectively, compared to the conventional method, so that the manufacturing time is reduced. The shortening effect is significant.Next, a second embodiment of the method for manufacturing a semiconductor integrated circuit according to the present invention will be described using the sequential cross-sectional views of the manufacturing process shown in FIGS. 3(a) to 3(e). The method for manufacturing semiconductor integrated circuits is DMO
It can also be applied to integrated circuits in which S and normal MOS or PNN diodes for ESD protection are present. In this case, the P-well forming the NMOS channel 5IJI region, the low-concentration diffusion for the DMOS train, the P-type diffusion for the diode, and the P-type diffusion for isolation are all preferably relatively low-concentration and deep P-type diffusions. The process-simplified Kamiyogetsu is formed in the same process. However, the diffusion profile of the P-well is a factor that determines the vTM and mobility of the NMOS, and the diffusion profile of the P-type diffusion of the diode is a factor that determines the breakdown voltage, which is the protection voltage of the circuit. There is a problem in that the diffusion profile cannot be optimized. In addition, if the amount of autodoping in the buried region is not large enough, the low concentration diffusion for the DMOS drain and the substrate are not connected, and the thermal diffusion for connecting the P-type diffusion for isolation and the buried region is performed. There is also the problem that the margin for the condition is small. The above two problems can be solved by forming the NMOS P well and DMOS drain low concentration diffusion under the first ion implantation condition, and forming the isolation P type diffusion and the diode P type diffusion under the second ion implantation condition. However, this problem can be solved, for example, by using a higher dose for the second ion implantation condition than for the first ion implantation condition. Figure 3 (a
) is a cross-sectional view of the integrated circuit after the same process as in FIG. 1(a), and FIG. 3(b) is a cross-sectional view of the integrated circuit after the same process as in FIG. 1(bJ). The ion implantation conditions for the type impurity are, for example, poron ions, 100KeV, 10" to 1
0"crn-" 6 Next, without removing the resist 5, a resist 15 is applied and patterned by photolithography to mask the ion implantation region 6 for the drain of the DMOS. resist 5,
Using the resist 15 as a mask, boron ions are implanted at, for example, 100 to 150 KeV, 10th to 1st
Ion implantation is performed in the isolation region under an implantation condition of 0 cm- to form ion implantations t1i16 (FIG. 3(c)).

Next, after removing resist 5.15, 1100~12
Heat treatment is performed at 00°C for 3 to 10 hours (Fig. 3(d)).
The P-type diffusion 9 for isolation has the same thermal diffusion conditions as the P-type diffusion 8 for drain, but because the amount of ions implanted is larger, it becomes a deep and highly concentrated diffusion region, and the margin of the thermal diffusion conditions is It gets expensive. Also, the NMOS formed at the same time
Since the diffusion profile can be determined independently for the P-well and P-type diffusion of the diode, the characteristics of each element can be optimized. Figure 3(e)
After the step shown in Figure 3(d), D is obtained through multiple steps.
FIG. 2 is a cross-sectional view of an integrated circuit in which a MOS gate electrode 14, a base 1N region 11, a source region 12, and a heavily doped drain region 13 are formed. The depth of the drain low concentration diffusion region 8 is determined so that the breakdown voltage of the base region 11 and the epitaxial layer 2 is sufficiently high.

[Effects of the Invention] According to the method for manufacturing a semiconductor integrated circuit of the present invention, the number of thermal diffusion processes that require high temperatures and long periods of time can be reduced, thereby shortening the manufacturing time of integrated circuits, reducing processing costs, and preventing yield loss due to thermal distortion. In the second embodiment of the present invention, the ion implantation for separation and diffusion is performed twice, but for example, the ion implantation for separation and diffusion and the ion implantation for drain diffusion are performed in separate steps, It is clear that the effects of the present invention can be obtained even when the injection conditions are changed.

[Brief explanation of drawings]

1(a) to 1(d) are cross-sectional views in the order of manufacturing steps of the first embodiment of the method for manufacturing a semiconductor integrated circuit according to the present invention, and FIGS. 2(a) to 2(d) are
(e) A sectional view in the order of manufacturing steps of a conventional method for manufacturing a semiconductor integrated circuit; FIGS. be.・ ・ ・ ・ ・ ・ ・ ・ 2 ・ ・ ・ ・ ・ ・ 3, l Ol 17 ・ 4 ・ ・ ・ ・ ・ ・ 5, 15 ・ ・ ・ ・ 6, 7.16 ・ ・ ・Substrate・Epitaxial layer・Oxide film/embedded region/resist/impurity ion implantation region Mitsakai single thin integrated circuit N load)-Ta's first large hill example Isolation diffusion region Base region Source region Drain high concentration diffusion region Gate electrode Above Applicant Seiko Electronics Co., Ltd. Agent Patent attorney Takayuki Hayashi Crab 1R mortar for manufacturing method of Minero Io Hayabusa horizontal circuit i button diagram figure 2

Claims (3)

[Claims] (1) A base region of an opposite conductivity type is disposed on a drain region of one conductivity type, a source region of one conductivity type is disposed on the base region, and the base is sandwiched between the drain region and the source region. In a method of manufacturing a semiconductor integrated circuit including a double-diffused field effect semiconductor device in which a channel region is formed on the surface of a region, the drain region of one conductivity type and the diffusion region of one conductivity type for element isolation are formed in the same thermal diffusion region. A method for manufacturing a semiconductor integrated circuit, characterized in that it is formed in a process. (2) The method of manufacturing a semiconductor integrated circuit according to item 1, wherein impurity introduction for forming the drain region and the element isolation diffusion region is performed using the same ion implantation step. (3) The method for manufacturing a semiconductor integrated circuit according to item 1, wherein the ion implantation conditions for forming the drain region and the ion implantation conditions for forming the diffusion region for device separation are different.