JPH0441660Y2 - - Google Patents

Description

[Detailed description of the invention] [Industrial field of application] The present invention relates to a vertical synchronization separation circuit used in television receivers, and in particular to a vertical synchronization separation circuit that can stably separate the vertical synchronization signals even for narrow vertical synchronization signals. It provides a separation circuit.

[Conventional technology]

FIG. 2 shows a conventional example. A capacitor 2 and a resistor 4 are connected to the composite video signal input terminal 1, and the other end of the capacitor 2 is connected to the emitter of a transistor 5 and the other end of the resistor 4 via a resistor 3. The base of the transistor 5 is connected to a bias terminal 22 to which a bias voltage is supplied, and the collector is connected to the power supply terminal 22 via diodes 6 and 7, as well as to the resistor 8 and the base of the transistor 10. The other end of the resistor 8 is connected to the emitter of the transistor 10 and connected to the power supply terminal 26 via the resistor 9.
connected to. The collector of the transistor 10 is
The emitter is connected to the collector and base of a transistor 11 which is grounded via a resistor 12, and the emitter is connected to the base of a transistor 14 which is grounded via a resistor 13. The collector of transistor 14 is grounded via capacitor 21 and is also connected to the collector of transistor 15 and comparator 23 . The base of the transistor 15 is connected to a bias terminal 19, and the emitter is connected to a power supply terminal 26 via a resistor 16. Comparator 2
The other input terminal 24 of 3 is supplied with a voltage providing the threshold of the comparator 23, and the output signal is selected from the output terminal 25.

Next, the operation of FIG. 2 will be explained. A signal video signal is input to terminal 1, transistor 5 becomes conductive only during the synchronization signal input period, and accordingly diodes 6 and 7
Then, transistor 10 becomes conductive and the composite synchronization signal is synchronously separated. Here, resistor 8 is R ₈ and resistor 9 is
If R ₉ is also R ₉ and the current flowing through the transistor 10 is I 1 , I ₁ is given by I ₁ =V _BE (7)/R ₉ −V _BE(10) /R ₈ .

To simplify the explanation, suppose that the resistance values of resistors 12 and 13 constituting the current mirror are equal, and the emitter areas of transistors 11 and 14 are equal.
A current I ₁ proportional to the synchronizing signal flows through the transistor 11 and is taken out to the collector of the transistor 14 . Assuming that the current flowing through the transistor 15 and resistor 16 that constitute the constant current source is _I2 , the capacitor 21 is charged by the constant current _I2 when no synchronizing signal is input, and when the synchronizing signal is input, the current flowing through the transistor 15 and resistor 16 is proportional to the synchronizing signal. The capacitor 21 is discharged by the difference current between the current I ₁ and the constant current I ₂ . Here, the discharge voltage is E ₀ ,
When the width of the synchronizing signal is ΔT and the value of the capacitor 21 is C, the discharge voltage E ₀ is given by E ₀ =(I ₁ −I ₂ )/C·ΔT (1).

As described above, frequency separation is performed by charging and discharging the capacitor 21, and the vertical synchronization signal is separated from the composite synchronization signal.

First, FIG. 3 shows the waveforms of various parts when a vertical synchronizing signal with a regular width is input. In the third
(A) shows the synchronously separated composite synchronization signal (the width of the vertical synchronization signal is indicated by _T1 ), (B) shows the integral waveform of the capacitor 21, and (C) shows the output waveform of the comparator.

Assuming that the threshold of the comparator 23 is given and the potential of the bias source supplied to the input terminal 24 is V _th , as shown by the dotted line in Figure 3 (b), in the case of a normal width signal, the vertical synchronization signal is larger than the width of the horizontal synchronization signal. Since the width of is more than five times, the discharge voltage E ₀ when the vertical synchronizing signal is input is larger than when the horizontal synchronizing signal is input, and as a result, it exceeds the threshold of the comparator 23 and the output 25 of the comparator 23 becomes the voltage E0 shown in FIG. A vertical synchronization signal indicated by a dotted line is extracted.

[Problem that the invention attempts to solve]

By the way, for tapes intended to prevent dubbing on VTRs, the width of the vertical synchronization signal is longer than the normal width, as shown by the solid line in Figure 3A (the vertical synchronization signal is indicated by T ₂ for ease of viewing). In some cases, the signal is about 1/3 of the width of the signal. In the conventional example described above for such signals,
As shown by the solid line in FIG. 3B, the capacitor is discharged only when the vertical synchronizing signal is input, and is charged before the potential drops to the comparator threshold _Vth , making it impossible to extract the vertical synchronizing signal.

If the current I ₁ flowing through the transistor 10 is increased or the current I ₂ flowing through the transistor 15 is decreased in order to extract the vertical synchronization signal, the synchronization separation sensitivity increases and the noise resistance performance deteriorates.

As described above, the above-described conventional vertical synchronization separation circuit has the disadvantage that it is not possible to frequency-separate the narrow vertical synchronization signal.

[Means for solving problems]

In order to solve the above-mentioned conventional problems, the present invention includes a current source that separates a composite synchronization signal and flows a current proportional to the composite synchronization signal, and a resistor and a transistor connected to this current source through a current mirror circuit. a capacitor whose other end is grounded and which is charged by the current from the constant current source and discharged by the difference current between the current source and the constant current source; In a vertical synchronization separation circuit equipped with a comparator that extracts a vertical synchronization signal by comparing it with a threshold set as an input, the constant current source is turned on only during a period when a pulse with a pulse width corresponding to the vertical synchronization period is input. The present invention is characterized in that a circuit for reducing the flowing current is provided in parallel to the resistor of the constant current source. The pulse generator can easily generate a pulse using a countdown method in which a vertical pulse and a horizontal pulse are frequency-divided and generated.

〔Example〕

FIG. 1 shows an embodiment of the present invention.

The same parts as those in the conventional example are given the same reference numerals and the explanation will be omitted. The circuit shown in FIG.
and a resistor 18, and a transistor 17
The emitter of the transistor 15 is connected to the power supply terminal 26, its base is connected to the pulse input terminal 20, and its collector is connected to the connection point between the emitter of the transistor 15 and the resistor 16 via the resistor 18.

Next, the operation of FIG. 1 will be explained. A composite video signal is input to terminal 1, and the narrow composite sync signal of the vertical sync signal shown by the solid line in Fig. 4A is synchronously separated.
A current I ₁ proportional to this is taken out from the collector of the transistor 14 as in the conventional example. Further, a pulse having a pulse width corresponding to the vertical synchronization period shown in FIG. The current I ₂ decreases. Therefore, for the horizontal synchronization signal, the integrated waveform in the capacitor 21 is the same as in the conventional example, but for the vertical synchronization signal, as can be seen from equation (1), the constant current I ₂ decreases, so the discharge occurs. As the voltage E ₀ increases, the charging voltage due to the constant current I ₂ decreases during the period when no vertical synchronization signal is input, and the next vertical synchronization pulse is input before the potential of the capacitor 21 has risen completely, and the threshold of the comparator V _th is reached. reach

In other words, the synchronization separation sensitivity increases during the vertical synchronization period, the integrated waveform of the capacitor becomes a waveform as shown by the solid line in Figure 4C, and the output of the comparator becomes the 4th waveform.
The waveform becomes as shown by the solid line in Figure D, and the vertical synchronization signal is extracted.

[Effects of the invention] As explained above, the vertical synchronization separation circuit according to the invention increases the vertical synchronization separation sensitivity by reducing the current of the transistor 15 constituting the constant current source during the vertical synchronization period, and reduces the width of the vertical synchronization signal. This has the effect of stably extracting the vertical synchronization signal even from narrow signals.

Further, as shown by the dotted lines in FIG. 4C and D, there is no problem at all with respect to the vertical synchronization signal having a regular width, and the noise resistance performance is not deteriorated.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram showing one embodiment of the present invention;
3 is a circuit diagram showing a conventional example, FIG. 3 is a waveform diagram used to explain the operation of FIG. 2, and FIG. 4 is a waveform diagram used to explain the operation of FIG. 1. 1 is a composite video signal input terminal, 2 and 21 are capacitors, 3, 4, 8, 9, 12, 13, 16, 18
are resistors, 5, 10, 11, 14, 15, 17 are transistors, 6, 7 are diodes, 19, 22,
24 is a bias terminal, 20 is a pulse input terminal, 2
6 is a power supply terminal, 23 is a comparator, and 25 is an output terminal.

Claims (1)

[Claims for Utility Model Registration] A current source that separates a composite synchronous signal and flows a current proportional to the composite synchronous signal, and a constant current source that is connected to this current source via a current mirror circuit and is composed of a resistor and a transistor. and a capacitor whose other end is grounded, which is charged by the current from the constant current source and discharged by the difference current between the current source and the constant current source, and the terminal voltage of this capacitor is set as input. A circuit for reducing the current flowing through the constant current source only during a period in which a pulse with a pulse width corresponding to a vertical synchronization period is input, in a vertical synchronization separation circuit comprising a comparator that extracts a vertical synchronization signal by comparing it with a threshold value. is provided in parallel with a resistor of the constant current source.