JPH04394B2 - - Google Patents

Description

[Detailed Description of the Invention] [Industrial Application] The present invention has a vertical embedded capacitor configured with a dielectric layer and two dielectric layers sandwiching the dielectric layer. This invention relates to improvements in a 1-transistor/1-capacitor type semiconductor memory device and its manufacturing method. In other words, 1 has a vertical buried capacitor configured to use a depletion layer generated between the p-n junction to which a reverse bias is applied.
-Relates to improvements in semiconductor memory elements and methods for manufacturing the same, which are aimed at eliminating the drawbacks of transistor/1-capacitor type semiconductor memory devices.

[Conventional technology]

It is well known that elements constituting a semiconductor device are composed of active elements and passive elements, and the passive elements are mainly resistors and capacitors. Although these passive elements are simple in structure, they require a large surface area on the surface of the semiconductor layer, and have been a bottleneck for improving the degree of integration.

In the prior art, both resistors and capacitors were arranged two-dimensionally on a semiconductor layer, but it was obvious that if they could be arranged three-dimensionally, it would be extremely effective for improving the degree of integration. However, (a) it is not always easy to accurately form a narrow, deep, groove-like opening in a semiconductor layer, and (b) a conductive layer, especially a metal layer, is formed on the inner wall of such a groove-like opening. For reasons such as the fact that it was not always easy to form a vertical buried capacitor, there are no vertical buried capacitors other than vertical buried capacitors that use a depletion layer generated between a p-n junction to which a reverse bias is applied. Unfortunately, it has not been realized. In other words, a vertical buried capacitor configured with a dielectric layer and two dielectric layers sandwiching this dielectric layer has not yet been realized.

On the other hand, as a semiconductor memory device, a so-called 1-transistor/1-capacitor type semiconductor memory device has been developed, which uses a field-effect transistor as a driver and a capacitor as an information storage element. At the beginning of development, the capacitor of a type semiconductor memory device was formed planarly on the surface of a semiconductor layer.

However, even in this 1-transistor/1-capacitor type semiconductor memory device, there is an extremely important need to improve the degree of integration, so the capacitors used in this device are formed planarly on the surface of the semiconductor layer. If this could be realized using a vertical embedded capacitor instead of a capacitor with a similar structure, the benefits would be extremely large.

In order to meet this demand, we have developed 1-transistor and 1-transistor devices with vertical embedded capacitors of various structures.
-Capacitor type semiconductor memory devices have been developed, but the vertical buried capacitors used in these devices are all p-type with reverse bias applied.
This is a vertical buried capacitor configured to use a depletion layer generated between n-junctions.

The structure and operating principle of two examples (both disclosed in Japanese Patent Laid-Open No. 51-130178) will be explained with reference to the drawings.

First example: An extension region of, for example, an n-type drain formed along the inner wall of a narrow and deep groove-like opening formed in a semiconductor layer, and a semiconductor of, for example, p-type, formed in the extension region of the drain. Refer to FIG. 5. In the figure, 11 is, for example, a p-type semiconductor substrate, and 12 is, for example, an n-type source. The drain region 12 is a drain region, and the drain region 12 is an opening 19.
(In the figure, it is buried with a semiconductor layer 21.) It extends both along the inner wall of the semiconductor substrate and into the semiconductor substrate. 13 is a gate insulating film, and a gate electrode 14 forming a word line is formed on this gate insulating film 13, and in this example extends in a direction perpendicular to the plane of the paper. Reference numeral 15 denotes a source electrode forming a bit line, which in this example extends in the left-right direction along the plane of the drawing, and 20 a source electrode on the inner wall of the opening 19 filled with the semiconductor layer 21 and on the semiconductor substrate 11.
This is an insulating film formed on top. 16 is an interlayer insulating film.

Here, when a positive voltage is applied to the gate electrode 14 forming the word line and the source electrode 15 forming the bit line, a channel is generated under the gate electrode 14, and the drain region 12 and the inner wall of the opening 19 are connected to each other. A positive charge is supplied to the drain extension region 12 formed in the semiconductor substrate along with the drain extension region 12 . However, if the potential of the semiconductor substrate 11 is lower than the bit line potential due to reasons such as the semiconductor substrate 11 being grounded, the voltage generated by the above positive charges will be
For example, since the p-n junction existing between the p-type semiconductor substrate 11 and the n-type drain extension region 12 has a reverse bias voltage, the drain extension region 12 and the semiconductor substrate 11 are depleted. layer 22
The drain extension region 12, the depletion layer 22, and the semiconductor substrate 11 constitute a capacitor, and the positive charge (positive voltage applied to the source electrode 15 forming the bit line) is is stored in this capacitor, and 1-transistor 1
- It functions as a capacitor type semiconductor memory element.

Second example: For example, by applying a positive voltage to a conductor layer, for example, a metal layer, formed on the inner wall of a narrow and deep groove-like opening formed in a semiconductor layer via an insulator layer. For example, the inversion layer and depletion layer generated in the p-type semiconductor substrate, and the above-mentioned insulator layer.
Refer to FIG. 6. In the figure, 11 is, for example, a p-type semiconductor substrate, and 12 is, for example, an n-type source region. 1
3 is a gate insulating film, and a gate electrode 14 forming a word line extends in a direction perpendicular to the plane of the paper in this example. Reference numeral 15 denotes a source electrode forming a bit line, which in this example extends in the horizontal direction along the plane of the paper. 20 is an insulating film formed on the inner wall of the opening 19 and on the semiconductor substrate 11, and 16 is an interlayer insulating film. 23 is a conductive film formed on the insulating film 20 formed on the inner wall of the opening 19;
In this example, it is held at a positive potential. As a result, an inversion layer (n-type region in this example) 24 and a depletion layer 22 are generated in the semiconductor substrate 11 in a region facing the conductor film 23 with the insulating film 20 interposed therebetween. The depletion layer 22 and the semiconductor substrate 11 constitute a capacitor.

Here, when a positive voltage is applied to the gate electrode 14 forming the word line and the source electrode 15 forming the bit line, a channel is generated under the gate electrode 14, and the source electrode 15 forming the bit line connects to the above capacitor. It functions as a 1-transistor/1-capacitor type semiconductor memory element.

[Problem to be solved by the invention]

As mentioned above, the conventional 1-transistor/1-capacitor type semiconductor memory device with a vertical buried structure has a depletion layer (in addition to this) generated between the p-n junction to which a reverse bias is applied. ,
In the second example, since a capacitor with a structure using an inversion layer is used, the inherent limitation of a capacitor with this structure is that a region surrounding the groove and allowing the expansion of the depletion layer is required. Due to the constraints, it is not only difficult to achieve sufficiently large capacitance and dielectric strength in a small area, but also because it is necessary to apply a reverse bias voltage, as in the second example, the inversion layer and depletion The electrode for the purpose of generating a layer (it seems to have various names, but the
In the specification of No. 51-130118, it is called a capacitive electrode. ), the selection of positive and negative voltages must be limited, and it is necessary to secure a depletion layer region around the trench, which requires a large surface area for isolation between elements. It cannot escape the drawbacks listed in .

(b) When forming a groove in the semiconductor layer 11, it is inevitable that some crystal defects will occur in the semiconductor substrate near the groove. Therefore, when a depletion layer or a depletion layer and an inversion layer are used, the charge storage electrode of the capacitor (in the case shown in FIG. 5, it is the n-type region 12, and in the case shown in FIG. 6, it is the inversion layer 24n). .)
It is difficult to avoid electric charge leaking from the DRAM, which shortens the refresh period and makes it extremely difficult to manufacture a large-capacity DRAM.

(b) Since a depletion layer is used, there is a risk that the amount of accumulated charge stored in the charge storage electrode will increase or decrease due to carriers generated in the semiconductor substrate when alpha rays invade, resulting in soft errors. It's easy to do.

As described above, the 1-transistor/1-capacitor type semiconductor memory device with the vertical buried structure that utilizes a depletion layer is not necessarily satisfactory;
However, there is still room for improvement. Therefore,
A capacitor with a large degree of freedom and a high degree of integration, high reliability, resistance to alpha rays, large capacitance, and large dielectric strength is used, and by using such a capacitor, a long refresh time is achieved. It has been desired to develop a 1-transistor/1-capacitor type semiconductor memory device that has a high resistance to alpha rays.

An object of the present invention is to meet this demand, and to provide a 1-transistor having a vertical buried capacitor configured with a dielectric layer and two dielectric layers sandwiching this dielectric layer. - 1- To provide a capacitor type semiconductor memory device and its manufacturing method.

[Means to solve the problem]

Among the above objects, the first object is to provide a 1-transistor/1-capacitor type semiconductor memory element, in which the capacitor is connected to a counter electrode (or a common counter electrode when the semiconductor memory element has a plurality of semiconductor memory elements). 1 conductivity type semiconductor layer 1
1 and a semiconductor oxide, semiconductor nitride, etc., such as silicon oxide, etc., which is formed on the inner wall of the groove drilled in this 1 conductivity type semiconductor layer 11 and forms a capacitor insulating layer.
A dielectric layer 17 made of silicon nitride, and a conductive layer formed on the dielectric layer 17, insulated from the semiconductor layer of one conductivity type, connected to the source or drain region of the transistor, and forming a charge storage electrode. This is achieved by a semiconductor memory device which is a vertical buried capacitor consisting of a body layer 18.

In order to obtain a large value of capacitance, (a) it is desirable that the thickness of the dielectric layer 17, ie, the layer 17 of semiconductor oxide, semiconductor nitride, etc., be as thin as the dielectric strength allows. Note that if the surge voltage that a semiconductor device receives is about 10V, theoretically a thickness of about 250 Å for the dielectric layer, typically a silicon oxide layer, should be sufficient, but if it is less than 250 Å, the dielectric strength will be insufficient. It has been experimentally confirmed that it is stable, so
Values of 500 Å or more are often chosen.

Among the above purposes, there is a step of forming an opposite conductivity type semiconductor region to become a source or drain of a transistor in a semiconductor layer of one conductivity type, and a step of etching the semiconductor layer of the first conductivity type using a vertical ion beam etching method. forming a groove-like opening in the semiconductor layer 11 of one conductivity type from the surface of the layer 11, and extending over an inner wall of the opening and at least a capacitor formation region on the surface of the semiconductor layer 11 of one conductivity type; forming a dielectric layer 17; and extending the dielectric layer 17 over the inner wall of the opening and the capacitor formation region on the surface of the one conductivity type semiconductor layer 11 and the opposite conductivity type semiconductor region. 1-Transistor 1-
This is achieved by a method for manufacturing a capacitor type semiconductor memory element.

In other words, vertical ion beam etching with high current density and high acceleration energy is used to form a vertical buried capacitor, which is one component of a 1-transistor/1-capacitor type semiconductor memory element. Then, from the surface of the semiconductor layer 11 into the semiconductor layer 11, a layer having a narrow width, for example, about 5 μm, and a deep depth, for example, 5 μm.
After that, the mask used in this etching step is removed, and the surface of the semiconductor substrate 11 is then thermally oxidized, and the formed oxide film is then etched. After cleaning the surface of the opening and at least the area where the capacitor is to be formed on the surface of the semiconductor layer 11 by removing foreign substances by etching with an acid (HF) cleaning solution, the semiconductor substrate 11 is oxidized again. Alternatively, by using a method such as nitriding, a dielectric film made of a semiconductor oxide film or a semiconductor nitride film, for example, a layer of silicon oxide or silicon nitride, is formed on the surface of the opening and at least the region where a capacitor is to be formed on the surface of the semiconductor layer 11. body layer 17 of at least 250 Å
A thin layer made of a conductor such as nickel (Ni) is formed on the dielectric layer 17 using an electroless plating method, and then a thin layer made of a conductor such as nickel (Ni) is formed on the dielectric layer 17 to a thickness of In addition, a layer 18 made of a conductor such as aluminum (Al) is formed, and the layer 18 made of the conductor constitutes a charge storage electrode of the capacitor, and the counter electrode is constituted by the semiconductor substrate 11. This is achieved by a method of manufacturing a 1-transistor/1-capacitor type semiconductor memory element having the following.

Here, the ion beam etching method with high acceleration energy can be used with an energy of about 1 to 10 KeV and an inert gas such as argon (Ar), or chlorine (Cl ₂ ), fluorine ( It is also possible to use reactive ion source materials such as F ₂ ) and carbon tetrafluoride (CF ₄ ) with an acceleration energy of about 500 eV. The mask used here is
A sapphire or metal mask is effective for etching using argon (Ar), and a mask made of semiconductor oxide or the like is effective for etching using a reactive substance. A cleaning step after opening is desirable to obtain high dielectric strength and large capacitance with thin dielectric layers.
In addition, the electroless plating process for nickel (Ni) etc.
This is suitable as a process for forming a conductive layer on a dielectric groove that is narrow in width and is electrically nonconductive.

[Effect]

The present invention utilizes the property that a vertical ion beam etching method with high current density and high acceleration energy can form a narrow and deep groove-like opening in a semiconductor layer. A 1-transistor/1-capacitor type semiconductor memory device having a vertical buried capacitor configured with a dielectric layer and two conductive layers sandwiching the dielectric layer can be easily manufactured. This was completed after experimentally confirming that this was the case, and the experimental results showed that the dielectric layer, which has the expected high focusing accuracy and a large degree of freedom in design, and the dielectric layer sandwiched between The vertical embedded capacitor is constructed with two dielectric layers formed by the above method, has a high degree of integration, has low charge leakage, has a long refresh time, is highly reliable, and has high resistance to alpha rays. A 1-transistor/1-capacitor type semiconductor memory device was realized.

〔Example〕

Hereinafter, with reference to the drawings, a vertical embedded capacitor according to an embodiment of the present invention is constructed with a dielectric layer and two dielectric layers formed by sandwiching the dielectric layer. -Transistor 1- Manufacturing process of a vertical buried capacitor, which is an essential component of a capacitor type semiconductor memory device, and is composed of a dielectric layer and two dielectric layers formed by sandwiching this dielectric layer. and a 1-transistor 1 which uses this capacitor and has a vertical buried capacitor composed of a dielectric layer and two dielectric layers formed by sandwiching this dielectric layer.
- The manufacturing process of a capacitor type semiconductor memory device will be explained.

Manufacturing process of a vertical buried capacitor consisting of a dielectric layer and two conductive layers sandwiching this dielectric layer.See Figure 1. A thin layer of silicon oxide with a thickness of about 4 μm is formed using a growth method or the like, and a mask 2 having an opening in the opening formation region is formed using a normal lithography method. Using this mask 2, use carbon tetrafluoride (CF ₄ ) containing chlorine (Cl ₂ ) as a reactive ion source material with an acceleration energy of about 500 eV at 1 mA/
Vertical ion beam etching is performed with a current density of approximately cm ² to form an opening 3. At this time, the silicon oxide film used as mask 2 is also etched at a rate of approximately one-half of the etching rate for silicon.

See Figure 2 After removing the mask used in the above etching process using a hydrofluoric acid (HF)-based solution, it is thermally oxidized, and the formed silicon oxide film is immersed in a hydrofluoric acid (HF)-based solution. By etching the inner wall surface of the opening 3 and the silicon (Si) substrate 1,
After removing unexpected foreign substances from the surface of the silicon (Si) substrate 1, the silicon (Si) substrate 1 is oxidized again by a method such as exposing it to oxygen (O ₂ ) at about 1000° C. for 40 minutes, or by plasma vapor deposition, etc. For example, by depositing a nitride film, the above opening 3 is
A dielectric layer 4 is formed on the inner wall surface of the silicon (Si) substrate 1 and on the surface of the silicon (Si) substrate 1.

Refer to FIG. 3 Next, the area other than the area where the capacitor is to be formed is covered with a resist, and a layer 5 of nickel (Ni) or the like is formed using an electroless plating method. Here, the reason for using the electroless plating method is that metal deposition, that is, plating, can proceed without applying a special external electrification potential to the dielectric layer and resist, which are electrically nonconducting. This is because it can be done.

Then, the thin layer 5 of the above-mentioned nickel (Ni) etc.
is used as an electrode, and a layer 6 of aluminum (Al) or the like is formed thereon by electrolytic plating.

Next, a resist is applied to the surface, openings are formed using a normal lithography method, and unnecessary metal layers 5 and 6 are removed using, for example, a phosphoric acid (H ₃ PO ₄ )-based etching solution. All of the resist is removed by oxygen (O ₂ ) plasma ashing.

Here, a capacitor is formed with the dielectric layer 4 in between and using the metal layers 5 and 6 and the silicon (Si) substrate 1 as respective electrodes.

Manufacturing process of a 1-transistor/1-capacitor type semiconductor memory device having a vertical buried capacitor composed of a dielectric layer and two conductive layers formed by sandwiching the dielectric layer.See FIG. 4. 1-1, which has a vertical embedded capacitor configured with a dielectric layer and two dielectric layers formed by sandwiching the dielectric layer, according to an embodiment of the present invention;
FIG. 4 shows an example of a cross-sectional view of a semiconductor memory element made of a transistor/1-capacitor type semiconductor memory device.

In the figure, 11 is, for example, a p-type silicon (Si) substrate, and 12 is, for example, an n-type source substrate.
13 is a gate insulating film, 14 is a gate electrode, which constitutes a word line in this example and extends in a direction perpendicular to the plane of the paper;
Reference numeral 5 denotes an aluminum (Al) electrode for the drain, which constitutes a bit line in this example and extends horizontally in a direction parallel to the plane of the drawing, and 16 a gate electrode 14 which forms a word line and a source electrode 1 which forms a bit line.
This is a so-called interlayer insulator between the 5 and 5 layers. 17 is a dielectric material of the capacitor according to the gist of the present invention, specifically, the silicon oxide film/silicon nitride film 4 shown in FIG. 3, and 18 is a common counter electrode of the capacitor according to the gist of the present invention. Specifically, the metal layers 5 and 6 shown in FIG. 3 are connected to the source region 12 of the field effect transistor.
The charge storage electrode is a silicon (Si) substrate 11.
As is clear from the figure, when a certain capacitance is given, the area of the semiconductor substrate 11 occupied by the capacitor is as follows. A configuration using a depletion layer generated between a reverse-biased p-n junction, which is relatively much less than that in , is not used. The charge storage 18 of the capacitor connected to the drain region 12 of the field effect transistor is a conductive layer extending on the dielectric 17, and does not utilize an inversion layer and a depletion layer as in the prior art. , it is easy to electrically isolate adjacent memory elements, and there is a large degree of freedom in design.
Suitable for high integration density due to close arrangement of elements.

〔Effect of the invention〕

As explained above, in the semiconductor memory element according to the present invention, one field effect transistor is used as a driver, and as an information storage means, a field effect transistor is formed between a dielectric layer and a field effect transistor sandwiching the dielectric layer. A single vertical buried structure capacitor is used, which is composed of two conductor layers, with a semiconductor layer made of a substrate serving as a common counter electrode, and a dielectric layer interposed between the capacitor and the semiconductor layer. The conductive layer that is completely and permanently insulated from the driver transistor and connected to the source or drain of the driver transistor is used as a charge storage electrode, and unlike the conventional vertical buried capacitor that uses a depletion layer,
Since the common electrode and charge storage electrode do not coexist in the substrate with a depletion layer in between, it is possible to achieve a high degree of integration, large capacitance, and large dielectric strength. , it has a high degree of integration, and there is no need for large distances between elements for element separation, so from this point of view as well, it has high integration accuracy.
Even if some crystal defects occur in the semiconductor substrate during groove formation, this will not generate leakage current, and therefore the refresh period will not be shortened, and leakage current will not occur due to the penetration of alpha rays. There is no adverse effect due to the carrier, and in short, all the disadvantages inherent in the conventional vertical buried capacitor using a depletion layer are eliminated, and the degree of freedom in design is increased. Furthermore, since the charge storage electrode does not exist in the semiconductor layer (substrate), it is possible to add another electrode via another insulating film on the charge storage electrode, which is a component of the present invention. In this way, the capacity can be easily doubled. In the conventional vertical buried capacitor using a depletion layer, since the charge storage electrode exists in the semiconductor layer (substrate), it is completely impossible to increase the capacitance in this way. .

In addition, in the method for manufacturing a semiconductor memory element according to the present invention, a vertical ion beam etching method with high current density and high acceleration energy is used to form a narrow width, for example, about 5 μm, into the semiconductor layer. forming a groove-like opening having a width and a deep depth, for example, about 5 μm, then cleaning the surface of the semiconductor layer, and forming a dielectric layer on this semiconductor substrate; Next, a conductive thin layer is formed on the dielectric layer using electroless plating, which is suitable as a process for forming a dielectric layer on an electrically nonconducting dielectric layer. A conductor layer is further formed on the thin conductor layer, and this conductor layer constitutes one electrode of the capacitor, and the other electrode is constituted by a semiconductor substrate. , it is possible to achieve large capacitance and large dielectric strength with high integration, and there is no need for large distances between elements for element isolation, and for the same reason, design The upper degree of freedom also increases.

In this way, a 1-transistor/1-capacitor type semiconductor memory device having a vertical buried capacitor constituted by a dielectric layer and two dielectric layers formed with the dielectric layer sandwiched therebetween, and its manufacture. A method was provided.

[Brief explanation of drawings]

FIGS. 1, 2, and 3 show a vertical buried structure having a dielectric layer and two conductive layers sandwiching this dielectric layer, according to an embodiment of the present invention. 1-transistor with capacitor 1-
FIG. 2 is a cross-sectional view of a substrate after the main steps of a method for manufacturing a vertical buried capacitor essential to a capacitor type semiconductor memory device. FIG. 4 shows a 1-transistor having a vertical buried capacitor configured with a dielectric layer and two conductive layers sandwiching the dielectric layer, according to an embodiment of the present invention. - It is a sectional view of a capacitor type semiconductor memory device. Fifth
FIG. 6 is a sectional view of a 1-transistor/1-capacitor type semiconductor memory device according to the prior art, which uses a depletion layer generated between a pn junction to which a reverse bias is applied. 1, 11... Semiconductor substrate, 2... Mask, 3, 19
...opening, 4, 17... dielectric layer, 5, 6, 18... conductor layer (one electrode), 12... source/drain region/drain extension region, 13... gate insulating film,
14... Gate electrode (word line), 15... Drain electrode (bit line), 16... Interlayer insulator, 20... Insulating film, 21... Semiconductor layer, 22... Depletion layer, 23... Electrode (capacitance electrode), 24... Inversion layer.

Claims (1)

[Scope of Claims] 1. In a 1-transistor/1-capacitor type semiconductor memory element, the capacitor includes a 1-conductivity type semiconductor layer 11 forming a counter electrode, and a 1-conductivity type semiconductor layer 11 bored through the 1-conductivity type semiconductor layer 11. A dielectric layer 17 is formed on the inner wall of the trench and serves as a capacitor insulating layer, and a dielectric layer 17 is formed on the dielectric layer 17 and is insulated from the semiconductor layer of the first conductivity type, and is connected to the source or drain region of the transistor and conducts charge. This is a vertical buried capacitor consisting of a conductor layer 18 forming a storage electrode. A semiconductor memory element characterized by: 2. A step of forming an opposite conductivity type semiconductor region 12 to serve as a source or drain of a transistor in the first conductivity type semiconductor layer 11, and etching the surface of the first conductivity type semiconductor layer 11 using a vertical ion beam etching method. forming a groove-shaped opening in the semiconductor layer 11 of the first conductivity type; and an inner wall of the opening and the semiconductor layer 11 of the first conductivity type.
a step of forming a dielectric layer 17 extending over at least the capacitor formation region on the surface of the opening and the inner wall of the opening and the first conductivity type semiconductor layer 11;
The dielectric layer 1 on the capacitor formation region on the surface of
7 and a step of forming a conductor layer 18 extending over the opposite conductivity type semiconductor region, 1-Transistor 1
- A method for manufacturing a capacitor type semiconductor memory element. 3. The semiconductor memory element according to claim 1, wherein the material of the dielectric layer 17 is a material containing silicon oxide or silicon nitride. 4. The method of manufacturing a semiconductor memory element according to claim 2, wherein the material of the dielectric layer 17 is a material containing silicon oxide or silicon nitride.