JPH043708B2 - - Google Patents

Description

[Detailed description of the invention]

[Field of Application of the Invention] The present invention relates to a control device for thermal recording, which is widely used in facsimile machines, etc., and particularly to a black pixel adaptive high-speed recording suitable for all-driver type recording heads that have driver circuits in all heating elements. The present invention relates to a control device for realizing the invention. [Prior art] As a means of achieving higher speed and lower cost thermal recording, a method (driver-mounted head) in which a driver chip with a built-in shift register is mounted on a substrate that forms a heating resistor is becoming mainstream. be. An example of a head configuration using this type of system is disclosed in Japanese Patent Application Laid-Open No. 56-69186 ``Thermal Recording Head'' and 1983.
This is described in the paper ``Thermal head for high-speed thermal recording'' (pages 169-172) presented at the 2017 Image Engineering Conference. In other words, it is basically based on a driver chip consisting of a shift register, latch register, and output driver, and some functions are added to this to simplify the head board wiring and increase the recording speed. . FIG. 1 is a diagram showing the basic configuration of a conventional head driver chip. In this figure, 100 is a shift register, 200 is a latch register, and 300 is an output driver, and the circuit is constructed by combining n sets (generally, n=8 to 32) of these.
The shift register 100 also has a serial data input terminal SI connected to the signal line 110, and a signal line 13 connected to the serial data input terminal SI.
0, a data transfer clock input terminal CP connected to a signal line 120, and a group of parallel data output terminals Q0 to Qn connected to a signal line 140. 100 parallel data output terminals Q0 to Qn are inputs D0 to Dn,
It has a latch strobe terminal T connected to a signal line 210. Furthermore, the latch resistor 200
The outputs of the output terminal group Q0 to Qn become the inputs I1 to In of the output driver 300 via the signal line 220, and the corresponding drive circuits are connected to the signal line 31.
It is driven when the AND condition with the output enable terminal E connected to O1 is established, and the output terminal group O1~
The On output energizes the corresponding output line via the signal line 320. Using such driver chips, it is possible to configure a head equipped with a driver, but in order to further increase the recording speed and reduce the power supply capacity, it is possible to perform recording control that adapts to the number of black pixels, and even when recording is not being performed. When attempting to implement heat pulse control to maintain head temperature, the following problems arise. In other words, the method of giving a drive permission signal to the driver chip according to the number of black pixels is so complicated that it is virtually impossible to do so.If you try to simplify the control, the wiring pattern on the board becomes complicated, which increases the cost of the head. For example, this function cannot be incorporated because there is no consideration given to the application of heat pulses. In order to provide a drive evaluation signal to the driver chips according to the number of black pixels, it is necessary to control the output enable terminals 310 of each chip.
Assuming a B4 size head with 32 dots/chip, 64 driver chips 300 are required, and at the same time prepare wiring patterns for 64 enable signal lines.
A circuit is required to determine which combination of the 64 chips should be driven. A JIS standard B4 size driver-equipped head that does not take into account black pixel adaptive recording (the above 64 wiring patterns are unnecessary) can be realized with a length of about 300 mm x width of 30 mm, but if you pass 64 wiring patterns through this, it will be 2. Even if patterning is done at 1/mm, a width of 32 mm is required.
More than double the head area is required. (In other words, the head cost almost doubles.) Furthermore, multi-core connection cables and connectors to the drive determination circuit are required, which not only poses a problem in terms of cost, but also in terms of the reliability of the connection points.
Practical implementation is close to impossible. Furthermore, the drive determination circuit requires approximately 20 logic ICs (for example, as shown in FIG. 9 of Japanese Unexamined Patent Publication No. 56-69186), which is also problematic in terms of hardware quantity. Furthermore, adding heat pulse control for preheating would further complicate the logic and require additional hardware. [Object of the Invention] An object of the present invention is to provide a thermal recording control device equipped with a head driver chip suitable for realizing a thermal recording control system suitable for black pixel adaptive recording. [Summary of the Invention] The present invention provides a driver selection function necessary for black pixel adaptive recording that records black pixels at the same time until the power supply capacity is limited, and a driver selection function that prevents the head temperature from dropping too much when there are no recording pixels. A function for selecting a heat pulse application driver for control is built into the driver chip. That is, a register set from the outside for the block number recorded in the driver chip, a counter for counting the block switching timing (i.e., recording pulse), and a matching circuit for detecting the match between the set value and the count value are provided, and a match circuit is provided to detect the match between the set value and the count value. When this happens, recording pulses are applied to the heat generating resistors through the respective drivers. [Embodiment of the Invention] FIG. 2 is a block diagram showing an embodiment of the driver chip according to the present invention, and shows a shift register 10.
0, latch register 200, output driver 30
0', an input/output control circuit 400, a block shift register 500, and a recording control circuit 600. The input/output control circuit 400 includes operation mode designation input terminals M0 and M1 connected to a signal line 410, a serial data input terminal SI1 connected to a signal line 110', a serial data output terminal SO1 connected to a signal line 130', Data transfer clock input terminal CP and signal line 21 connected to signal line 120'
Latch strobe input terminal STB connected to 0'
terminals CP1, SO2, SI3, which are connected to the signal line 420 with the shift register 100;
Terminal T1 connected to signal line 430 with latch register 200, terminal T2 and RST connected to signal line 440 with recording control circuit, terminal CP2 connected to signal lines 510 and 520 with block shift register 500, It has SI2. Also,
The recording control circuit 600 has a signal line 63 in addition to an output enable terminal WCP connected to the signal line 310'.
The heat pulse input terminal HCP is connected to the block shift register 50 via the signal line 530.
Input terminals D0 to D7 are connected to block number designation outputs Q0 to Q7 of 0, terminals WE and WH are connected to drive signal terminals E1 and E2 of the output driver 300' via signal line 620, and input/output control circuit 4.
It has terminals T2, RST connected to terminals T2, RST of 00 via a signal line 440. (In the above description, the same reference numerals as in FIG. 1 have the same functions.) In the following operation description, the same reference numerals are used for terminals and signals at the terminals. The input/output control circuit 400 determines how the data input from the serial data input terminal SI1 is input to the shift register 100 and the block shift register 500 according to the specification signals input to the operation mode specification input terminals M0 and M1, and how the data input from the serial data input terminal SI1 is input to the shift register 100 and the block shift register 500. 10
It controls which of the outputs 0 and 500 is output to the serial data output terminal SI1, and also outputs the latch signal T1 to the latch register 200 and the signals T2 and RST to the recording control circuit 600.

〔Effect of the invention〕

As explained above, according to the present invention, black pixel adaptive recording can be easily realized by adding simple hardware, and the recording speed can be improved (10 to 20 times faster than the normal fixed block recording method). ) and recording power capacity can be reduced. Further, even if a plurality of driver chips are mounted on the recording head, the wiring pattern is simple, and the driver-mounted head can be realized at a high yield and at low cost. Furthermore, the driver chip and recording interface control circuit of the present invention are versatile and can be widely applied to facsimile machines, printers, etc., so they are expected to be effective in mass production and are suitable for LSI implementation.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a conventional driver chip, FIG. 2 is a block diagram showing an embodiment of the driver chip according to the present invention, FIGS. 3 to 6 are diagrams showing data flow according to transfer mode, and FIG. FIG. 7 is a diagram showing the format of block designation data, FIGS. 8 to 10 are more detailed block diagrams of the configuration means of the present invention, and FIG. 11 is an embodiment of a system suitable for applying the present invention. The block diagram shown in Figure 12 is a detailed diagram of a part of it, and Figure 13 is the MPU.
FIG. 14 is a flowchart showing the operation of the data memory format shown in another embodiment.
Figures a and b are time charts showing an example of the operation of one scanning line of black pixel adaptive recording according to the present invention. 100...Shift register, 200...Latch register, 300'...Output driver, 600...
... Recording control circuit, 601... Recording block designation register, 602... Recording block counter, 60
3... Recording block judgment circuit.

Claims (1)

[Claims] 1. A thermal recording device that controls and records the current flowing to a heating resistor, in which a driver chip based on a shift register, a latch register, and a driver circuit for controlling the presence or absence of the energization is the same as the heating resistor. In a thermal recording control device configured to be mounted on a substrate or an adjacent substrate, the driver chip includes a register for specifying a recording block number, a block counter for counting the correspondence with the recording block number, and a register for checking the correspondence between the contents of the two. 1. A thermal recording control device, comprising a built-in coincidence detection circuit for detecting a coincidence, and when the two coincide, a recording pulse is applied to a heating resistor through a corresponding driver.