JPH0437070A - Semiconductor device - Google Patents

Abstract

PURPOSE:To augment the fluctuation rate of capacitance corresponding to the fluctuation in the backward bias voltage by a method wherein a MOS transistor whereon a drain electrode is provided on the rear side region opposing to a gate electrode on a semiconductor substrate is composed of a variable capacitance diode. CONSTITUTION:A depletion layer 20 is formed on the PN junction between an epitaxially grown layer 13 and impurity regions 14 in a semiconductor substrate 11 by impressing the region between an anode electrode 19 and cathode electrodes 16 with a backward bias voltage. The depletion layer 20 is expanded in the epitaxially grown layer 13 from the broken lines a to b from the PN junction surface to the outside of the region encircled by the impurity regions 14 as the backward bias voltage is boosted. Next, at the time point or later when the backward bias voltage reaches the specified value, the depletion layers 20 expanding inward are joined together as shown by the broken line C so that the capacitance in the region between the anode electrode 19 and a gate 17 may be abruptly fluctuated to be decreased. Through these procedures, the fluctuation in the capacitance DELTAC can be augmented.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and more particularly to a semiconductor device in which a MOS transistor is a variable capacitance diode.

[Conventional technology]

Conventionally, variable capacitance diodes widely used in TV set tuners and the like generally have a PN junction structure as shown in FIG. This variable capacitance diode is
A low concentration of N is placed on a high concentration of N+ type suspension stray L-(1).
A low concentration P- type impurity such as boron is diffused into a semiconductor substrate (3) made of silicon or the like on which a - type epitaxial growth layer (2) is laminated to form an impurity region (4). A cathode electrode (
5) and an anode electrode (6) on the back surface of the semiconductor substrate (3) facing the cathode electrode (5).
It is formed by depositing.

In the above variable capacitance diode, by applying a reverse bias voltage between the anode electrode (6) and the cathode electrode (5), the epitaxial growth layer (2) and the impurity region (4) are separated.
A depletion layer (7) is formed at the PN junction surface between them. This depletion layer (7) is an insulating region, and its thickness corresponds to the thickness of the dielectric of the capacitor. The above anode electrode (
6) and the cathode electrode (5) c: By increasing or decreasing the applied reverse bias voltage, the depletion lit (7)
As the thickness increases and decreases, the number of containers increases accordingly.

[Problem to be solved by the invention]

By the way, in the tt* variable 8-bar diode described above, the change U of the reverse bias voltage applied between the anode electrode (6) and the power electrode (5) is followed by the depletion N (7).
Since the thickness of N and L does not increase or decrease monotonically, it changes to -A when the reverse bias voltage changes. That is, the 4th section 4U of the above-mentioned reverse bias heavy pressure.

On the other hand, the rate of change in capacitance is relatively small, so you can obtain the desired variable range of capacitance! In this case, there was a problem in that the adjustment range of the reverse bias voltage had to be widened.

Therefore, the present invention has been developed in consideration of the above-mentioned problems, and the object thereof is to provide a semiconductor device which can obtain a rate of change in capacity of 1.7 with respect to a change in reverse bias voltage. It is in.

[Means to solve the problem]

Technical 45 to achieve the above purpose in invention J
In step 7, an impurity 1 of a different conductivity type is diffused into the semiconductor substrate 71 and a source electrode ξ1 is formed on its surface U'. 3. In both cases, the impurity region of the other conductivity type (the exposed surface area of the sandwiched semiconductor substrate) is
A gate electrode 1 of the semiconductor substrate is provided.
Drain electrodes are placed in the opposite regions @lI direction: M
(3S tranny) 2 stars, drain and source electrode M
``''e (!') fi, due to the expanding state of the depletion layer based on the application of the Asumi pressure, l' i, , -in Ga.
The capacitance that varies between the two electrodes is variable.
・-

[Effect]

Il, 1'1, MO31 in the ¥-conductor device according to the present invention
drain, in, and source electrodes of the run source respectively)°ノ・
A variable capacitance diode is used as a cathode electrode and a cathode electrode. Configure and.

By applying a reverse bias voltage between the γ nor )'' and cathode electrodes, a depletion layer is formed at the PN junction surface, and by increasing the reverse bias voltage, the state of expansion of the depletion layer changes2, and based on this, the anode and The capacitance changes between the gate electrode and the gate electrode.At this time, there is a state in which the spread of the depletion layer in the semiconductor substrate between the anode and gate electrode changes rapidly, resulting in the formation of a reverse barrier bias. 1 for small changes in pressure
．． -The largest rate of change in ζ volume can be obtained.

〔Example〕

FIGS. 1 to 3 show the -.
This will be explained with reference to the figures.

In the semiconductor device Q shown in FIGS. 1 and 2, (11
) is an N-type semiconductor substrate made of silicon, etc., with a high concentration of N'' type support!/- (12), and a low concentration of N
− type epitaxial growth M (13) f product Ii is formed. (14) is 4k fi l1f on the evitaxial growth M (13) of the semiconductor substrate (11) mentioned above.
P formed by diffusing P-type impurities such as f
In the ' type impurity l$A region, a high concentration of P type impurity is diffused into this impurity region (Step 4) to form two P'' type electrode extraction layers (1).
(5) is formed. (16) is the above electrode drawer! ,,N(
15) So--Sumi electrodes such as A1 deposited on J=, serve as cathode' electrodes in variable displacement diodes.

(1, 7) is a region where the epitaxial growth layer (13) of the semiconductor substrate (11) sandwiched between the impurity regions (14) is exposed at a high speed.
... 2 (adhesive formation, via oxidation if (18)
Gelt electrode for AI, etc., (19) is a semiconductor substrate (]1)
Upper & H5 gate/electrode (17) and area opposite @ back side C
A drain electrode is deposited and forms a 7-node electrode in a variable displacement diode. In addition, in the following explanation, "4" and "7"
Sauce, 1. The twin electrodes (16) and (19) are referred to as cathode and anode electrodes, and the feature of the present invention is that the MOS transistor having the structure described in 1. Due to the expansion state of the depletion layer (described later) based on the voltage application, the anode)' gate electrode (step 9) (11')
) is a variable capacitance diode with a capacitance that changes.

To explain in terms of scissors 4, by applying a reverse bias voltage between the anode electrode (19) and the quad electrode (16), the semiconductor substrate (step 1) is Among them, I”N between the J bitaxial H layer (13) and the impurity region (14)
A depletion layer (20) is formed at the junction surface. Gono depletion m (
20) &;! :! ＠rim＠area tear, ``r/-V electrode (
The depletion layer (2) between the bridge (17) and the bridge (17)
The thickness of 0) corresponds to the thickness of the dielectric of the capacitor, and a capacitor is formed. As the reverse bias voltage applied between the anode electrode (19) and the cathode electrode (16) is increased, the depletion layer (20) grows epitaxially from the PN junction surface to the outside of the region surrounded by the impurity region (14). In the layer (13), the depletion layer (20) expands from dashed line a to b in the diagram, and after the reverse bias voltage reaches a predetermined value, the depletion layer (20) expands inward as shown by dashed line C in the diagram. At this time, as shown in FIG. 3, the capacitance between the anode electrode (19) and the gate electrode (17) suddenly changes and decreases. In this way, for a small change ΔV in reverse bias voltage, the above capacitance change ΔC
You can get a large amount. Since a large rate of change in capacitance can be obtained as described above, it is easy to set the capacitance over a wide range with a small adjustment range of reverse bias voltage, making it suitable for use in electronic chainers for television cameras, resonant switching power supplies, etc. .

Briefly, the above semiconductor device has a structure in which a MOS transistor is a variable capacitance diode, whereas a normal MOS transistor structure has a gate capacitance COC between the drain and gate electrodes and a gate capacitance CGs between the source and gate electrodes. , in the semiconductor device of the present invention, the gate electrode (17)
and an epitaxially grown layer (13) of a semiconductor substrate (IL) in which a gate oxide film (18) is surrounded by an impurity region (14).
) is deposited only on the surface of the exposed region, the gate capacitance CGs between the source and gate electrodes mentioned above is made as small as possible to the extent that it can be ignored, and the anode and gate electrodes (
19) Only the capacity between (17) is considered.

〔Effect of the invention〕

According to the semiconductor device of the present invention, by using a variable capacitance diode as a MOS transistor, the rate of change in capacitance with respect to a change in reverse bias voltage can be increased, so that a wide range of capacitance settings can be achieved with a small adjustment range of reverse bias voltage. This makes it possible to provide semiconductor devices with excellent versatility and great practical value.

[Brief Description of the Drawings] Fig. 1 is a schematic cross-sectional view showing an embodiment of a semiconductor device according to the present invention, Fig. 2 is a reduced plan view of Fig. 1, and Fig. 3 is a characteristic of capacitance with respect to reverse bias voltage. It is a diagram. FIG. 4 is a schematic cross-sectional view showing a conventional example of a variable capacitance diode. (11)...-m=conductive type semiconductor substrate, (14) -11 other conductive type impurity region, (16) -source electrode,
(17) - gate electrode, (18) - gate oxide film,
(19) - Drain electrode, (20) - Depletion layer. Figure 3

Claims (1)

[Claims] (1) Impurities of one conductivity type are diffused into a semiconductor substrate of another conductivity type, a source electrode is provided on the surface thereof, and a gate oxide film is provided on the surface of the exposed region of the semiconductor substrate sandwiched between the impurity regions of the other conductivity type. A MOS transistor having a gate electrode and a drain electrode provided on the back surface of the region facing the gate electrode of the semiconductor substrate is connected to the drain and gate electrodes by the spread state of the depletion layer based on the application of a reverse bias voltage between the drain and source electrodes. A semiconductor device characterized in that it is a variable capacitance diode having a capacitance that changes with.