JPH04365288A - Method for sampling video signal - Google Patents

Abstract

PURPOSE:To prevent color display from being defective by making close timing for changing a sampling pulse from high to low for the same display unit generated in a video signal driving circuit. CONSTITUTION:The cycle of sampling clocks phi1 and phi2 is regularly changed with ts1-ts3 as one cycle and for the cycle ts1-ts3, the dot cycle of the video signal has the fixed relation with tvo as well. Between the sampling clocks phi1 and phi2, there is phase difference corresponding to the dot cycle tvo of the video signal. Start pulses ST1 and ST2 are set corresponding to the start edges of the correspondent sampling clocks phi1 and phi2. Therefore, the timing to change the sampling pulse from high to low (to close a sampling gate) is made close at sampling pulses Q11, Q21 and Q12 corresponding to picture elements R1, G1 and B1.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] This invention provides sample points for red, green, and blue (hereinafter referred to as R, G, B) video signals in the same display unit when serially sampling video signals of a color display device. The present invention relates to a method of sampling a video signal in such a way that the signals can be brought closer to each other.

0002

2. Description of the Related Art Conventionally, a color display device is generally composed of a plurality of R, G, and B pixels.
For example, a serial sample video signal drive circuit as shown in FIG. 3 is used to input a predetermined voltage level to the B pixel.

This serial sample video signal drive circuit 1
0 drives the color display 20, and includes a sampling pulse generator 11 consisting of a shift register, and sample hold circuits (hereinafter referred to as S/H circuits) 121 to 1.
25, and output buffers 131-135.

This sampling pulse generator 11 is controlled by a start pulse ST and a sampling clock φ, and outputs sampling pulses Q1 to Q5 to S/H circuits 121 to 121.
125.

Further, the S/H circuits 121 to 125 sample and hold the red, green, and blue video signals VR, VG, and VB in synchronization with the respective sampling pulses Q1 to Q5. The sampled and held signals are output to the output terminals D1 to D1 of the output buffers 131 to 135 in synchronization with the output enable signal OE.
It is output to D5.

[0006] Such serial sample video signal drive circuits 10 are connected in two rows, upper and lower, to form a color display 20.
FIG. 4 shows a configuration diagram when driving a liquid crystal display (LCD) 30. The pixel arrangement of the LCD in this case is an RGB stripe arrangement, where R, G, and B mean red, green, and blue pixels, respectively. Even if the pixel arrangement is in another arrangement such as a mosaic arrangement, it can be driven using the same principle.

[0007] Also, the video signal lines X11 to X15 of the LCD
, X21 to X25 are connected to every other serial sample video signal drive circuit 10a, 10b in the upper and lower two columns. The scanning signal line Y is connected to a scanning signal drive circuit 40.

FIG. 5 is a timing diagram for explaining a conventional sampling method in an LCD system connected as shown in FIG. Here, video signals VR, VG, V
B assumes a signal in which black and white display repeats every other line. However, this is the case in normally black mode (black display mode when no voltage is applied) and frame inversion drive.

When a display signal from a general computer is considered as a signal source, R, G, and B video signals are in phase with each other. Therefore, in this case, the video signal VR
, VG, and VB become the same signal.

Regarding the sampling pulse generator 11, a method is being considered in which the level of the sampling pulse changes at the rising timing of the sampling clock, as shown in FIGS. 5(a) and 5(b).

Next, the operation will be explained using FIG. 5. In the sampling pulse generation section of the serial sample video signal drive circuit 10a, the clock pulse φ1 shown in FIG. 5(a) and the start pulse ST1 shown in FIG. 5(b) are input, and the clock pulse φ1 shown in FIG. ) Sampling pulses Q11, Q12, . . . are output as shown in FIG.

Similarly, in the sampling pulse generation section of the serial sample video signal drive circuit 10b,
Sampling clock φ2 shown in FIG. 5(c), FIG. 5(d)
) is input, and the start pulse ST2 shown in FIG. 5(f) is input.
, as shown in FIG. 5(h), the sampling pulse Q21,
Q22... is output.

These sampling pulses Q11, Q1
2..., Q21, Q22... are at high level, S/
The sampling gates of the H circuits 121 to 125 are opened, and the video signals VR, VG, and VB are sampled as shown in FIG. 5(i).

Therefore, the actual output voltage level is the sampling pulse Q11, Q12..., Q21, Q2.
2... becomes the video signal VR, VG, VB level at the moment when it changes from high to low level (sampling gate closes). The levels are indicated by circles in FIGS. 5(i) and 5(j).

FIG. 5(i) shows an ideal video signal with a sufficiently high signal band. Therefore, in this case, FIG.
The voltage levels input to the R1, G1, B1, and R2 pixels are the video signals VR1, VG1, and V in FIG. 5(i), respectively.
It becomes B1, VR2.

Here, the sampling clock φ1 shown in FIG. 5(a) and the sampling clock φ2 shown in FIG. 5(b)
The following relationship exists between the period ts and the one-dot period tvo of the video signal shown in the lower part of FIG. 5(i). ts=2tvo/3...
...(1)

[0017]

[Problem to be Solved by the Invention] The number of horizontal color pixels of a display (one consisting of one pixel each of R, G, and B shown in FIG. 4)
When n is the number of display units s, assuming a signal close to a television signal, and assuming an effective horizontal scanning time of 50 μsec, tvo is: tvo=50/nμsec
......It is given by (2). For example, when n=320, tvo=156 nsec. When converted into frequency, this becomes fvo=6.4 MHz.

However, since the signal band of the IC circuit that processes normal liquid crystal drive signals is not very high, the video signals VR, VG, and VB input to the video signal circuit are as shown in FIG.
As in (j), it becomes so-called slang.

For this reason, R1, G1, B1, R2 in FIG.
The voltage levels input to the pixels are shown in Fig. 5(j), respectively.
The video signals VR1, VG1, VB1, VR2, . . .

In this way, as shown in FIG. 5(i), the video signals VR1, VG1, and VB1 must take the on (white display) level, and the video signal VR2 must take the off (black display) level. However, it takes a different level. Therefore, coloring occurs in black and white display.

In this case, since the level of the video signal VR1 has decreased and the level of the video signal VR2 has increased, white is colored light blue and black is colored red. The same holds true for sampling pulses corresponding to subsequent pixels, and coloring occurs in all black and white displays.

[0022] The above has described the problems that occur in the case of black and white display, but the difference in R, G, and B sample levels when inputting a high frequency signal as described above is generally caused by a color display defect when inputting a high frequency signal. This appears to be an issue.

[0023] Therefore, in order to solve this problem, the signal processing section must be constructed of discrete circuits with a high signal band. However, this results in an increase in system size and cost.

[0024] This invention was made to solve the above-mentioned problem, and even if a normal liquid crystal drive signal processing IC circuit whose signal band is not high enough is used, color display defects occur in high-frequency signals. The purpose is to obtain a method for sampling video signals that does not require

[0025]

[Means for Solving the Problems] A video signal sampling method according to the present invention involves regularly changing the period or duty ratio of a sampling clock and inputting the sampling signal to a plurality of serial sample video signal drive circuits of a color display. By giving the clocks a predetermined phase difference and setting the start pulse to correspond to the sampling clock, the timing at which the sampling pulses corresponding to three consecutive pixels change from high to low level can be brought closer together. .

[0026]

[Operation] In this invention, the sampling timing of three R, G, and B dots can be adjusted by regularly changing the period or duty ratio of the sampling clock to drive a plurality of serial sample video signal drive circuits of a color display. This works to suppress color display defects.

[0027]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the video signal sampling method of the present invention will be described with reference to the drawings. Figure 1 is Figure 4
FIG. 2 is a timing diagram for explaining an embodiment of the present invention in an LCD system connected as shown in FIG. Here, similarly to FIG. 5, it is assumed that the video signals VR, VG, and VB are signals in which black and white display is repeated every other signal.

This also applies to frame inversion driving in normally black mode (a mode in which black is displayed when no voltage is applied).

When a display signal from a general computer or the like is considered as a signal source, R, G, and B signals are in phase with each other. Therefore, in this case, the video signals VR, V
G and VB become the same signal.

Similarly to FIG. 5, the sampling pulse generating section shown in FIG.
As shown in FIGS. 1(e) to 1(h), we are considering a method of changing the level of the sampling pulse.

Next, the operation will be explained using FIG. In the sampling pulse generation section of the serial sample video signal drive circuit 10a (FIG. 4), the sampling clock φ1 shown in FIG. 1(a) and the start pulse ST1 shown in FIG. 1(b) are input, and the signals shown in FIGS. Sampling pulses Q11, Q12, . . . shown in FIG. 1(h) are output.

Similarly, in the sampling pulse generating section of the serial sample video signal drive circuit 10b shown in FIG. 4, the sampling pulse φ2 shown in FIG.
Then, a start pulse ST2 shown in FIG. 1(d) is inputted, and sampling pulses Q21, Q22, . . . are outputted as shown in FIG. 1(f) and FIG. 1(h).

[0033] The sampling gate of the S/H circuit is opened only during the period when these sampling pulses are at high level.
Video signals VR, VG, and VB are sampled.

Therefore, the actual output voltage level depends on the sampling pulse changing from high to low level (
Video signals VR, V at the moment when the sampling gate closes
Becomes G, VB level. The level is indicated by a circle in FIG. 1(i).

Here, the periods of the sampling clocks φ1 and φ2 shown in FIGS. 1(a) and 1(c) are as shown in FIG. 1(a).
As shown above, it changes regularly with ts1, ts2, and ts3 as one cycle.

Here, the period ts1. ts2 and ts3 have the following relationship with the dot period tvo of the video signal shown at the bottom of FIG. 1(i). ts1=ts3=5/6ts0......(3)t
s2=1/3ts0……(
4)

Furthermore, there is a phase difference between the sampling clocks φ1 and φ2 corresponding to the dot period tvo of the video signal. Furthermore, the start pulses ST1 and ST2 correspond to the corresponding sampling clocks φ1 and φ2.
It is set to respond to the rising edge of .

By using the above sample signals,
As shown in FIG. 1(e), (f), and (g), R1, G1
, Sampling pulses Q11, Q2 corresponding to B1 pixels
1, Q12, the timing at which the sampling pulse changes from high to low level (sampling gate closes) approaches each other, and the time difference between them is 1/6 tvo.

As a result, the sampled voltage levels correspond to the video signals VR1, VG1, VB1 of FIG. 1(i), respectively.
Therefore, the original input voltage level is maintained, and the coloring in white display that occurs in the conventional method does not occur.

Furthermore, in the sampling pulse Q22 corresponding to R2 belonging to the next display unit, the timing at which the sampling pulse changes from high to low level (the sampling gate closes) is the timing of the sampling pulse Q12 shown in FIG. 1(g). 2/3t for
There is a big time difference with vo.

As a result, the sampled voltage level becomes the video signal VR2 shown in FIG. 1(i), which is the same as the original input voltage level.
Coloring does not occur in black display. The same can be said of the sampling pulses corresponding to subsequent pixels, and all black and white display is realized without coloring.

[0042] The above has been explained using the case of black and white display as an example, but by using this sample signal, in general,
The problem of poor color display when high-frequency signals are input, which was encountered with conventional methods, can be avoided.

Next, a second embodiment of the present invention will be described. FIG. 2 is a timing diagram for explaining a second embodiment of the present invention in an LCD system connected as shown in FIG. Here, compared to FIG. 1, the generation method of the sampling pulse generator of the serial sample video signal drive circuit is different.

That is, this embodiment is a method in which the level of the sampling pulse changes at both the rising and falling timings of the sampling clock.

In this case, in order to realize a video signal sample similar to the sampling method shown in FIG.
, and the sampling clocks φ1 and φ2 shown in FIG. 2(c) are inputted to generate start pulses ST1 and ST2 as shown in FIG. 2(b) and FIG. 2(d), respectively. Therefore, here, the duty ratio of the sampling clocks φ1 and φ2 appears to change regularly according to the above-mentioned period ts1, ts2, and ts3 values.

Note that in the above embodiment, the period ts
Although the values of 1, ts2, and ts3 are defined according to equations (3) and (4), other values may be used. For example, period t
Even if the values of s1, ts2, and ts3 are arbitrarily determined so as to satisfy the following relationship, the same effect can be obtained. 2ts1+ts2=2tvo……(5)
ts1=ts3
......(6)

Here, the smaller the value of the period ts2, the closer the above sample points are, and the greater the above effect becomes. Therefore, the effect of suppressing color display defects also works for video signals with lower signal bands.

However, as the period ts2 decreases, the video signal drive circuit is required to operate at higher speed, so it cannot be made smaller unnecessarily.

From the above, the periods ts1, ts2, t
The value of s3 must be selected as an optimal condition based on the band characteristics of the signal processing IC circuit and the operating speed of the serial sample video signal driving circuit. For example, the condition in the above embodiment corresponds to ts2=1/3 tvo.

In this case, as mentioned above, tvo=156
If nsec, then ts2=52 nsec, which almost matches the operating speed of the video signal drive circuit IC, which currently operates at the highest speed.

[0051] Regarding the signal band of the current signal processing circuit IC, the bit frequency with a 3 dB reduction is approximately 3 to 9 MHz.
z, it can be said that there is a sufficient suppressing effect on color display defects under this condition. Therefore, the conditions shown in the above embodiment should be one of the optimum conditions when considering the current LCD system.

[0052] In the above embodiments, a method for sampling video signals of an LCD panel was explained, but the present invention
It can also be applied to video signal samples in display devices other than D.

Further, in the above embodiment, the number of video signal drive circuits is two, but the present invention can also be applied to a case where there are three or more.

[0054]

As described above, according to the present invention, the period or duty ratio of the sampling clock of a video signal is regularly changed, and the sampling clock is input to a plurality of video signal drive circuits that drive a color display device. By giving an appropriate phase difference to the signals and setting the start pulse to correspond to the sampling clock, we are able to bring the sample points of the R, G, and B video signals in the same display unit closer together, so that the waveforms are not distorted. This has the effect of suppressing color display defects that occur when sampling high-bandwidth video signals, which can lower the video signal processing band, allowing the use of inexpensive liquid crystal drive signal processing IC circuits, and reducing costs. be.

[Brief explanation of the drawing]

FIG. 1 is a timing diagram illustrating a video signal sampling method according to a first embodiment of the present invention.

FIG. 2 is a timing diagram for explaining a video signal sampling method according to a second embodiment of the present invention.

FIG. 3 is a circuit diagram of a conventional serial sample video signal driving circuit.

FIG. 4 is a configuration diagram of an LCD system using the serial sample video signal drive circuit of FIG. 3;

FIG. 5 is a timing diagram illustrating a conventional video signal sampling method.

[Explanation of symbols]

φ1 Sampling clock φ2 Sampling clock ST1 Start pulse ST2 Start pulse Q11 Sampling pulse Q12 Sampling pulse Q21 Sampling pulse Q22 Sampling pulse VR Video signal VB Video signal VG Video signal ts1 Sampling clock period ts2 Sampling clock period ts3 Sampling clock period tsvo Video 1-dot period of signal VR1 Sampled video signal VG1 Sampled video signal VB1 Sampled video signal VR2 Sampled video signal

Claims (1)

[Claims] Claim 1: A plurality of serial sample video signal drive circuits are controlled using a sampling clock whose period or duty ratio is regularly changed to have a predetermined phase difference and a start pulse corresponding to the sampling clock, and a predetermined phase difference of the sampling clock is controlled. Generate sampling pulses at the right timing,
A video characterized in that red, green, and blue video signals of the same display unit are sampled only during the high level period of this sampling pulse, and the sampling point of the video signal is brought close to the timing when the sampling pulse changes from high level to low level. How to sample the signal.