JPH04365133A - Preload instruction executing device and program correcting device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention]

0001

[Industrial Field of Application] The present invention relates to a method for increasing the effectiveness of a buffer memory in a computer when a copy of data in the main memory is held in the buffer memory to speed up instruction execution. The present invention relates to a device for executing a new instruction, and a program modification device for automatically arranging a program to use the new instruction.

0002

[Prior Art and Problems to be Solved by the Invention] In a computer, a relatively high-speed, small-capacity buffer memory is provided in the central processing unit, and once accessed, data in the main memory is processed to a certain extent, including the data. When executing an instruction that specifies that a long block of data is held and refers to data in main memory as an operand, if there is a copy of the necessary data in the buffer memory, the main memory A well-known method is to execute an instruction by referring to the copy without accessing the main memory, and to access the main memory only when there is no copy. This buffer memory is also called a cache memory or the like.

As is well known, the buffer memory can be constructed by using a memory element that is sufficiently faster than the main memory in the vicinity of the instruction execution mechanism of the processing unit. Therefore, when the data in the buffer memory can be used, the instruction execution time can be significantly reduced compared to when data is retrieved from the main memory.

[0004] Therefore, in order to effectively utilize the effect of such a buffer memory, it is necessary to increase the chances that the data necessary for executing each instruction will be retained in the buffer memory by the time of execution. Must be.

[0005] To this end, after reading data from the main memory to the buffer memory, the program is modified based on the principle that instructions that require the data are executed as soon as possible after the data has been read. It has been considered that the effectiveness of buffer memory can be improved by methods such as

However, it has not been done in the past to proactively prepare necessary data in a buffer memory by a special instruction before the instruction is executed. The present invention provides a preload instruction execution device that executes instructions that can prepare necessary data in advance in a buffer memory with less influence on the execution of instructions necessary in the original program, and an appropriate position of the program. The purpose of the present invention is to provide a program modification device that can automatically insert preload instructions into a program.

[0007]

Means for Solving the Problems FIG. 1 is a block diagram showing the configuration of the present invention. FIG. 1(a) shows the configuration of a preload instruction execution device, which has a main memory device 1 and a buffer memory 2, and executes an instruction that specifies to refer to data on the main memory device 1 as an operand. In this case, if there is a copy of the data in the buffer memory, refer to the copy; if there is no copy, read data of a predetermined length including the data from the main storage device 1 and hold it in the buffer memory 2. In a computer configured to refer to the data, a preload instruction 3 is provided, and in the preload instruction 3,
Information specifying an address on the main memory device 1 as an operand is provided according to a predetermined instruction format.

The preload instruction execution means 4 performs a process of identifying whether or not there is a copy of the data at the address in the buffer memory 2, and, if there is no copy, transfers a predetermined length of data including the data to the main memory. 1 is read out unconditionally and held in the buffer memory 2, and the execution of the preload instruction is completed.

FIG. 1(b) shows the configuration of the program modification device 5, in which a program 6 configured to be executed by the computer has an instruction sequence consisting of instructions for the computer.
When the operand identified by the operand identification unit 10 and referenced by each instruction is data on the main storage device, a predetermined position in the instruction sequence to be executed prior to the instruction satisfies a predetermined condition. If satisfied, the instruction generation unit 11 generates the preload instruction specifying the data as an operand, the insertion processing unit 12 inserts the preload instruction at the predetermined position, and generates the modified program 13.

In addition, the computer has a plurality of instruction execution mechanisms that can be executed in parallel, and the instruction sequence includes a group of instructions to be executed in parallel, up to the number of instruction execution mechanisms, as an instruction set. If it consists of a sequence of the instruction set, the insertion processing unit 12
The predetermined position is provided in the instruction set consisting of instructions whose number is less than the number of instruction execution mechanisms.

[0011]

[Operation] According to the preload instruction of the present invention, if the specified data on the main memory is not in the buffer memory, the block containing the data is unconditionally read from the main memory without checking for storage protection, etc. Only the processing held in the buffer memory can be executed. This instruction specification makes it easy to make the preload instruction an instruction that can be executed at relatively high speed.

By placing such a preload instruction at an appropriate location in a program, the data can be brought to the buffer memory by the preload instruction prior to execution of an instruction that actually requires the data. Ba,
Since the effect of buffer memory can be effectively used to speed up instruction execution, the program modification device of the present invention examines the operands of program instructions and stores the necessary operand data in advance in the main memory using a preload instruction. A modification will be made to automatically insert a preload instruction so that it can be retrieved from.

[0013] In this case, if the computer has multiple instruction execution mechanisms that execute in parallel, due to data dependencies in program logic, functional constraints of the instruction execution mechanisms, etc. cannot be assigned,
By searching for a step where the instruction execution mechanism has slack and inserting a preload instruction there, the execution time of the preload instruction is hidden, so the function of the preload instruction can be used most efficiently.

[0014]

[Example] The preload instruction of the present invention operates in the same way as a normal so-called load instruction that loads data in main memory into a general-purpose register or floating-point register of a processing unit, but does not load data into a register. It is a command.

[0015] Also, before it is necessary in the program logic,
Since it is used to access the main memory, there is a possibility that it will be executed before the conditions such as memory protection are set, so the access will be executed unconditionally without checking for so-called instruction exceptions such as memory protection. Such an instruction specification also has the effect of shortening the instruction execution time.

[0016] It is sufficient to provide a preload instruction with the above instruction specifications as a completely new instruction, but if possible, for example, a preload instruction with a specific register (for example, general register #0 (GR
0), and if necessary floating point register #0 (FR0
)) as a special register that cannot be written to.
This can also be achieved without creating a new special operation code.

In that case, it can be easily controlled by disconnecting the write input bus to the above-mentioned specific register, and in that case, unconditional access control is performed by the operating system's interrupt processing when an exception occurs. In this case, the exception may be ignored.

When the preload instruction is realized in this manner, for example, when the instruction is expressed in an assembler language style, the floating point load instruction becomes ``fload x<i>''.
, fpr2'', and an instruction to load double-precision floating point data x<i> on the main memory into floating point register fpr2.
, fpr0'', it becomes a preload instruction.

Therefore, the preload instruction "fload
x<i>, fpr0'' is executed, if the double-precision floating point data x<i> on the main memory is not in the buffer memory, the block containing that data is unconditionally read from the main memory and stored in the buffer. Only the process of storing into memory is executed, and the contents of floating point register fpr0 remain unchanged.

Next, a program modification process for automatically inserting a preload instruction into a program will be described. A computer has, for example, three sets of instruction execution mechanisms: up to two integer type operation instructions or floating point operation instructions, one branch instruction,
In combination with floating point arithmetic instructions or integer type arithmetic instructions,
It is assumed that up to three instructions can be executed in parallel.

A compiler that generates a program that can effectively utilize the parallel execution function of a computer is well known. In other words, it analyzes the source program of a given language like a normal compiler,
When the assembler-expressed instruction code for the target computer is generated in the usual way, the so-called data dependencies between instructions, which is the relationship between the data definition in each instruction and the reference of that data in other instructions, are analyzed. Instructions are ordered in a way that does not cause conflicts in terms of data dependencies.

Based on this ordering, the target program shown in FIG. 2(b) is generated from the source program shown in FIG. 2(a), for example, by sequentially packing instructions that can be executed in parallel into a set of instructions. Each line in FIG. 2(b) indicates each instruction set, and the three instructions lined up in each instruction set are instructions that are executed in parallel.

In FIG. 2(b), ``nop'' is a dummy invalid instruction, ``brc'' is a branch instruction, and the others are arithmetic instructions. ” etc. represent floating point register #5, etc., and “x<i>” etc. are data names and correspond to address information indicating data on the main storage device.

As seen in this example, even if there are three instruction execution mechanisms, it is not possible to fill them all.
You can fill in the p instruction, so you can use nop at that position.
If an appropriate preload instruction is executed instead of the preload instruction, the original program for executing the preload instruction will not be affected and efficiency will be improved.

FIG. 3 is a flow chart showing an example of preload instruction insertion processing performed by the program modification device. Considering the case where a preload instruction is prefixed to only the load instruction, the program correction device receives the load instruction from the compiler and processes it as follows.

First, in processing step 20, a set of instructions having a nop instruction is searched for in the set of instructions preceding the set of instructions in which the load instruction is placed. This is done, for example, by scanning a fixed number of instruction sets preceding the load instruction set from the beginning to before the load instruction set.

If it is identified in processing step 21 that there is a preceding instruction set with a nop instruction, processing step 2
In step 2, one of the nop instructions in the instruction set is replaced with a load instruction, but the number of the load destination register of the load instruction is set to #0, thereby changing it to a preload instruction.

In processing step 20, if there is no corresponding instruction set, for example, no preload instruction is inserted for this load instruction, and the processing ends. The result of inserting a preload instruction into the program of FIG. 2(b) through the above process is shown in FIG. 2(c). The shaded instructions in FIG. 2(c) are the inserted preload instructions, and the preload instructions inserted in instruction set 4 are the instructions in instruction set 6.
The preload instruction inserted into instruction set 7 corresponds to the floating point load instruction of instruction set 10.

[0029]

[Effects of the Invention] As is clear from the above description, according to the present invention, in a computer that maintains a copy of data in the main memory in the buffer memory, the influence on the execution of instructions necessary in the original program can be reduced. Therefore, an instruction is provided that can prepare necessary data in a buffer memory in advance, and a preload instruction can be automatically inserted at an appropriate position in a program, which has a significant industrial effect.

[Brief explanation of the drawing]

[Figure 1] Block diagram showing the configuration of the present invention

[Figure 2]
Diagram showing an example program

[Figure 3] Flowchart of preload instruction insertion process

[Explanation of symbols] 1 Main storage device 2 Buffer memory 3 Preload instruction 4 Preload instruction execution means 5 Program modification device 6 Program 10 Operand identification section 11 Instruction generation section 12 Insertion processing section 13 Modified programs 20 to 22 Processing steps

Claims (3)

[Claims] 1. When executing an instruction that has a main memory (1) and a buffer memory (2) and specifies that data on the main memory is referred to as an operand,
If there is a copy of the data in the buffer memory, refer to the copy; if there is no copy, read a predetermined length of data including the data from the main storage device, hold it in the buffer memory, and read the data. In a computer configured to refer to , a preload instruction (3) is provided, information for specifying an address on the main storage device as an operand according to a predetermined instruction format is provided in the preload instruction, and means for executing the preload instruction. (4) is a process of identifying whether or not there is a copy of the data at the address in the buffer memory (2), and if there is no copy, the data of a predetermined length including the data is unconditionally transferred from the main storage device. 1. A preload instruction execution device characterized in that the preload instruction execution device is configured to complete execution of the preload instruction by only reading the preload instruction and holding the preload instruction in the buffer memory. 2. Regarding a program (6) configured to be executed by the computer according to claim 1, an operand referenced by each instruction is stored in the main memory according to claim 1. 2. The preloading method according to claim 1, wherein, in the case of data on a device, if a predetermined position in the instruction sequence to be executed prior to the instruction satisfies a predetermined condition, the data is designated as an operand. generate an instruction,
A program correction device characterized in that (5) the program correction device is configured to insert the preload instruction into the predetermined position. 3. The computer has a plurality of instruction execution mechanisms that can be executed in parallel, and the instruction sequence is an instruction set for each group of instructions to be executed in parallel up to the number of instruction execution mechanisms. 3. The program correction apparatus according to claim 2, wherein the program correction apparatus comprises a sequence of the instruction sets, and the predetermined position is provided in the instruction set consisting of instructions whose number is less than the number of the instruction execution mechanisms.