JPH04358241A - Store buffer controller - Google Patents

Abstract

PURPOSE:To accelerate data transfer to a data request part when an entire real address is not coincident although an in-page address is coincident by suppressing the comparison of the in-page address and directly executing the comparison of the entire real address. CONSTITUTION:When the read address of a read request outputted from the data request part is registered on a first address translation buffer 111, the coincidence of the entire read address is compared on a cache access stage after an in-page address 112 of the read request coming from the data request part is compared with each in-page address of the address part of a store buffer on an address translation stage. When the real address is not registered on the first address translation buffer 111 but registered on a second address translation buffer 113, an address comparison part control means 101 is provided to compare the coincidence of the entire real address on the address translation stage. Therefore, the data transfer to the data request part can be accelerated, and performance can be improved.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a throw buffer control device, and more particularly to a store buffer control device that controls a store buffer that stores data written from an arithmetic processing unit to a main memory in correspondence with the address of the data.

0002

[Prior Art] Conventionally, in this type of store buffer control device, when a read request issued from a data request unit involves translation from a virtual address to a real address, the real address is cannot be determined, so the address translation stage compares only the address in the page of the read request and the address in each page of the address part of the store buffer, and if a match is detected, the address translation stage calculates the The cache access stage compares the real address with each real address stored in the address field of the store buffer, and detects a match by comparing addresses within the page and comparing all real addresses. When a read request that attempts to read a store request that has not been matched from the cache memory is detected, the store request in the store buffer is flushed to the cache memory, and after the store request that caused the match detection is flushed to the cache memory, Data was being returned to the data request section.

0003

[Problems to be Solved by the Invention] In the conventional store buffer control device described above, the real address of the read request issued from the data request section is not registered in the first address translation buffer, and Even if the real address has already been found when indexing the address array in the address translation stage, such as when it is registered in a buffer, the address translation stage compares the addresses within the page and then Since the entire real address was compared in the cache access stage, if the address within the page matched but the entire real address did not match, the data transfer to the data requesting unit was delayed and performance deteriorated. Ta.

0004

[Means for Solving the Problems] A store buffer control device of the present invention stores a plurality of pairs of virtual page numbers and real page numbers, and quickly converts a request address from a data requesting unit from a virtual address to a real address. The first address translation buffer has a small capacity to perform address translation, and the first address translation buffer has a large capacity but performs address translation when the actual address to be sought is not registered in the first address translation buffer. A low-speed second address translation buffer, an address array that checks whether the data requested by the data request unit exists in the cache memory using the converted real address, and an operation result and Equipped with a store buffer that holds multiple pairs of storage addresses of operation results on the main memory, the address conversion stage converts the request address from a virtual address to a real address, indexes the address array, and further reads the data request section. If the real address of the read request sent from the data request section is registered in the first address conversion buffer in a pipeline computer where the requested data is read from the cache memory, the address of the read request sent from the data request section is The address in the page of the read request is compared with the address in each page of the store buffer in the address translation stage, and then in the cache access stage, the match in the entire real address is compared, and the address is registered in the first address translation buffer. If the real address is not registered in the second address translation buffer, the address comparison unit control means is provided to compare the entire real addresses for coincidence in the address translation stage.

[0005]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention. In FIG. 1, the store buffer control device according to the first embodiment of the present invention includes an address comparator control circuit 10.
Consists of 1. The store address register A102 and the store address register B103 are registers for storing write addresses to the main memory of data stored from the arithmetic execution unit to the main memory. Address A
104 is written, and the contents of the register selected by the address read pointer 106 and selector A 107 are sent to the main memory and cache memory. The virtual address register 108 is a register that stores the virtual address (or real address if address translation is not required) sent from the address sending unit.If address translation is not required, the virtual address register A109 is used as is.
is stored in If address translation is required, virtual page number 110 is set to address translation buffer TLB1 (11
After being converted into a real page number in step 1), it is stored in the real address register A109. In addition, address 11 on the page
2 is stored as is. Address translation buffer TLB
2 (113), address conversion is performed simultaneously with TLB1 (111), and the converted real address is stored in the real address register B114. Here, if TLB1(1
If the real page number corresponding to virtual page number 110 is not registered in 11), TLB2 (113)
The real address converted in step 1, that is, the contents of the real address register B114, is stored in the real address register A109. TLB2 (113) also has virtual page number 1
If the real page number corresponding to 10 is not registered, the paging mechanism obtains the real page number and stores it in the real address register C115 along with the address within the page.
After that, it is stored in the real address register A109. By the way, in the address translation stage, a real address is obtained and, using the real address, it is checked by an address array (not shown) whether or not the data requested to be read from the data request section exists in the cache memory. ) has a small capacity, so address conversion is very fast, and the address array can be directly examined using the real page number converted by TLB1 (111). However, since the capacity is small, it is difficult to expect a TLB hit (the actual page number to be sought is registered in the TLB). Therefore, if there is a TLB miss in TLB1 (111), it has a larger capacity (that is, the probability of a TLB hit is high, but it is slow and the address array cannot be directly examined using the converted real address). T.L.B.
2 (113) converts the address and stores it in real address register B1.
By using the real address stored in TLB
The deterioration in performance due to the low probability of a TLB hit of 1 (111) is minimized.

[0007] The intra-page address comparison unit 116 stores the store address register A102 and the store address register B.
The address conversion stage matches the in-page address part of the real address stored in A 103 and the in-page address 112 of the read request.
The real address stored in the store address register B103 and the real address B118 of the read request are compared to see if they match. The real address B118 is usually
Since the output of the real address register A109 is selected, the real addresses are compared in the cache access stage, but if there is a TLB hit in TLB1 (111), the real address register switching signal 119 causes the address comparison unit control to be performed. Circuit 101 is real address B11
8 to the output of the real address register B114, a comparison of the real addresses is performed in the address translation stage. Also, at this time, the comparison output of the intra-page address comparison section 116 is suppressed by the address comparison section control circuit 101. Then, when the store check unit 120 detects that the read request has overtaken the store request based on the match report from the in-page address comparison unit 116 and the real address comparison unit 117, that is, the store address register A102, the store address register B1
When the data request unit detects that the data request unit attempts to read the store data corresponding to the address stored in address 03 from the cache memory before it is written to the cache memory, the reply signal 121 to the data request unit is suppressed. , the store request in the store buffer is flushed out to the cache memory, and after the store request that is the key to detecting address matching is flushed out of the cache memory, the requested data is transferred from the cache memory to the data requesting unit along with the reply signal 121. .

[0008]

As explained above, the present invention suppresses the comparison of addresses within a page when a TLB miss occurs in the small-capacity, high-speed address translation buffer TLB1, and a TLB hit occurs in the large-capacity, low-speed address translation buffer TLB2. Direct comparison of the entire real addresses has the effect of speeding up data transfer to the data requesting unit and improving performance when addresses within the page match but the real addresses do not match as a whole.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram showing one embodiment of the present invention.

[Explanation of symbols]

101 Address comparison section control circuit 102
Store address register A103 Store address register B104 Real address A 105 Address write pointer A106
Address read pointer 107 Selector A 108 Virtual address register 109 Real address register A 110 Virtual page number 111 Address translation buffer (TLB1) 11
2 In-page address 113 Address conversion buffer 114 Real address register B 115 Real address register C 116 In-page address comparison section 117
Real address comparison section 118 Real address B 119 Real address register switching signal 120
Store check section 121 reply signal

Claims (1)

[Claims] 1. A small-capacity first address conversion buffer that stores a plurality of pairs of virtual page numbers and real page numbers and converts a request address from a data request unit from a virtual address to a real address at high speed; A second address translation buffer, which has a large capacity but is slower than the first address translation buffer, performs address translation when the desired real address is not registered in the first address translation buffer; An address array that checks whether or not the data requested by the data requesting section exists on the cache memory using the converted real address, and an address array that checks whether the data requested by the data requesting section exists on the cache memory, and storing the operation result in the operation execution section and the operation result on the main memory. It is equipped with a store buffer that holds multiple pairs of storage addresses, and the address conversion stage converts the request address from a virtual address to a real address, indexes the address array, and reads the data requested by the data request unit. exists on the cache memory, in the pipeline computer that reads data from the cache memory in the next cache access stage, the real address of the read request issued from the data request unit is transferred to the first address translation buffer. If the address in the page of the read request that came from the data request section matches the address in each page of the address section of the store buffer, the address translation stage compares the address in the page, and then the cache access stage The match of the entire real address is compared at the address translation stage, and if it is not registered in the first address translation buffer but is registered in the second address translation buffer, the match of the entire real address is compared in the address translation stage. A store buffer control device comprising address comparison unit control means for comparison.