JPH04356956A - Semiconductor device and its manufacture - Google Patents
Semiconductor device and its manufactureInfo
- Publication number
- JPH04356956A JPH04356956A JP3131425A JP13142591A JPH04356956A JP H04356956 A JPH04356956 A JP H04356956A JP 3131425 A JP3131425 A JP 3131425A JP 13142591 A JP13142591 A JP 13142591A JP H04356956 A JPH04356956 A JP H04356956A
- Authority
- JP
- Japan
- Prior art keywords
- hole
- semiconductor substrate
- semiconductor device
- wiring
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 51
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 19
- 239000002184 metal Substances 0.000 claims abstract description 49
- 229910052751 metal Inorganic materials 0.000 claims abstract description 49
- 239000000758 substrate Substances 0.000 claims abstract description 26
- 239000000853 adhesive Substances 0.000 claims abstract description 17
- 230000001070 adhesive effect Effects 0.000 claims abstract description 17
- 239000000126 substance Substances 0.000 claims 1
- 238000000034 method Methods 0.000 description 18
- 230000015572 biosynthetic process Effects 0.000 description 9
- 239000000243 solution Substances 0.000 description 9
- 229910045601 alloy Inorganic materials 0.000 description 6
- 239000000956 alloy Substances 0.000 description 6
- 239000010408 film Substances 0.000 description 6
- 230000010354 integration Effects 0.000 description 6
- 229910020220 Pb—Sn Inorganic materials 0.000 description 5
- 229910001080 W alloy Inorganic materials 0.000 description 5
- 238000000206 photolithography Methods 0.000 description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 238000007747 plating Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 238000001020 plasma etching Methods 0.000 description 4
- 229910000679 solder Inorganic materials 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 239000011347 resin Substances 0.000 description 3
- 229920005989 resin Polymers 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 238000002844 melting Methods 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 230000000149 penetrating effect Effects 0.000 description 2
- 238000003672 processing method Methods 0.000 description 2
- 238000007650 screen-printing Methods 0.000 description 2
- 230000008646 thermal stress Effects 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- 229910001069 Ti alloy Inorganic materials 0.000 description 1
- 239000003082 abrasive agent Substances 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 230000002250 progressing effect Effects 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 230000035882 stress Effects 0.000 description 1
- 230000009897 systematic effect Effects 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73257—Bump and wire connectors
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【０００１】0001
【産業上の利用分野】この発明は、半導体装置及びその
製造方法に関する。さらに詳しくは半導体チップの上下
面を貫通する外部接続用入出力端子からなる半導体装置
及びその製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same. More specifically, the present invention relates to a semiconductor device comprising external connection input/output terminals penetrating the upper and lower surfaces of a semiconductor chip, and a method for manufacturing the same.
【０００２】0002
【従来の技術】従来、シリコン半導体基板上に作られる
、ＩＣ・ＬＳＩは日夜、製造技術が進歩し、トランジス
ター等の集積度も飛躍的に増大している。集積度が上る
につれ、半導体デバイス（半導体チップ）の機能も飛躍
的に向上し、単なる部品よりも、大きなシステムとして
みなされるようになっている。又、同時にシステムの構
成要素としてのＣＰＵ（論理回路）マスクＲＯＭ、ＥＰ
ＲＯＭ、ＥＥＰＲＯＭ、フラッシＥＰＲＯＭ、ＤＲＡＭ
、ＳＲＡＭ、Ｉ２Ｌ、高速入出力部（バイポーラ、バイ
−ＣＭＯＳ）等、それぞれの独立したデバイスがそれぞ
れの専用の製造工程を用い効率良く生産が行われるよう
になっている。このような状況下においてニューロネッ
トワーク素子等、多数の構成要素の集合した大規模半導
体装置の開発が望まれている。2. Description of the Related Art Conventionally, manufacturing technology for ICs and LSIs manufactured on silicon semiconductor substrates is progressing day by day, and the degree of integration of transistors and the like is increasing dramatically. As the degree of integration increases, the functionality of semiconductor devices (semiconductor chips) also improves dramatically, and they are now viewed as larger systems rather than just components. At the same time, the CPU (logic circuit) mask ROM, EP as a component of the system
ROM, EEPROM, flash EPROM, DRAM
, SRAM, I2L, high-speed input/output units (bipolar, bi-CMOS), and other independent devices are now efficiently produced using their own dedicated manufacturing processes. Under these circumstances, there is a desire to develop large-scale semiconductor devices such as neuronetwork elements that are assembled with a large number of components.
【０００３】0003
【発明が解決しようとする課題】このような、技術的要
素の中で以下のような問題がある。
１）ＬＳＩの集積規模の増大に伴い、入出力部の外部接
続端子数が大きくなり、チップ面上のボンディングパッ
ド及び入出力保護回路の面積比率が増大し集積効率が低
下する。
２）ＬＳＩの集積規模の増大に伴い、個々のトランジス
ター等で消費される電気エネルギーが熱となり、発熱量
が大きくなり、デバイスの温度上昇を引き起し、信頼性
低下、集積度の限界を生じさせる。
３）ＬＳＩ等デバイスに求められるシステム的な機能の
高度化に伴い、１つの２次元的表面に形成される従来の
ＬＳＩ製造工程では、あらゆる前記構成要素を包含する
製造プロセスを構築することは非常に困難であり、仮に
そのような複雑な製造プロセスを構築することが出来た
としても、最小配線幅寸法等に制限が生じ現在ある個々
の専用の製造工程よりも非常に効率の悪いものとなり、
出来上ったデバイスの性能も低下するという問題がある
。[Problems to be Solved by the Invention] Among these technical elements, there are the following problems. 1) As the scale of LSI integration increases, the number of external connection terminals in the input/output section increases, the area ratio of bonding pads and input/output protection circuits on the chip surface increases, and the integration efficiency decreases. 2) As the scale of LSI integration increases, the electrical energy consumed by individual transistors becomes heat, increasing the amount of heat generated, causing a rise in device temperature, lowering reliability, and limiting the degree of integration. let 3) With the increasing sophistication of the systematic functions required of devices such as LSIs, it has become extremely difficult to construct a manufacturing process that includes all of the above components in the conventional LSI manufacturing process, which is formed on a single two-dimensional surface. Even if it were possible to construct such a complex manufacturing process, it would be much less efficient than the current individual dedicated manufacturing processes due to restrictions on minimum wiring width dimensions, etc.
There is also the problem that the performance of the finished device also deteriorates.
【０００４】この発明は、上記問題を解決するためにな
されたものであって、従来のそれぞれ専用の製造工程を
用いて生産されるＣＰＵ、マスクＲＯＭ、ＤＲＡＭ等そ
れぞれ１つの半導体基板からなる独立した機能の装置（
デバイス）を多数接続でき、大規模装置（システム）を
構成することのできる外部接続用入出力端子を有する半
導体装置及びその製造方法を提供しようとするものであ
る。The present invention has been made to solve the above problem, and it is possible to manufacture independent CPUs, mask ROMs, DRAMs, etc. each made of one semiconductor substrate using conventional manufacturing processes dedicated to each. Functional equipment (
It is an object of the present invention to provide a semiconductor device having input/output terminals for external connection to which a large number of devices (devices) can be connected and to configure a large-scale device (system), and a method for manufacturing the same.
【０００５】[0005]
【課題を解決するための手段】この発明によれば、所定
位置にスルーホールを有する半導体基板において、スル
ーホールの壁面に絶縁層とその上に接着性金属層を積層
し、配線用金属プラグをスルーホールを介してその上部
と下部に突出するように設けたことを特徴とする半導体
装置が提供される。上記半導体基板は、素子形成前のウ
ェハー、素子形成中のウェハー又は素子形成後のウェハ
ーのいずれも用いることができる。上記スルーホールは
、配線用金属プラグを形成するためのものであって、半
導体基板の外部接続用入出力端子の形成位置に開孔され
る。スルーホールの形成は、フォトリソグラフィー法、
ドリル加工法、レーザー加工法、超音波加工法、液体ホ
ーニング法（微細研磨材の高圧噴射加工）等によって行
うことができる。この中で、例えばフォトリソグラフィ
ー法について述べると、まず、半導体基板上にスクリー
ン印刷法等を用い、厚さ ２００〜 ５００μｍ程度の
ホトレジストを塗布し、外部接続用入出力端子を形成し
ようとする位置に、フォトリソグラフィーの技術を用い
て直径５０〜 ２００μｍの窓（樹脂のない部分）をあ
けてレジストパターンを形成する。窓の形状は、通常円
形であるが、後述する配線用金属プラグと半導体基板と
の熱膨張率の差により生ずる応力に対して、有利な形状
を適宜選定するのが好ましい。次に上記レジストパター
ンをマスクにしてリアクティブイオンエッチング（通称
ＲＩＥ）装置を用い、異方性のエッチングを行いウェハ
ー裏面まで貫通する穴（スルーホール）を形成する。上
記絶縁層は、半導体基板と形成する配線用金属プラグと
を絶縁するためのものである。絶縁膜の形成は、例えば
次の３つの方法等を用いて行うことができる。第１は、
酸素もしくは水蒸気を用いたシリコンの熱酸化法、第２
は、ＣＶＤ法によってＳｉＯ２ 、ＳｉＮの薄膜を堆積
する方法、第３は、半導体基板と逆の極性を有する不純
物拡散層を形成する方法である。また、必要により上記
壁面以外の不要の絶縁層は、通常後工程の接着性金属層
を形成した後に不要の接着性金属層と共に除去される。
上記接着性金属層は、スルーホールを介して設ける配線
用金属プラグを接着するためのものであって、絶縁層の
上を含む領域に例えばＴｉ／Ｗ合金、Ｔｉ、Ｃｒ、Ｎｉ
等の高融点金属もしくは、それらの合金の層を公知の方
法によって形成し、好ましくはぬれ性を向上させるため
にその上に例えば、Ｃｕ、Ａｇ、Ａｕ、Ｎｉ等の薄膜を
積層して、形成することができる。この後に、必要によ
り上記壁面以外の不要の絶縁層と接着性金属層を除去す
る。配線用金属プラグは、外部接続用入出力端子を構成
するためのものであって、スルーホールを介してその上
部と下部に突出するように設けられる。配線用金属プラ
グの形成は、金属の溶融物又は溶液（通常メッキ液とよ
ばれる）に半導体基板の片面を接触させることによって
毛細管現象と表面張力によって溶融金属をスルーホール
内及びスルーホール上に導入し、適宜冷却または通電す
ることによって固化して行うことができる。また金属の
溶液を用いる方法は、中空の巣を有する配線用金属プラ
グを形成することができ、この配線用金属プラグは半導
体基板との熱膨張系数の違いにより生ずる熱応力を低下
させることができるので好ましい。金属の溶融物は、約
１５０〜 ４００°Ｃ例えば半田（Ｐｂ−Ｓｎ系合金
）を溶融して用いることができる。金属の溶液は、例え
ばＣｕ、Ａｕ等の溶液（公知のメッキ液）を用いること
ができる。また、配線用金属プラグの上記突出した領域
は、外部接続用入出力端子の外部と接合部分を形成する
ためのものであって、突出した高さ（スルーホールから
の高さ）が、通常５〜５０μｍである。外部接続用入出
力端子の形成は、複数の種類の半導体装置について行な
われる。この後外部接続用入出力端子を介して複数の半
導体装置を適宜組合せ大規模半導体装置を構成すること
ができる。[Means for Solving the Problems] According to the present invention, in a semiconductor substrate having a through hole at a predetermined position, an insulating layer and an adhesive metal layer are laminated on the wall surface of the through hole, and a metal plug for wiring is laminated on the wall surface of the through hole. There is provided a semiconductor device characterized in that the semiconductor device is provided so as to protrude from its upper and lower parts through through holes. As the semiconductor substrate, any of a wafer before device formation, a wafer during device formation, or a wafer after device formation can be used. The through hole is for forming a metal plug for wiring, and is opened at a position on the semiconductor substrate where an input/output terminal for external connection is to be formed. The through holes are formed using photolithography method,
This can be performed by a drilling method, a laser processing method, an ultrasonic processing method, a liquid honing method (high-pressure injection processing of a fine abrasive material), or the like. Among these methods, for example, referring to the photolithography method, first, a photoresist with a thickness of about 200 to 500 μm is applied onto a semiconductor substrate using a screen printing method, etc., and then applied to the positions where input/output terminals for external connections are to be formed. , a resist pattern is formed by opening a window (the part without resin) with a diameter of 50 to 200 μm using photolithography technology. The shape of the window is usually circular, but it is preferable to appropriately select a shape that is advantageous for stress caused by a difference in thermal expansion coefficient between the wiring metal plug and the semiconductor substrate, which will be described later. Next, using the resist pattern as a mask, anisotropic etching is performed using a reactive ion etching (commonly known as RIE) device to form holes (through holes) that penetrate to the back surface of the wafer. The insulating layer is for insulating the semiconductor substrate and the wiring metal plug to be formed. The insulating film can be formed using, for example, the following three methods. The first is
Thermal oxidation of silicon using oxygen or water vapor, Part 2
The first method is to deposit thin films of SiO2 and SiN by CVD, and the third method is to form an impurity diffusion layer having a polarity opposite to that of the semiconductor substrate. Further, if necessary, the unnecessary insulating layer other than the above-mentioned wall surface is usually removed together with the unnecessary adhesive metal layer after forming the adhesive metal layer in a subsequent process. The adhesive metal layer is for adhering a wiring metal plug provided through a through hole, and is made of, for example, Ti/W alloy, Ti, Cr, Ni, etc. in the region including the top of the insulating layer.
A layer of a high melting point metal such as or an alloy thereof is formed by a known method, and preferably a thin film of Cu, Ag, Au, Ni, etc. is laminated thereon to improve wettability. can do. After this, unnecessary insulating layers and adhesive metal layers other than the wall surface are removed if necessary. The metal plug for wiring constitutes an input/output terminal for external connection, and is provided so as to protrude from the upper and lower parts through the through hole. Metal plugs for wiring are formed by bringing one side of a semiconductor substrate into contact with a molten metal or solution (usually called a plating solution) and introducing molten metal into and over the through-holes using capillary action and surface tension. It can be solidified by cooling or energizing as appropriate. In addition, the method using a metal solution can form a metal plug for wiring having a hollow cavity, and this metal plug for wiring can reduce thermal stress caused by the difference in thermal expansion coefficient from the semiconductor substrate. Therefore, it is preferable. The molten metal may be used by melting solder (Pb-Sn alloy) at about 150 to 400°C. As the metal solution, for example, a solution of Cu, Au, etc. (known plating solution) can be used. The above-mentioned protruding area of the wiring metal plug is for forming a joint part with the outside of the external connection input/output terminal, and the protruding height (height from the through hole) is usually 5.5 mm. ~50 μm. Formation of external connection input/output terminals is performed for a plurality of types of semiconductor devices. Thereafter, a large-scale semiconductor device can be constructed by appropriately combining a plurality of semiconductor devices via external connection input/output terminals.
【０００６】[0006]
【作用】配線用金属プラグが、スルーホールの上部と下
部に突出した部分で他の半導体装置又はヒートシンクと
重ねて接続させ、外部端子と接続させると共に、半導体
装置の駆動時に発生する熱を放散させる。[Function] The wiring metal plug connects to other semiconductor devices or heat sinks by stacking them on the upper and lower parts of the through hole, connects them to external terminals, and dissipates the heat generated when the semiconductor device is driven. .
【０００７】[0007]
実施例１
半導体基板を貫通するスルーホールの形成図１（ａ）に
示すように、半導体基板１上にスクリーン印刷法を用い
て厚さ ３５０μｍ程度のフォトレジスト膜２を塗布し
、電極を形成しようとする場所に直径 １３０μｍの窓
（樹脂のない部分）をフォトリソグラフィー法を用いて
形成する。図１（ｂ）に示すように、リアクティブイオ
ンエッチング（通称ＲＩＥ）装置を用い、フォトレジス
ト膜２をマスクにしてエッチングイオン３を照射しウェ
ハー裏面まで貫通する穴（スルーホール４）が形成され
るまで、異方性のエッチングを行う。Example 1 Formation of a through hole penetrating a semiconductor substrate As shown in FIG. 1(a), a photoresist film 2 with a thickness of about 350 μm is applied on a semiconductor substrate 1 using a screen printing method to form an electrode. A window (portion without resin) with a diameter of 130 μm is formed at the location using photolithography. As shown in FIG. 1(b), using a reactive ion etching (commonly known as RIE) device, etching ions 3 are irradiated using the photoresist film 2 as a mask to form holes (through holes 4) that penetrate to the back surface of the wafer. Perform anisotropic etching until the
【０００８】次に、図１（ｃ）に示すように、形成され
たスルーホール４の内面に酸素もしくは水蒸気を用いた
シリコンの熱酸化によって酸化シリコン膜５を形成する
。Next, as shown in FIG. 1C, a silicon oxide film 5 is formed on the inner surface of the formed through hole 4 by thermal oxidation of silicon using oxygen or water vapor.
【０００９】スルーホールへの接着性金属層と配線用金
属プラグの形成
図１（ｄ）に示すように、半導体素子形成後、予め前記
のように形成されたスルーホール面に、後述の配線用金
属プラグ（半田、Ｐｂ−Ｓｎ合金）に対する接着性向上
と拡散防止の為の、バリアー形成の作用をする接着性金
属層（Ｔｉ／Ｗ合金）６と、更に、この上に後述の配線
用金属プラグ（Ｐｂ−Ｓｎ合金）に対するぬれ性を得る
ための金属層（Ｃｕ）を形成する。Formation of an adhesive metal layer and metal plug for wiring on the through hole As shown in FIG. An adhesive metal layer (Ti/W alloy) 6 acts as a barrier to improve adhesion to the metal plug (solder, Pb-Sn alloy) and prevent diffusion. A metal layer (Cu) is formed to obtain wettability to the plug (Pb-Sn alloy).
【００１０】次に図２（ｅ）に示すように、前記スルー
ホールの壁面の処理の完了した半導体基板を素子形成面
１ａを上にして溶融した半田（Ｐｂ−Ｓｎ合金）上に浮
かせ、毛細管現象と表面張力を利用して、スルーホール
内にＰｂ−Ｓｎ合金７を充填し、冷却固化して図２（ｆ
）に示すようにスルーホール上部に突出した領域を有す
る入出力端子７ａを形成する。Next, as shown in FIG. 2(e), the semiconductor substrate on which the wall surface of the through hole has been processed is floated on melted solder (Pb-Sn alloy) with the element forming surface 1a facing upward, and the capillary tube is Utilizing the phenomenon and surface tension, the through hole is filled with Pb-Sn alloy 7, which is cooled and solidified as shown in Fig. 2 (f).
), an input/output terminal 7a having a projecting region above the through hole is formed.
【００１１】なお、半導体基板を溶融した半田上から取
出した際にスルーホール下部にも突出した領域が形成さ
れる。Note that when the semiconductor substrate is taken out from above the molten solder, a protruding region is also formed under the through hole.
【００１２】外部接続用入出力端子を有する半導体装置
を用いた大規模装置の作製
次に図２（ｇ）に示すように上述の入出力端子を有する
Ｉ／Ｏ出力制御用バイポーラチップ１４、ＥＥＰＲＯＭ
チップ１５、マスクＲＯＭチップ１６、ＳＲＡＭチップ
１７、ＣＰＵチップ１８及びＣＣＤチップ１９を作製し
てセラミックパッケージ１２上に絶縁体のヒートシンク
１３を介して順に積層し、突出した領域を有する入出力
端子７ａを介して接続しワイヤボンド２０で外部端子２
１に接続して大規模装置を作製する。Fabrication of a large-scale device using a semiconductor device having input/output terminals for external connection Next, as shown in FIG.
A chip 15, a mask ROM chip 16, an SRAM chip 17, a CPU chip 18, and a CCD chip 19 are fabricated and stacked in this order on a ceramic package 12 via an insulating heat sink 13 to form an input/output terminal 7a having a protruding area. Connect via wire bond 20 to external terminal 2
1 to create a large-scale device.
【００１３】実施例２
実施例１において、図１（ｄ）に示すように、スルーホ
ール内面のみに接着性金属層（Ｔｉ／Ｗ合金）６を形成
し、更にこの上にぬれ性の金属層（Ｃｕ）を形成する代
わりに接着性金属層（Ｔｉ／Ｗ合金）及びぬれ性金属層
（Ｃｕ）を、図３に示すように半導体基板１の片面のみ
、全面に残しておき、その上面をホトレジスト膜１０で
覆い、電極形成部のみフォトリソグラフィー技術を用い
て該樹脂を取り除いておく。Example 2 In Example 1, as shown in FIG. 1(d), an adhesive metal layer (Ti/W alloy) 6 was formed only on the inner surface of the through hole, and a wettable metal layer was further formed on this. Instead of forming an adhesive metal layer (Ti/W alloy) and a wettable metal layer (Cu), an adhesive metal layer (Ti/W alloy) and a wettable metal layer (Cu) are left on only one side of the semiconductor substrate 1, as shown in FIG. It is covered with a photoresist film 10, and the resin is removed from only the electrode forming portion using photolithography.
【００１４】このような処理をほどこされた半導体基板
をＣｕ溶液（Ｃｕメッキ液）１１に接するように配置し
、前記接着用／ぬれ性の金属層を通じて流す電流により
電気メッキを電極形成用のスルーホール内面に行う。
最終形状として必要とされる突出領域（バンプと称する
もので半導体基板表面より、５〜５０μｍ程度突出する
。）が形成されるまでメッキを行う。得られた半導体基
板は、図４に示すように、半導体基板１と配線用金属プ
ラグ間の熱膨張系数の違いにより生ずる熱応力を緩和す
る為中空の巣９が生じている。ただし５は絶縁層、６は
接着性金属層、８は配線用金属プラグである。このメッ
キによる形成法は、従来のＴＡＢ用のバンプ形成技術を
利用することが出来る。The semiconductor substrate subjected to such treatment is placed in contact with a Cu solution (Cu plating solution) 11, and electroplating is performed by a current flowing through the adhesive/wettable metal layer for electrode formation. Perform on the inside of the hall. Plating is performed until a protruding region (referred to as a bump, which protrudes from the surface of the semiconductor substrate by about 5 to 50 μm) required as the final shape is formed. As shown in FIG. 4, the obtained semiconductor substrate has hollow cavities 9 in order to relieve thermal stress caused by the difference in thermal expansion coefficient between the semiconductor substrate 1 and the wiring metal plug. However, 5 is an insulating layer, 6 is an adhesive metal layer, and 8 is a wiring metal plug. This plating method can utilize conventional bump formation technology for TAB.
【００１５】[0015]
【発明の効果】この発明によれば、従来のそれぞれ専用
の製造工程を用いて生産されるＣＰＵ、マスクＲＯＭ、
ＤＲＡＭ等それぞれ１つの半導体基板からなる独立した
昨日の装置（デバイス）を多数接続でき、大規模装置（
システム）を構成することのできる外部接続用入出力端
子を有する半導体装置及びその製造方法を提供すること
ができる。[Effects of the Invention] According to the present invention, a CPU, a mask ROM,
It is possible to connect a large number of independent devices such as DRAM, each consisting of one semiconductor substrate, and it is possible to connect large-scale devices (
It is possible to provide a semiconductor device having input/output terminals for external connection that can configure a system (system), and a method for manufacturing the same.
【図１】この発明の実施例で作製した半導体装置の説明
図である。FIG. 1 is an explanatory diagram of a semiconductor device manufactured in an example of the present invention.
【図２】この発明の実施例で作製した半導体装置の製造
工程説明図である。FIG. 2 is an explanatory diagram of the manufacturing process of a semiconductor device manufactured in an example of the present invention.
【図３】この発明の実施例で作製した半導体装置の製造
工程説明図である。FIG. 3 is an explanatory diagram of the manufacturing process of a semiconductor device manufactured in an example of the present invention.
【図４】この発明の実施例で作製した半導体装置の製造
工程説明図である。FIG. 4 is an explanatory diagram of the manufacturing process of a semiconductor device manufactured in an example of the present invention.
１ 半導体基板
１ａ 素子形成面
２ レジストパターン
３ エッチング用イオン
４ スルーホール
５ 絶縁層
６ 接着性金属層
７ 溶融金属
８ 配線用金属プラグ
９ 中空の巣
１０ ホトレジスト膜
１１ Ｃｕ溶液
１２ セラミックパッケージ
１３ 絶縁体のヒートシンク
１４ Ｉ／Ｏ出力制御用バイポーラチップ１５ Ｅ
ＥＰＲＯＭチップ
１６ マスクＲＯＭチップ
１７ ＳＲＡＭチップ
１８ ＣＰＵチップ（論理回路）
１９ ＣＣＤチップ
２０ ワイヤボンド
２１ 外部端子1 Semiconductor substrate 1a Element formation surface 2 Resist pattern 3 Etching ions 4 Through hole 5 Insulating layer 6 Adhesive metal layer 7 Molten metal 8 Wiring metal plug 9 Hollow nest 10 Photoresist film 11 Cu solution 12 Ceramic package 13 Insulator Heat sink 14 Bipolar chip for I/O output control 15 E
EPROM chip 16 Mask ROM chip 17 SRAM chip 18 CPU chip (logic circuit) 19 CCD chip 20 Wire bond 21 External terminal
Claims (2)
体基板において、スルーホールの壁面に絶縁層とその上
に接着性金属層を積層し、配線用金属プラグをスルーホ
ールを介してその上部と下部に突出するように設けたこ
とを特徴とする半導体装置。Claim 1: In a semiconductor substrate having a through hole at a predetermined position, an insulating layer is laminated on the wall surface of the through hole and an adhesive metal layer is laminated thereon, and a metal plug for wiring is attached to the upper and lower parts of the through hole through the insulating layer. A semiconductor device characterized by being provided in a protruding manner.
少なくともスルーホールの壁面に絶縁層を形成しさらに
その上に接着性金属層を形成し、必要により前記の壁面
以外の不用の絶縁層と接着性金属層を除去し、次いで、
配線用金属プラグ用の金属の溶融物又は溶液をスルーホ
ールを介してその上、下に突出するようにスルーホール
に導入し、固化さすことによって配線用金属プラグを形
成することからなる半導体装置の製造方法。[Claim 2] A semiconductor substrate having a through hole,
Forming an insulating layer on at least the wall surface of the through hole, and further forming an adhesive metal layer thereon, removing unnecessary insulating layer and adhesive metal layer other than the wall surface if necessary, and then
A semiconductor device in which a metal molten substance or solution for a wiring metal plug is introduced into a through hole so as to protrude above and below through the through hole, and is solidified to form a wiring metal plug. Production method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3131425A JP2622038B2 (en) | 1991-06-03 | 1991-06-03 | Semiconductor device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3131425A JP2622038B2 (en) | 1991-06-03 | 1991-06-03 | Semiconductor device and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04356956A true JPH04356956A (en) | 1992-12-10 |
| JP2622038B2 JP2622038B2 (en) | 1997-06-18 |
Family
ID=15057664
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3131425A Expired - Fee Related JP2622038B2 (en) | 1991-06-03 | 1991-06-03 | Semiconductor device and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2622038B2 (en) |
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| US5424245A (en) * | 1994-01-04 | 1995-06-13 | Motorola, Inc. | Method of forming vias through two-sided substrate |
| WO2000036650A1 (en) * | 1998-12-16 | 2000-06-22 | Seiko Epson Corporation | Semiconductor chip, semiconductor device, circuit board and electronic equipment and production methods for them |
| JP2000196014A (en) * | 1998-12-25 | 2000-07-14 | Texas Instr Japan Ltd | Semiconductor chip and semiconductor device mounted with the semiconductor chip |
| JP2002353223A (en) * | 2001-05-30 | 2002-12-06 | Sony Corp | Semiconductor device and its manufacturing method |
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| EP1248295A3 (en) * | 2001-04-06 | 2005-07-13 | Shinko Electric Industries Co. Ltd. | Semiconductor element, connection structure thereof, semiconductor device using a plurality of such elements and processes for making the same |
| JP2006352171A (en) * | 1998-12-16 | 2006-12-28 | Seiko Epson Corp | Semiconductor chip manufacturing method, semiconductor device manufacturing method, circuit board manufacturing method, and electronic device manufacturing method |
| JP2007520051A (en) * | 2003-09-23 | 2007-07-19 | マイクロン テクノロジー，インコーポレイテッド | Process and integration scheme for manufacturing semiconductor components including conductive components, through vias and conductive through wafer vias |
| JP2008028407A (en) * | 1997-04-04 | 2008-02-07 | Glenn J Leedy | Information processing method |
| JP2009512215A (en) * | 2005-10-13 | 2009-03-19 | インテル・コーポレーション | Integrated microchannel for 3D through silicon architecture |
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-
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|---|---|---|---|---|
| US5424245A (en) * | 1994-01-04 | 1995-06-13 | Motorola, Inc. | Method of forming vias through two-sided substrate |
| JP2011181176A (en) * | 1997-04-04 | 2011-09-15 | Glenn J Leedy | Information processing method and laminated integrated circuit memory |
| JP2008166832A (en) * | 1997-04-04 | 2008-07-17 | Glenn J Leedy | Information processing method |
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| JP2008166831A (en) * | 1997-04-04 | 2008-07-17 | Glenn J Leedy | Information processing method |
| JP2008172254A (en) * | 1997-04-04 | 2008-07-24 | Glenn J Leedy | Information processing method |
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| US6677237B2 (en) | 1998-12-16 | 2004-01-13 | Seiko Epson Corporation | Semiconductor chip, semiconductor device, circuit board and electronic equipment and production methods for them |
| JP2006352171A (en) * | 1998-12-16 | 2006-12-28 | Seiko Epson Corp | Semiconductor chip manufacturing method, semiconductor device manufacturing method, circuit board manufacturing method, and electronic device manufacturing method |
| JP4497147B2 (en) * | 1998-12-16 | 2010-07-07 | セイコーエプソン株式会社 | Semiconductor chip manufacturing method, semiconductor device manufacturing method, circuit board manufacturing method, and electronic device manufacturing method |
| WO2000036650A1 (en) * | 1998-12-16 | 2000-06-22 | Seiko Epson Corporation | Semiconductor chip, semiconductor device, circuit board and electronic equipment and production methods for them |
| JP2000196014A (en) * | 1998-12-25 | 2000-07-14 | Texas Instr Japan Ltd | Semiconductor chip and semiconductor device mounted with the semiconductor chip |
| JP2003503834A (en) * | 1999-06-23 | 2003-01-28 | ギーゼッケ ウント デフリエント ゲーエムベーハー | Semiconductor memory chip module |
| EP1248295A3 (en) * | 2001-04-06 | 2005-07-13 | Shinko Electric Industries Co. Ltd. | Semiconductor element, connection structure thereof, semiconductor device using a plurality of such elements and processes for making the same |
| JP2002353223A (en) * | 2001-05-30 | 2002-12-06 | Sony Corp | Semiconductor device and its manufacturing method |
| JP4717290B2 (en) * | 2001-09-12 | 2011-07-06 | 株式会社フジクラ | Manufacturing method of through electrode |
| JP2003086591A (en) * | 2001-09-12 | 2003-03-20 | Fujikura Ltd | Method for manufacturing through electrode and the electrode |
| JP2007520051A (en) * | 2003-09-23 | 2007-07-19 | マイクロン テクノロジー，インコーポレイテッド | Process and integration scheme for manufacturing semiconductor components including conductive components, through vias and conductive through wafer vias |
| US9287207B2 (en) | 2003-09-23 | 2016-03-15 | Micron Technology, Inc. | Methods for forming conductive vias in semiconductor device components |
| JP2009512215A (en) * | 2005-10-13 | 2009-03-19 | インテル・コーポレーション | Integrated microchannel for 3D through silicon architecture |
| US8395269B2 (en) | 2005-12-02 | 2013-03-12 | Renesas Electronics Corporation | Method of stacking semiconductor chips including forming an interconnect member and a through electrode |
| JP2013084711A (en) * | 2011-10-07 | 2013-05-09 | Denso Corp | Semiconductor device and manufacturing method of the same |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2622038B2 (en) | 1997-06-18 |
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