JPH04356834A - Synchronizing circuit using crc check - Google Patents

Abstract

PURPOSE:To reduce a circuit scale without requiring parallelly developed protecting circuits even in the case of synchronization by parallelly developing received signals and parallelly executing CRC checks for the plural signals. CONSTITUTION:CRC arithmetic/comparison circuits 6-8 parallelly arranged to the parallelly developed signals execute the arithmetic of CRC, compare the arithmetic result with a CRC bit and output match detection signals, and a selecting circuit 9 previously sets priority for the match detection signals outputted by the respective CRC arithmetic/comparison circuits 6-8 as mentioned above. When more than two match signals are simultaneously outputted from the above-mentioned CRC arithmetic/comparison circuits 6-8, one match detection signal as mentioned above is selected in the order of priority set in advance. Therefore, the synchronizing circuit using the CRC check can be obtained to reduce the circuit scale without requiring parallelly developed protecting circuits 11.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronization circuit that synchronizes received signals in a digital communication device, and more particularly to a synchronization circuit that synchronizes received signals using a CRC check from parallel expanded signals.

0002

2. Description of the Related Art Conventionally, there has been a device of this type as shown in FIG. This figure is from IEICE Technical Report SAT89-4
1 (written by Toyoshima, Kan, and Hideo Tatsuno: Study of cell synchronization circuit configuration method due to header error), and in the figure, 1
is a serial/parallel conversion circuit, 2 is a frequency divider circuit, 3 to 5 are flip-flops, 6 to 8 are CRC calculation/comparison circuits, 10, 14,
15 is a coincidence detection circuit, 11, 16, 17 are protection circuits, 1
8 is an AND circuit, 12 is an inhibit circuit, and 13 is a frame counter.

Next, the operation will be explained. The serial-to-parallel conversion circuit L expands the input signal into n parallels, and the frequency division circuit 2
Divide the frequency of the input clock by n. The L flip-flops 3 to 5 delay the n signals developed in parallel to generate a total of {n×(L+1)} parallel signals. The n CRC computation/comparison circuits 6 to 8 each have {n×(L
+1)} signals expanded in parallel, a CRC calculation is performed on specific m signals each containing one bit, and a match is detected by comparing the calculation result with the CRC bit. The detection signal is separately applied to n coincidence detection circuits 10, 14, and 15, and compared with the detection timing signal output from the frame counter 13.

If the detection signals from the CRC calculation/comparison circuits 6 to 8 match the detection timing signals, the match detection circuit 1
0, 14, and 15 are determined to have detected a synchronization signal,
The n protection circuits 11, 16, and 17 maintain the same state when the synchronization is established, and when the synchronization is not established, the synchronization is established when a coincidence is detected six times in a row. I judge that.

[0005] Also, if the above timings do not match,
This is a case where a synchronization signal is not detected at all, or a synchronization signal is detected at a timing different from normal, and the n protection circuits 11, 16, and 17 detect a discrepancy, for example, seven times in a row while the synchronization is established. When, inhibit circuit 1
Output an inhibit signal to frame counter 1
Disable the clock input to 3.

Therefore, this synchronous circuit converts the input signal into n
Synchronization is achieved by expanding the signals in parallel, performing n CRC checks on the signals in parallel, and applying protection to each of the n coincidence detection signals.

[0007]

[Problem to be Solved by the Invention] Since the conventional synchronous circuit using the CRC check is configured as described above,
When synchronizing received signals by expanding them in parallel, the probability of false pattern matching due to a bit string that partially includes CRC bits near the synchronization position is very high, so it is necessary to reduce the probability of false synchronization using the protection circuit output. Ta. Therefore, a protection circuit corresponding to the number of parallel expansions is required, resulting in a problem that the circuit scale increases.

The present invention was made to solve the above-mentioned problems, and even when input signals are expanded in parallel and synchronized, protection circuits for the number of parallel expansions are not required.
The object of the present invention is to obtain a synchronous circuit using a CRC check that can reduce the circuit scale.

[0009]

[Means for Solving the Problems] Synchronization using a CRC check according to the present invention is performed in a synchronization circuit that synchronizes a plurality of parallel signals expanded in parallel by performing CRC checks on the plurality of parallel signals. Multiple CRs are arranged in parallel depending on the number of CRs, each performs CRC calculations on multiple parallel signals, and a match is detected by comparing the calculation results and CRC bits.
The present invention is equipped with a C calculation/comparison circuit and a selection circuit that sets priorities in advance for the coincidence signals output from each of the CRC calculation/comparison circuits and selects and outputs one coincidence detection signal in order of priority. It is constructed using a characteristic CRC check.

0010

[Operation] In the present invention, a plurality of CRC calculation/comparison circuits arranged in parallel perform CRC calculations on signals developed in parallel, compare the calculation results with CRC bits, and generate a coincidence detection signal. output, and the selection circuit selects each of the above CRs.
Priorities are set in advance for the coincidence detection signals output by the C calculation/comparison circuits, and if two or more of the above-mentioned CRC calculation/comparison circuits output coincidence detection signals at the same time, 1 The two coincidence detection signals are selected and output.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram showing an embodiment of the present invention, in which numerals 1 to 8 and 10 to 13 are the same as the conventional device shown in FIG. In the figure, 1 is a serial-to-parallel conversion circuit;
2 is a frequency divider circuit, 3 to 5 are flip-flops, and 6 to 8 are C
RC calculation/comparison circuit, 9 a selection circuit, 10 a coincidence detection circuit, 11 a protection circuit, 12 an inhibit circuit, and 13 a frame counter.

Next, the operation will be explained. The serial-to-parallel converter circuit 1 expands the input signal into n parallels, and the frequency divider circuit 2
Divide the frequency of the input clock by n. The L flip-flops 3 to 5 delay the n signals developed in parallel to generate a total of {n×(L+1)} parallel signals. The n CRC computation/comparison circuits 6 to 8 each have {n×(L
+1)} signals expanded in parallel, a CRC calculation is performed on specific m signals each containing one bit, and a match is detected by comparing the calculation result with the CRC bit.

The selection circuit 9 assigns priorities in advance to the n coincidence detection signals outputted from the n CRC calculation/comparison circuits 6 to 8, and during the synchronization pull-in operation, selects two or more coincidence detection signals. When signals are detected at the same time, one detection signal is selected according to its priority, and in the state before synchronization establishment or in the synchronization establishment state, n CRC calculation/comparison circuits 6 to 6 selected during the synchronization pull-in operation are selected. Only the coincidence detection signal from one of the 8 CRC calculation/comparison circuits is output.

The detection signal selected by the selection circuit 9 is applied to a coincidence detection circuit 10 and compared with a detection timing signal output from a frame counter 13. If the detection signal from the selection circuit 9 and the detection timing signal match,
The coincidence detection circuit 10 determines that a synchronization signal has been detected, and the protection circuit 11 maintains the same state when synchronization is established, and continuously performs synchronization during synchronization pull-in operation or before synchronization is established. It is determined that synchronization has been established when a match is detected, for example, six times.

[0015] Also, if the above timings do not match,
This is the case when the synchronization signal is not detected at all, or when the synchronization signal is detected at a timing different from normal, and the protection circuit 11 sends an inhibit signal to the inhibit circuit 12 when a mismatch is detected seven times in a row in the synchronization established state. A signal is output to inhibit the clock input to the frame counter 13.

Therefore, this synchronous circuit converts the input signal into n
Synchronization is achieved by expanding the signals in parallel, performing CRC checks on n signals in parallel, selecting one coincidence detection signal from each of the n coincidence detection signals in order of priority, and applying protection. FIG. 2 is a timing diagram showing operations in the coincidence detection circuit 10 and the protection circuit 11 when the selection circuit 9 selects coincidence detection signals output from n CRC calculation/comparison circuits 6 to 8. .

[0017]

[Effects of the Invention] As described above, according to the present invention, a plurality of CRC calculation/comparison circuits arranged in parallel perform CRC calculations, compare the calculation results with CRC bits, and output a coincidence detection signal. , the selection circuit sets a priority in advance for the coincidence detection signals output from each of the above-mentioned CRC calculation/comparison circuits, and when coincidence detection signals are outputted from two or more of the above-mentioned CRC calculation/comparison circuits at the same time, Since one of the coincidence detection signals is selected and output in the order of the set priority, even when input signals are expanded in parallel and synchronized, protection circuits for the number of parallel expansions are not required, making it possible to reduce the circuit scale. This has the effect that a synchronous circuit using a CRC check can be obtained.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a timing diagram showing the characteristic operation of the above embodiment.

FIG. 3 is a block diagram showing a conventional device.

[Explanation of symbols]

1 Serial to parallel conversion circuit 2 Frequency divider circuit 3 Flip-flop 4 Flip-flop 5 Flip-flop 6 CRC calculation/comparison circuit 7 CRC calculation/comparison circuit 8 CRC calculation/comparison circuit 9 Selection circuit 10 Coincidence detection circuit 14 Coincidence detection circuit 15 Coincidence detection circuit

Claims (1)

[Claims] Claim 1: In a synchronizing circuit that synchronizes a plurality of parallel signals developed in parallel by performing CRC checks in parallel, a plurality of parallel signals are arranged in parallel according to the number of parallel signals, and each of the plurality of parallel signals is A CRC calculation/comparison circuit that performs a CRC calculation and compares the calculation result with the CRC bits to detect a match, and a priority is set in advance for the match signal output from each CRC calculation/comparison circuit. 1 in order
A synchronous circuit using a CRC check, comprising: a selection circuit that selectively outputs two coincidence detection signals.