JPH04355562A - Read circuit for image sensor - Google Patents

Abstract

PURPOSE:To provide the sensor with high resolution while its read speed quickened by delaying a timing of integration start of an integration device from a leading of a drive pulse fed to a light receiving element. CONSTITUTION:The read circuit consists of a linear image sensor 10, an incomplete integration device 20, a leakage recovery circuit 30 and a delay circuit 50. Moreover, the delay circuit 50 is made up of a delay line 51 delaying a clock CK and a JK flip-flop 52 receiving the delay clock and outputting a switching pulse switching reset switches 35, 36. Then an output in response to a pattern projected on a light receiving element line is obtained even when the integration time is decreased by delaying the integration start time from the leading of the drive pulse used to read a picture signal from each light receiving element 11 by a prescribed delay time resulting in reducing a time of a high level of the drive pulse.

Description

[Detailed description of the invention]

0001

[Field of Industrial Application] The present invention relates to a reading circuit for an image sensor used for reading images of facsimile machines and image scanners, and in particular, the present invention relates to a reading circuit for an image sensor used for reading images of facsimile machines and image scanners. The present invention relates to a reading circuit for an image sensor in which a plurality of elements are arranged in a line.

0002

2. Description of the Related Art An image sensor used for reading an image in a facsimile machine, for example, uses a light-receiving element line of approximately the same length as the width of the document, and receives an image signal of one line of the document surface by electrical scanning in the line direction. At the same time as reading, the document is moved by the document feeder (in the sub-scanning direction), and the electrical scanning is sequentially performed to read the entire surface of the document. In this type of image sensor, for example, as shown in FIG. 4, a photodiode PD and a blocking diode BD are connected in series so as to have opposite polarities to form one receiving element 61. A configuration in which a plurality of 61 are arranged one-dimensionally in a line has been proposed.

[0003] Reading of the image signal of the image sensor is carried out as follows. That is, the already charged photodiode PD is irradiated with reflected light from the document surface (not shown), and a photocurrent proportional to the amount of the irradiated light flows into the anode side of the photodiode PD.
The charges accumulated in the photodiode PD are discharged (accumulation period). Subsequently, a drive pulse is applied to the anode side of the blocking diode BD via the individual drive line 62 by the shift register SR, and the blocking diode B
D is forward biased to reset the cathode voltage across the diode to a substantially constant value (signal read period). Therefore, the same amount of charge as the positive charge of the cathode electrode flowing out as a photocurrent during the accumulation period is replenished (charged) from the outside by the signal reading operation. The supplementary amount of this charge is applied to the common signal line 6.
By detecting the voltage as a voltage with an integrator 64 via 3, an image signal output can be obtained. The above operation is performed for each light receiving element 61 every time a driving pulse is sequentially applied from each terminal of the shift register SR, and an image signal of one line on the document can be obtained in time series.

0004

[Problem to be solved by the invention] Each light receiving element 61 in FIG.
(n), 61(n+1), 61(n+2), 61(n+
Regarding 3), consider the case where reflected light from the charts 70 arranged in white, black, white, black along the main scanning direction is incident so as to correspond to each of the light receiving elements. The timing at which the integrator 64 starts integrating in the above reading circuit is determined by a reset pulse that opens and closes the reset switch 65. According to the conventional reading circuit, this reset pulse is given at the same timing as the rising edge of the clock CK input to the shift register SR, as shown in FIGS. 5(a) and 5(h).

However, at the above timing, the integrator 6
4, the clock CK is activated for high-speed reading.
When the cycle is shortened, an integral waveform as shown in FIG. 5(i) is output for the black and white chart 70. Therefore, according to this integral waveform, V(n), V(n+1),
There was a problem that V(n+2) and V(n+3) were approximately the same, and the black and white pattern of the chart 70 could not be separated. This corresponds to each drive pulse S(
n) to S(n+3) to light receiving elements 61(n) to 61(n+
3), the common signal line 6 on the input side of the integrator 64
This is considered to be due to the fact that, as shown in the current waveform of FIG. 5(g), a current I whose current value is continuous at the black and white boundary of the chart 70 is generated.

The present invention has been made in view of the above-mentioned circumstances, and provides an image sensor in which a plurality of light-receiving elements each consisting of two diodes connected in series with opposite polarities are arranged in a line. It is an object of the present invention to provide a reading circuit that can ensure sufficient resolution even if the reading speed is increased.

[0007]

[Means for Solving the Problems] In order to solve the problems of the above-mentioned conventional example, an image sensor reading circuit according to the present invention has the following features:
An image sensor comprising a plurality of light receiving elements arranged in a line, each consisting of two diodes connected in series with opposite polarities, and a driving means for sequentially applying a driving pulse to one end of each of the light receiving elements. , a reading circuit for an image sensor having a common signal line that connects the other end of each of the light receiving elements in common, and an integrator connected to the common connection line, the timing of the start of integration of the integrator is set according to the light receiving It is characterized by providing a phase advance circuit or a phase delay circuit that lags behind the drive pulse applied to the element.

[0008]

[Operation] According to the present invention, the output of the integrator is projected onto the light receiving element even when the integration time is shortened by delaying the timing of the start of integration of the integrator from the rising edge of the drive pulse applied to the light receiving element. It can be made to correspond to the pattern.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the image sensor reading circuit of the present invention will be described with reference to the drawings. FIG. 1 is an overall configuration diagram of an image sensor reading circuit, which includes a one-dimensional image sensor 10, an incomplete integrator 20, and a leakage regeneration circuit 30.
and a delay circuit (delay circuit) 50.

The one-dimensional image sensor 10 is constructed by connecting a photodiode PD and a blocking diode BD in series with opposite polarities to form a light receiving element 11, and arranging a plurality of these in a line as one pixel. has been done. As shown in FIG. 2, each light receiving element 11 has a lower electrode 2 (for example, formed of a metal film) formed on an insulating substrate 1.
Two semiconductor layers 3a and 3b made of amorphous silicon in which an n-layer and an i-layer are laminated are separately formed on top, and upper electrodes 4a and 4b are formed on these semiconductor layers 3a and 3b, respectively.
By stacking the photodiode PD and the blocking diode BD (formed, for example, of a transparent conductive film), the photodiode PD and the blocking diode BD can be disposed facing each other and connected in series with opposite polarities. The upper electrodes 4a and 4b are connected to the individual drive lines 12 and the common signal line 1 made of aluminum through contact holes 6a and 6b formed in the insulating layer 5.
3 are connected to each other.

Each individual drive line 1 is connected to the anode side of the blocking diode BD constituting each light receiving element 11.
2 is connected to each terminal of the shift register SR. Further, the common signal line 13 connected to the anode side of each photodiode PD is common to each light receiving element. The shift register SR is provided with a data terminal DATA and a clock terminal CK, and a data pulse input from the data terminal DATA is shifted and sequentially output as a drive pulse S(n) from each terminal of the shift register SR. This drive pulse S(n) is applied to each light receiving element 11 via the individual drive line 12, and this drive pulse S(n
) becomes “High”, the sensor output current I corresponding to the photocurrent generated in the light receiving element 11 is transmitted to the common signal line 13.
taken out to the outside.

The imperfect integrator 20 operates as an integrator at high frequencies and as a current-voltage amplifier at low frequencies.
Perfect integrator 22 having an integrating capacitor 21 in the negative feedback section
, a non-inverting amplifier 23 for voltage amplifying the output of the perfect integrator 22, and a resistor 24 connected between the output side of the non-inverting amplifier 23 and the input side of the perfect integrator 22. The perfect integrator 22 has a non-inverting input and an inverting input, the non-inverting input is fixed at a constant potential, and the common connection line 1 of the one-dimensional image sensor 10 is connected to the inverting input side.
3 is connected. Further, the configuration is such that the output voltage divided by the resistors 25 and 26 is input to the non-inverting amplifier 23. Resistor 24 operates to leak capacitor 21 at the output of non-inverting amplifier 23.

The leak regeneration circuit 30 includes capacitors 31 each having one end connected to the output of the non-inverting amplifier 23.
, 32; constant current sources 33, 34 connected to the other ends of the capacitors 31, 32; reset switches 35, 36 connected to the other ends of the capacitors 31, 32; Sample and hold circuits 37 and 38 connected to the end side and this sample and hold circuit 37
, 38, and a multiplexer 41 that integrates two signal output lines 39 and 40 into one system. The constant current sources 33 and 34 are configured to output a current value approximately proportional to the output voltage value of the imperfect integrator 20. Further, the reset switches 35 and 36 are connected to the reference power source Vo.
connected to s.

In this leak regeneration circuit 30, one end of the capacitors 31, 32 is driven by the output of the imperfect integrator 20, and the other end of the capacitors 31, 32 is driven by a constant current source 33, connected thereto. 34 compensates for the leakage caused by the resistor 24, and an output obtained by integrating the sensor output current I appears here. After the integration is completed, the reset switches 35 and 36 reset to a constant reference potential (Vos), and the integration starts again. The above-mentioned integration and reset operations are performed using the capacitor 31 (32), constant current source 33 (
34), Since the two sets of circuits of the reset switches 35 (36) perform the operations alternately and complementarily, the leak regeneration circuit 30 can always be set to the integration mode, so it operates with the loss caused by the switching time of the reset switches 35 and 36. Speed is not limited.

The delay circuit 50 is composed of a delay line 51 that delays the clock CK, and a JK flip-flop 52 that inputs the delayed clock and outputs switch opening/closing pulses for opening and closing the reset switches 35 and 36. The length of the delay time in the delay line 51 is configured to be selectable up to 200 nsec in 40 nsec steps. A “High” signal is always applied to the J and K terminals of the JK flip-flop 52, and a clock CK is applied to the CK terminal of the JK flip-flop 52.
The output Q is inverted every time . Further, the JK flip-flop 52 is provided with a CLR terminal, and the data pulse (
A start pulse) is applied to the CLR via an inverter 53.
By being applied to the terminal, the output Q of the JK flip-flop 52 is set to "Lo" every time the shift register SR starts.
Clear to "w".

Next, an integral waveform obtained by the circuit having the above configuration will be explained with reference to FIG. Each light receiving element 11(n), 11(n+1), 11(n+2), 11(
n+3), when the reflected light from the charts arranged in white, black, white, black along the main scanning direction so as to correspond to each of the light receiving elements is incident, that is, every other light receiving element 11 Consider the case where light is incident on . When a data pulse (High) is input to the shift register SR,
Drive pulses S(n) that become "High" are sequentially output from the output terminal of the shift register SR in response to the clock CK. In this driving pulse S(n), the shift register SR
power supply voltage is output. Furthermore, the shift register S
In R, CMOS is used instead of bipolar because the "High" level and "Low" level must strictly match.

When the driving pulse S(n-1) becomes "Low" and the driving pulse S(n) becomes "High", the anode side of the blocking diode BD of the light receiving element 11(n) becomes "High", A current I (sensor output current) flows in the forward direction from the anode side of the photodiode PD. This current I starts increasing little by little for 200nsec.
It reaches its maximum at ~400 nsec. Therefore, if the period of the clock CK is set to about 300 nsec in order to perform high-speed reading, the drive pulse S(n) becomes "L" as shown in FIG.
The current I reaches its peak value when it reaches "ow".

Next, when the drive pulse S(n) becomes "Low" and the drive pulse S(n+1) becomes "High", the photodiode PD constituting the light receiving element 11(n)
The current from the blocking diode BD becomes zero, but the current I continues to flow in the same direction due to the overshoot of the operational amplifier used in the incomplete integrator 20. However, as described in the section of the prior art, during the signal reading period from each light receiving element 11, the light receiving element 1
1(n), the current I
decreases. Subsequently, the drive pulse S(n+1) becomes “Lo
When the current becomes "High" and the drive pulse S(n+2) becomes "High", the current I starts to increase again. In this way, the current increases or decreases depending on the brightness or darkness projected onto the light receiving element line, resulting in a waveform as shown in FIG. 2(g).

On the other hand, a delay line 5 is connected from the output terminal Q and the inverted output terminal Q' side of the JK flip-flop 52.
A delayed clock delayed by a delay time Δt through 1 (Fig. 2
Switch opening/closing pulses as shown in FIGS. 2(i) and 2(j), which are inverted each time (h)) rises, are output, respectively. When the reset switches 35 and 36 are closed while the switch opening/closing pulse is "High", the reference potential Vos is reset, and then when the switch opening/closing pulse is "Low", the reset switch 35
, 36 are opened, and an integration mode is entered in which integration is started from the reference potential Vos. Therefore, the toggle operation of the JK flip-flop 52 is performed every time the switch opening/closing pulse rises and falls (the delay clock rises), and the drive pulse S in the shift register SR
The shift operation (n) is delayed by a delay time Δt. Therefore, the integration start timing is as shown in FIG. 2(k). When integration is performed at the above timing, the integrated waveform becomes as shown in Fig. 2(l), and the output V'(n) corresponds to the pattern projected on the light receiving element line (pattern corresponding to the black and white chart).
, V'(n+1), V'(n+2), and V'(n+3) can be obtained.

According to the above embodiment, by delaying the integration start time by the delay time Δt from the rise of the drive pulse for reading image signals from each light receiving element, the "High" period of the drive pulse is shortened and the integration time is reduced. Even when the period of the clock CK is shortened (the cycle of the clock CK is shortened), it is possible to obtain an output according to the pattern projected on the light receiving element line (a pattern corresponding to the black and white chart), and the image sensor has sufficient resolution. can be ensured.

[0021] The delay time Δt is determined based on the delay from the rise of the drive pulse S(n), which is the output of the shift register SR, to the maximum value of the current I. This is determined experimentally while monitoring the output. Specifically, 180nsec~2
The highest resolution was shown at 00 nsec.

In the above embodiment, by providing the delay circuit (delay circuit) 50, the timing at which the incomplete integrator 20 starts integration is delayed from the drive pulse S(n) applied to the light receiving element 11. , the same effect can be obtained by using a phase advancing circuit.

[0023]

According to the present invention, by delaying the start of integration of the integrator from the rise of the drive pulse applied to the light receiving element, even when the integration time is shortened, the output of the integrator can be transmitted to the light receiving element. It can be made to correspond to the projected pattern. As a result, it is possible to increase the reading speed and obtain a sensor with high resolution.

[Brief explanation of the drawing]

FIG. 1 is an equivalent circuit diagram of a reading circuit of an image sensor showing an embodiment of the present invention.

FIG. 2 is a cross-sectional explanatory diagram of a light receiving element.

FIGS. 3(a) to 3(l) are waveform diagrams for explaining the operation of the reading circuit of the image sensor of this embodiment.

FIG. 4 is an equivalent circuit diagram of a reading circuit of a conventional image sensor.

FIGS. 5A to 5I are waveform diagrams for explaining the operation of a reading circuit of a conventional image sensor.

[Explanation of symbols]

10... One-dimensional image sensor, 11... Light receiving element,
12...Individual drive line, 13...Common signal line, 20
...incomplete integrator, 30...leak regeneration circuit, 35
...Reset switch, 36...Reset switch,
50...Delay circuit (slow phase circuit), 51...Delay line, 52...JK flip-flop

Claims (1)

[Claims] 1. An image sensor comprising a plurality of light-receiving elements arranged in a line, each consisting of two diodes connected in series with opposite polarities, and a driving pulse sequentially applied to one end of each of the light-receiving elements. In a reading circuit for an image sensor, the image sensor has a driving means for applying a voltage, a common signal line that commonly connects the other end of each of the light receiving elements, and an integrator connected to the common connection line. timing,
A reading circuit for an image sensor, comprising a phase advance circuit or a phase delay circuit that lags behind a drive pulse applied to the light receiving element.