JPH04355297A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To reduce a peak of a bit line precharge current of a semiconductor memory for executing serially write and read-out of data, and also, to decrease the current consumption. CONSTITUTION:The semiconductor memory is provided with a column selection transistor 22 connected to a sense amplifier 20, a read-out column address counter 24 for driving successively the column selection transistor 22 in accordance with a read-out control clock RphiCL, and a read-out column address decoder 23, and a precharge transistor 21 connected between a read-out bit line BLRn and a prescribed voltage line Vp. In such a state, to a gate of the precharge transistor 21 connected to a read-out bit line BLRn+2 selected at the timing after one clock or more from a read-out bit line BLRn selected by a read-out control block RphiCL of a certain timing, an output control signal RCn of the read-out column address decoder 23, and only this read-out bit line BLRn+2 is pecharged.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory in which data is serially written or read.

0002

2. Description of the Related Art In general, dual port memories have been developed for screen memories of systems that perform digital processing by AD converting video signals, video memories used for 1H delays, or FIFO memories. This dual port memory serially writes or reads data using a control clock.

FIG. 3 shows a dual port memory constructed from a conventional DRAM.

The memory cell 1 is a so-called three-transistor type dynamic memory cell composed of N-channel MOS transistors, and is composed of a write transistor 2, a read transistor 3, and a memory transistor 4 serving as a capacitor. The information charge is accumulated in the NOS capacitor between the gate electrode and the channel of the memory transistor 4, and data is determined based on the accumulated charge depending on whether the memory transistor 4 is on or off.

The gate of the write transistor 2 of the memory cell 1 is connected to each of the write word lines WWLi (i=1 to X) output from the write row address decoder 5.
The count value of a write row address counter 6 that counts the write row address clock WφROW is applied. Further, the drains of the write transistors 2 are connected to write bit lines BLWj (j=1 to Y), respectively,
A write amplifier 7 and a precharge transistor 8 are connected to each write bit line BLWj. Furthermore, the input of the write amplifier 7 and the data input line DI
A column selection transistor 1 controlled by the output WCj of the write column address decoder 9 is connected between
0 is provided, and the count value of a write column address counter 11 that counts the write control clock WφCL is applied to the write column address decoder 9.

On the other hand, the gate of the read transistor 4 of the memory cell 1 is connected to each read word line RWLi output from the read row address decoder 12. The count value of the read row address counter 13 is applied. Further, the drains of the read transistors 4 are connected to the read bit lines BLRj, and each read bit line BLRj is connected to a sense amplifier 14 and a processor.
ditransistor 15 is connected. Further, a column selection transistor 17 controlled by the output RCj of the read column address decoder 16 is provided between the sense amplifier 14 and the data output line DOUT, and the read column address decoder 16 counts the read control clock RφCL. The count value of the read column address counter 18 is applied.

In FIG. 3, when reading data, one pulse of the read row address clock RφROW is applied to advance the count of the read row address counter 13 and select one of the read word lines RWLi. Then, as shown in FIG. 4, by applying the read control clock RφCL and causing the read column address counter 18 to count, the read column address decoder 16 sequentially selects the column selection transistors 17. As a result, the data of the memory cell 1 transmitted to the read bit line BLRj is serially outputted to the data output line DOUT via the sense amplifier 14 and the column selection transistor 17. Here, the precharge clock *φRP is the read control clock RφC
The precharge transistor 15 is turned on during the period between the data output periods, and each read bit line BLRj is precharged to the precharge voltage VP.

Data writing is performed in the same manner as reading, and the write row address clock WφROW
Apply one pulse to write low address counter 6.
, and selects one of the write word lines WWLi. By applying the write control clock WφCL and write data in synchronization, the write column address counter 11 performs counting, and the write column address decoder 9 sequentially selects the column selection transistors 10 according to the counted value. This results in
Write data is supplied to the write bit line BLWj via the selected column selection transistor 10 and the write amplifier 7. At this time, the write control clock W
A precharge clock *φWP having a phase opposite to φCL turns on the precharge transistor 8 during a period between data read periods, and each write bit line BLWj
The precharge voltage VP is precharged.

According to the dual port memory shown in FIG. 3, data can be written and read independently and asynchronously, and data can be written and read serially.

0010

[Problem to be Solved by the Invention] However, according to the dual port memory shown in FIG.
In the period between the data transfer periods of φCL or read control clock RφCL, the write bit line B
Since all of the precharge transistors 8 or 15 of LWi or the read bit line BLRj are turned on, the peak current becomes large, causing noise due to fluctuations in the power supply voltage, and the current consumption becomes large.

[0011]

[Means for Solving the Problems] The present invention has been created in view of the above-mentioned points, and includes a word line that is selected according to address data and a signal that is transmitted according to write data or stored data. a memory cell arranged at the intersection of the word line and the bit line, a sense amplifier connected to the bit line, a column selection transistor connected to the sense amplifier, and a memory cell arranged at the intersection of the word line and the bit line. The column address means for selecting the column selection transistor includes column address means for sequentially driving the column selection transistors according to a control clock, and precharge transistors each connected between the bit line and a predetermined voltage line. The output is connected to the gate of the precharge transistor connected to the bit line corresponding to the column selection transistor selected at a timing delayed by at least one clock from the timing of the control clock at which the output is selected. The company provides semiconductor memory.

0012

[Operation] According to the above means, when the column address means sequentially selects one of the column selection transistors based on the control clock, the signal controlling the column selection transistor is sent at a timing delayed by at least one clock of the control clock. Since the precharge transistor connected to the bit line corresponding to the selected column selection transistor is turned on, only that bit line is precharged to the precharge voltage. As a result, all the bit lines are not precharged at once, but one by one is precharged prior to bit line selection, resulting in a reduction in peak current and current consumption.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a partial block diagram showing an embodiment of the present invention, showing the structure of precharging a read bit line, and omitting the same structure as FIG. 3.

The memory cell 19 is a three-transistor type dynamic memory cell having the same configuration as the memory cell 1 shown in FIG. and read bit line BL
Connected to Rj. A sense amplifier 20 is connected to each read bit line BLRj, and a precharge transistor 2 is connected between the read bit line BLRj and the precharge voltage VP.
1 is connected. Further, a column selection transistor 22 controlled by a control signal RCj of a read column address decoder 23 is provided between the output of each sense amplifier 20 and the data output line DOUT. The output of the read column address counter 24 is applied to the read column address decoder 23, and the read control clock Rφ
As the count value of CL increases, the output RCj of the read column address decoder 23 is sequentially selectively output.

The present invention is characterized in that the control signal RCj for controlling each column selection transistor 22 is selected at a timing one or more clocks later than the timing of the read control clock RφCL at which each column selection transistor 22 is selected. The voltage is applied to the gate of the precharge transistor 21 corresponding to the column selection transistor 22. That is, in this embodiment, for example, the control signal RCn-1 of the read column address decoder 23 is applied to the sense amplifier 2 of the read bit line BLRn-1.
is applied to the gate of the column selection transistor 22 connected to 0 and simultaneously inverted via the inverter 25,
Sense amplifier 20 for read bit line BLRn+1
is applied to the gate of the precharge transistor 21 of the column selection transistor 22 connected to the column selection transistor 22 . Similarly, the control signal RCn is applied to the column selection transistor 22 connected to the sense amplifier 20 of the read bit line BLRn.
At the same time, it is inverted via the inverter 25 and applied to the gate of the precharge transistor 21 of the column selection transistor 22 connected to the sense amplifier 20 of the read bit line BLRn+2.

Next, the operation will be explained with reference to FIG.

When the read control clock RφCL is applied to the read column address counter 24, if the control signal RCn-1 of the read column address decoder 23 is output, the read word line RWLi is selected and the read bit line BLRn-1 is output. The data Dn-1 of the memory cell 19 transmitted to the sense amplifier 20
and is output to the data output line DOUT via the column selection transistor 22. At the same time, control signal R
A precharge transistor 2 connected to the read bit line BLRn+1 to which an inverted signal of Cn-1 is applied.
1 is turned on, and only the read bit line BLRn is precharged to the precharge voltage VP.

Next, the read control clock RφCL becomes 1.
When the clock is input, the control signal RCn is output, and the read data Dn is output to the read bit line BLRn.
is outputted to the data output line DOUT via the sense amplifier 20 and column selection transistor 22. Furthermore,
The precharge transistor 21 connected to the read bit line BLRn+2 to which the inverted signal of the control signal RCn is applied turns on, and the read bit line BLRn+
2 is precharged to the precharge voltage VP.

In this way, the read bit line B selected by the currently applied read control clock RφCL
Only the read bit line BLRn+1 selected two clocks after LRn is precharged, and each time a clock pulse of the read control clock RφCL is applied,
Precharged read bit line BLRn+2
proceed sequentially.

Therefore, the read bit line BLRn is not precharged during the data transfer period of the read control clock RφCL, and only the read bit line BLRn+2 is precharged during the data transfer period. Precharge current peaks are eliminated, reducing current consumption.

Although the description of the precharging of the write bit line BLWj is omitted in FIG. 1, the same effect can be obtained by using the same configuration as the precharging of the read bit line BLRj.

[0022]

As described above, according to the present invention, only the bit lines selected at a timing delayed by at least one clock pulse from the timing of the control clock RφCL applied to the column address counter are precharged. There is no current peak, and noise generation due to a drop in power supply voltage is suppressed. In addition, each bit line is precharged only once while all memory cells connected to one word line are selected, which greatly reduces precharge current, making semiconductor memory with low current consumption possible. is realized.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a timing diagram illustrating the operation of the block diagram shown in FIG. 1;

FIG. 3 is a block diagram showing a conventional example.

FIG. 4 is a timing diagram illustrating the operation of the conventional example shown in FIG. 3;

[Explanation of symbols]

19 Memory cell 20 Sense amplifier 21 Precharge transistor 22
Column selection transistor 23 Read column address decoder 24 Read column address counter 25 Inverter

Claims (3)

[Claims] 1. A word line selected according to address data, a bit line to which a signal according to write data or stored data is transmitted, and a memory cell arranged at each intersection of the word line and the bit line. , a sense amplifier connected to the bit line, a column selection transistor connected to the sense amplifier, a column address means for sequentially driving the column selection transistor according to a write or read control clock, and a column address means for sequentially driving the column selection transistor in accordance with a write or read control clock; and precharge transistors each connected between predetermined voltage lines, and the output of the column address means for selecting the column selection transistor is delayed by at least one clock from the timing of the control clock at which the output is selected. A semiconductor memory characterized in that the semiconductor memory is connected to a gate of the precharge transistor connected to the bit line corresponding to the column selection transistor selected at a timing. 2. The column address means includes a column address counter that counts the control clock, and a column address decoder that drives one of the column selection transistors based on the output of the column address counter. Each output of the decoder is connected to the gate of the corresponding column selection transistor, and the bit corresponding to the column selection transistor is driven at a timing delayed by at least one clock from the timing of the control clock at which the column selection transistor is driven. 2. The semiconductor memory according to claim 1, further comprising driving a gate of a line precharge transistor. 3. A write word line selected according to write address data, a read bit line to which a signal according to the stored data is transmitted, and a memory arranged at each intersection of the read word line and the read bit line. a cell, a sense amplifier each connected to the read bit line, a column selection transistor connected to the sense output of the sense amplifier, a column address means for sequentially driving the column selection transistor according to a read clock, and the read bit line. The column address means includes precharge transistors each connected between a bit line and a predetermined voltage line, and the output of the column address means for selecting the column selection transistor is at least one clock from the timing of the control clock at which the output is selected. A semiconductor memory characterized in that the semiconductor memory is connected to the gate of the precharge transistor connected to the read bit line corresponding to the column selection transistor selected at the delayed timing.