JPH043516A - Inverting circuit - Google Patents

Abstract

PURPOSE:To prevent deterioration in the yield in the electric characteristic inspection of ICs by connecting a gate of a 2nd N-channel transistor(TR) and a source of a 1st P-channel TR and extracting an output from a connecting point between a drain of a 2nd P-channel TR and a drain of a 1st N-channel TR. CONSTITUTION:A 2nd P-channel TR is connected between a source 5 of a p-channel TR 1 of an inverter and a power supply line 7, a 2nd N-channel TR is connected between a source 4 of an N-channel TR 2 and a ground line 6, a gate of the 2nd N-channel TR is connected to a source of the 2nd P-channel TR and a gate of the 2nd P-channel TR connects to the source of the 2nd N-channel TR. Thus, the effect of noise onto VDD and GND is hardly caused. Thus, deterioration in performance and malfunction due to noise onto VDD and GND in the electric characteristic inspection of ICs is prevented by an IC tester.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an inverting circuit (hereinafter referred to as an inverter) used in a semiconductor integrated circuit (hereinafter referred to as an IC).

[Conventional technology]

In conventional ICs, in order to obtain a power voltage with the opposite phase to the input voltage, a P-type field effect transistor (as shown in Fig. 2) is used.
An inverter was used in which an N-type transistor 2 (hereinafter abbreviated as a transistor) and an N-type transistor 2 were connected in series between a power supply line 7 and a connection line 6.

[Problem to be solved by the invention]

Recently, the area of IC chips has become larger, and the power lines (hereinafter referred to as VD) and ground wires (hereinafter referred to as GND) within the chip have become longer, and the resistance of V9 and GND themselves has become larger. . In addition, since it has a large number of output circuits, if many output circuits are turned on at the same time, a large current will flow from VDD and also to GND, which will generate noise in VDD and GND itself. In testing the electrical characteristics of ICs, yields have been reduced due to performance deterioration or malfunctions.

This will be explained in more detail using FIGS. 2, 3, and 4. In the inverter shown in FIG. 2 described above, when vD noise shown in FIG. 3 occurs on VDD7, the difference between vnb and the voltage v1 (input high level voltage) applied to the gate terminal 3 is based on 7. Then, by adding noise voltage v2 to VDD and subtracting vl from it, V 3 = V Dn +
V 2 V 1, and the difference increases by the noise voltage. Therefore, depending on the magnitude of the noise voltage v2, the high level voltage applied to the gate terminal 3 becomes a low level voltage, and the low level voltage is applied to the output terminal 8. Instead, a high level voltage is output. Similarly, GND6 is connected to the GN shown in Figure 4.
When D noise occurs, the voltage applied to the gate terminal 3 will be V4 (input low level voltage) and V5 with reference to 6.
(GND noise voltage) becomes V6 = V4 + V, and the potential difference increases by the noise voltage. Therefore, depending on the magnitude of the noise voltage v5, the low level voltage applied to the gate terminal 3 becomes a high level voltage. , a low level voltage is outputted to the output terminal 8 instead of a high level voltage, and like the former, there is a drawback that performance deteriorates or malfunction occurs in some cases.

[Means to solve the problem]

The present invention connects a second P-type transistor between the source terminal 5 of the P-type transistor 1 and the power supply line 7 of the inverter shown in FIG. A second N-type transistor is connected between the ground line 6, a gate terminal of the second N-type transistor is connected to a source terminal of the second P-type transistor, and a gate terminal of the second N-type transistor is connected to the second P-type transistor. The main point is to connect the gate terminal of the second P-type transistor to the source terminal of the second N-type transistor.

〔Example〕

FIG. 1 shows an embodiment according to the present invention. Compared to the conventional example explained in FIG. The drain/source terminal of the second N-type transistor 10 is connected between the line 6, the node terminal of the second N-type transistor 10 and the source terminal of the second P-type transistor 9, and the The feature is that the gate terminal of the second P-type transistor 9 and the source terminal of the second N-type transistor 10 are connected.

When vnn noise as shown in FIG. 3 occurs at VDD7 in FIG. 1, as explained in the conventional example, the difference between the input high voltage applied to the gate terminal 3 and VDD increases by the noise voltage of 72. , equivalently, the conductance g of the P-type transistor 9, a9, the conductance g of the P-type transistor 1
3. becomes larger. On the other hand, since the vnn and vDD noises are directly applied to the gate terminal 12 of the N-type transistor 10, the voltage between the grounding line 6 and the gate terminal 12 is added by the noise voltage 72, equivalently to the N-type transistor 10. Funductance g a. becomes larger. Similarly, when GND noise as shown in Fig. 4 occurs at GND6 in Fig. 1, the difference between the input low voltage applied to the gate terminal 3 and GND increases by the noise voltage V6, equivalently The conductance gm+o of the N-type transistor 10 and the conductance gm2 of the N-type transistor 2 become larger. On the other hand, since GND noise is directly applied to the gate terminal 11 of the P-type transistor 9, the voltage between the power supply line 7 and the gate terminal 11 is added by 76 noise voltages, which equivalently increases the conductance of the P-type transistor 9. Increase g1. P
If the conductance of type transistor 1 is g+a+ and the conductance of N type transistor 2 is gm2, then the series conductance of P type transistors 1 and 9 is 1, and the series conductance of N type transistors 2 and 10 is gl g
+se. In order to suppress fluctuations in the logic threshold voltage due to VDD and GND noise, the ratio ratio g is set.

It is best to make sure that it does not change.

Therefore, gml. (gm++gm,)=gm*(g
+20 gmto) In other words, g m lo・g ,,==
If the channel length and channel width are designed so that g van @g at, the fluctuation of the logic threshold voltage due to VDD and GND noise will remain almost unchanged.
In the inverter shown in FIG.
The high level voltage applied to the output terminal 6 is not mistaken as a low level voltage, and the low level voltage is not mistaken as a high level voltage and is correctly transmitted to the output terminal 6.

〔Effect of the invention〕

According to the present invention, by adding one N-type transistor and one P-type transistor, VI) D noise can be reduced.

It can be made less susceptible to the influence of GND noise, and when inspecting the electrical characteristics of ICs using an IC tester, it is possible to prevent performance deterioration and malfunction due to VNN noise and GND noise, and it is possible to improve the inspection yield. It has the effect of contributing to cost reduction.

[Brief explanation of the drawing]

FIG. 1 shows an inversion circuit according to the present invention, and FIG. 2 shows a conventional inversion circuit. Figures 3 and 4 are VDD. This is a drawing for explaining GND noise. In Figures 1 and 2, 1...P-type transistor, 2...N-type transistor, 3...gate terminal, 4...
...Source terminal, 5...Source terminal, 6...
...Ground wire (GND), 7...Power wire (VD)
D), 8... Output terminal, 9... P-type transistor, 10... N-type transistor, 11
...... Gate terminal, 12... Gate terminal, 13... Source terminal, 14... Source terminal In Figures 3 and 4, Vl ...High level voltage applied to gate terminal 3, ■4...Low level voltage applied to gate terminal 4, v2...VDD noise voltage value, ■,・
...GND noise voltage value, v3...VD
Difference between D and v2, V6...sum of v4 and ■. Agent: Susumu Uchihara, patent attorney Figure 1 Figure 3

Claims (1)

[Claims] The drain terminal of the first P-type field effect transistor and the second
The source terminal of the second P-type field effect transistor is connected to the first N field-effect transistor, and the drain terminal of the second P-type transistor is connected to the first
connected to the drain terminal of a type field effect transistor,
The source terminal of the first N-type field effect transistor is
The drain terminal of the second N-type field effect transistor is connected to the drain terminal, the source terminal of the first P-type field effect transistor is connected to the power supply line, and the source terminal of the second N-type field effect transistor is connected to the power supply line. connected to the ground wire, and the first P
The gate terminal of the type field effect transistor and the source terminal of the second N type field effect transistor are connected, and the gate terminal of the second P type field effect transistor and the first N type field effect transistor are connected to each other. the gate terminal of the second N-type field effect transistor is connected to the source terminal of the first P-type field effect transistor; An inverting circuit characterized in that it has a configuration in which an output is taken out from a connection point between a drain terminal of a transistor and a drain terminal of the first N-type field effect transistor.