JPH04345021A - Method for manufacturing compound semiconductor device - Google Patents

Abstract

PURPOSE:To realize a reduction of a semiconductor manufacturing process using a compound semiconductor and the stabilization of an annealing process. CONSTITUTION:An insulative film 15 for annealing use and a conductive film 14 for annealing use are used as a film for annealing use and after an annealing process ends, the film 14 is not all removed and is utilized for a wiring and a resistor of a semiconductor integrated circuit. Moreover, films, whose stresses have a film quality directly opposite to each other in TENSILE and COMPRESS IBLE, are combined with each other and deposited as a film for annealing use and the improvement of the adhesion of a semiconductor at the time of annealing to the films for annealing use is made possible.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing compound semiconductor field effect transistors and integrated circuits.

0002

2. Description of the Related Art Conventionally, in the manufacturing process of field effect transistors (hereinafter referred to as FETs) using compound semiconductors such as GaAs, a method of forming the active layer of the FET using ion implantation has been widely used. A necessary step in the FET active layer forming method described above is a high temperature heat treatment (hereinafter referred to as annealing) step. Annealing methods include cap annealing, in which an annealing film is deposited before annealing, and then annealing is performed, and capless annealing, in which no annealing film is used.

[0003] Cap annealing will be explained below with reference to FIG. As shown in FIG. 3A, a gate electrode 11 and an ion implantation layer 12 are formed on a GaAs semiconductor substrate 13 using a photolithography process. Next, an annealing film 31 is deposited on the semiconductor surface (FIG. 3(b)). After that, annealing is performed to form the FET active layer (Fig. 3
(c)). Finally, the basic structure of the FET is formed by removing the annealing film 31 (FIG. 4(d)).

0004

[Problems to be Solved by the Invention] Such conventional annealing methods have the following problems. (1) Cap annealing requires a deposition process and a removal process for an annealing film, which lengthens the FET manufacturing process. (2) The adhesion between the semiconductor and the annealing film during annealing may have a significant effect on the activation of implanted ions. If the activation of the implanted ions changes, the threshold value and resistance of the FET will change. (3) Capless annealing does not require a long manufacturing process because there is no deposition or removal process for an annealing film;
During annealing, it is necessary to control the vapor pressure outside the semiconductor to prevent evaporation of atoms from inside the semiconductor. It is difficult to control steam pressure, so it is not suitable for mass production. (4) It is necessary to use a gas that is toxic to the human body during annealing, which is also a problem in implementation.

[0005]

[Means for Solving the Problems] In order to achieve the above object, the present invention uses an insulating film and a conductive film as an annealing film, and does not completely remove the above-mentioned annealing film after the annealing process is completed, but instead provides a semiconductor Used for wiring and resistance in integrated circuits. In addition, by depositing a combination of films with opposite film properties such as TENSILE (stretch) and COMPRESSIBLE (compression) as the annealing film, it is possible to improve the adhesion between the semiconductor and the annealing film during annealing. do.

[0006]

[Function] The present invention allows the annealing film to play both the role of wiring and resistance of the semiconductor integrated circuit and the role of stabilizing the activation of implanted ions during annealing by the above-described method. It is possible to simultaneously shorten the process and stabilize FET characteristics and resistance.

[0007]

Embodiment An embodiment of the present invention will be described below with reference to FIGS. 1 and 2.

As shown in FIG. 1A, a gate electrode 11 and an ion implantation layer 12 are formed on a GaAs semiconductor substrate 13 using a photolithography process and an ion implantation process. Next, an insulating annealing film 15 and a conductive annealing film 14 are deposited on the surface of the GaAs semiconductor substrate 13 (Fig.
(b)). Thereafter, annealing is performed to activate the ion implantation layer and form the FET active layer 16 (FIG. 1(c)). Next, a photoresist 17 is applied (FIG. 1(d)). A predetermined portion of the photoresist 17 is removed using a photolithography process (FIG. 2(a)). Etching is performed using the photoresist 17 as a mask, and the conductive annealing film 14 is removed except for a predetermined portion (FIG. 2(b)).
). Finally, the photoresist 17 is removed, and the wiring process using the conductive annealing film 14 is completed (FIG. 2(c)).
).

Furthermore, by changing the thickness of the conductive annealing film 14, it is possible to create a film resistor of any size, and the conductive annealing film can be used as it is as a resistor in a compound semiconductor integrated circuit. be able to. A resistor manufactured in this manner has the advantage that it has less variation and can apply a larger electric field to the resistor than a resistor manufactured in a semiconductor by conventionally used ion implantation.

Furthermore, the stress of the insulating annealing film 15 and the conductive annealing film 14 is TENSILE.
It is possible to improve the adhesion between the semiconductor and the annealing film during annealing by depositing a combination of films having opposite film properties, ie, COMPRESSIBLE and COMPRESSIBLE.

It should be noted that the present invention is not limited to the above-mentioned embodiments, and various modifications can be made based on the spirit of the present invention.

0012

[Effects of the Invention] According to the above embodiments, according to the present invention, the annealing film has both the role of wiring and resistance of the semiconductor integrated circuit and the role of stabilizing the activation of implanted ions during annealing. , process shortening in the FET manufacturing process and FET manufacturing process
It is possible to simultaneously stabilize the ET characteristics and resistance.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view of a wiring forming process using an annealing film according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view of a wiring forming process using an annealing film according to an embodiment of the present invention.

FIG. 3 is a cross-sectional view showing a conventional annealing process.

[Explanation of symbols]

11 Gate electrode 12 Ion implantation layer 13 GaAs semiconductor substrate 14 Conductive annealing film 15 Film metal for insulating annealing 16 FET active layer 17 Photoresist

Claims (4)

[Claims] Claim 1: In a high-temperature heat treatment step necessary for forming a field-effect transistor active layer in a field-effect transistor manufacturing process using a compound semiconductor, after depositing two or more types of films on the surface of the compound semiconductor, a high-temperature heat treatment step is performed. A method for manufacturing a compound semiconductor device, characterized by performing the following steps. 2. As the two or more types of films according to claim 1, the first layer is an insulating film and the second layer is a conductive film, and the conductive film described above is directly used as wiring of a compound semiconductor integrated circuit. A method for manufacturing a compound semiconductor device characterized by: 3. In the film structure for high-temperature heat treatment according to claim 1, the first layer is an insulating film, the second layer is a conductive film, and the thickness of the second conductive film is varied and deposited. 1. A method for manufacturing a compound semiconductor device, characterized in that a resistor of a conductive film of an arbitrary size is manufactured by this method, and the conductive film described above is directly used as a resistor of a compound semiconductor integrated circuit. 4. The two or more types of films according to claim 1, wherein the stress of the film is TENSILE (extension) and COMPRES.
A method for manufacturing a compound semiconductor device, characterized in that the adhesion between the compound semiconductor and the above-mentioned film during a high-temperature heat treatment process can be arbitrarily changed by depositing a combination of films having opposite film properties called SIBLE (compression).