JPH04342327A - Synchronizing detection circuit - Google Patents

Abstract

PURPOSE:To provide the cycle of a frame counter from being shifted even when the same pattern as a synchronizing code exists in data while the frame counter reset by the detecting pulse of the synchronizing code is under counting in the cycle of one frame. CONSTITUTION:When a pattern comparator 2 detects the synchronizing code and the detecting pulse is outputted and inputted to a gate circuit 4, the detecting pulse is passed by the gate circuit 4 and inputted to a frame counter 5 and the frame counter 5 is reset. When the frame counter 5 is reset, a gate signal generator 3 impresses a gate signal to the gate circuit 4 so as to inhibit that the detecting pulse is outputted from the gate circuit 4 even when it is inputted from the pattern comparator 2 to the gate circuit 4. Thus, the frame counter 5 is not reset again by a pseudo synchronizing code existent in one frame after it is reset.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal transmission circuit, and more particularly to a synchronization detection circuit.

0002

2. Description of the Related Art Conventionally, when a synchronization code is detected in an out-of-synchronization state, a synchronization detection circuit of this type resets a frame counter using a detection pulse, and calculates the number of times the input signal pattern matches the synchronization code. A protection counter is used to count at the cycle of the frame counter, and if a synchronization code is detected consecutively for a set number of frames or more, a signal indicating the synchronization state is output.

0003

[Problems to be Solved by the Invention] In the above-mentioned prior art, a frame counter that is reset by a synchronization code detection pulse detects a pattern identical to the synchronization code ( If a pseudo synchronization code (pseudo synchronization code) is present, this will be detected and the frame counter will be reset, causing a shift in the period of the frame counter. Since the synchronization code cannot be compared and the synchronization code must be detected again, there is a problem that the synchronization recovery time becomes long.

[0004] An object of the present invention is to prevent a frame counter that is reset by a synchronization code detection pulse from counting the synchronization code even if the same pattern as the synchronization code exists in the data while counting in one frame period. The purpose is to prevent the cycle of the frame counter from shifting.

[0005]

[Means for Solving the Problems] In order to achieve the above object, the present invention provides a pattern comparator into which data multiplexed with synchronization codes is input, outputs a detection pulse to its output terminal, and outputs a detection pulse to a gate circuit. When input, the detection pulse passes through the gate circuit and resets the frame counter by inputting it to the frame counter, and when the frame counter is reset, the gate signal generator resets the frame counter by applying the gate signal to the gate circuit. , even if the detection pulse from the pattern comparator is input to the gate circuit, it is prohibited from being output from the gate circuit, and as a result, after the frame counter is reset, it is reset again by a pseudo synchronization code that exists within one frame. This was done so that it would not happen again.

Further, in the present invention, the pattern comparator to which the data multiplexed with the synchronization code is input outputs a detection pulse at its output terminal, and there is no detection pulse at the position of the carry signal output from the frame counter. In this case, the protection counter counts the number of times, and outputs an out-of-synchronization signal when the set number of frames continues to exceed a certain number, and this signal is supplied to the gate signal generator, and from the gate signal generator to the gate circuit. The detection pulse output from the pattern comparator is input to the frame counter via the gate circuit, and a signal is output that allows the frame counter to be reset.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings. FIG. 1 shows a block diagram of an embodiment of the present invention, FIG. 2 shows waveforms until synchronization occurs, and FIG. 3 shows waveforms until synchronization is restored.

First, referring to FIG. 1, the operation when an out-of-synchronization occurs will be explained.

When data in which a synchronization code is multiplexed is input from an input terminal 1 and a synchronization code is detected by a pattern comparator 2, a detection pulse shown in FIG. 2(a) is output. If there is no detection pulse (a) at the position tm+2 from the carry signal t1 of the frame counter 5 with period T shown in FIG. 2(b), the protection counter 6 counts the number of times as shown in FIG. 2(c1). When the set number of frames continues for m or more, a signal indicating out-of-synchronization as shown in FIG. 2(g) is output. This signal is supplied to the gate signal generator 3,
By being applied from the gate signal generator 3 to the gate circuit 4, the detection pulse (
a) is input to the frame counter 5 via the gate circuit 4, a signal for permitting resetting the frame counter 5 is output, and the detection pulse (
Wait for a) to be output.

Next, the operation from the out-of-synchronization state to the return to the synchronization state will be explained.

The pattern comparator 2 detects the synchronization code and outputs the detection pulse shown in FIG.
, the gate circuit 4 converts the detection pulse (a) into (f
) and input it to the frame counter 5 to reset the frame counter 5. When the frame counter 5 is reset, the gate signal generator 3 applies a gate signal to the gate circuit 4, so that even if the detection pulse (a) from the pattern comparator 2 is input to the gate circuit 4, the gate signal generator 3 applies the gate signal to the gate circuit 4. Prohibit output from . This prevents the frame counter 5 from being reset again due to a pseudo synchronization code existing within one frame after it is reset. The frame counter 5 counts at the period T of one frame, checks the output of the pattern comparator 2 at the timing of the carry signal outputted as shown in FIG. 3(b) at the period T, and outputs the detection pulse (a). If not, the gate signal generator 3, which regarded the previous detection pulse as a pseudo synchronization code and prohibited the output of the gate circuit 4, again allows the output of the reset pulse from the gate circuit 4 to the frame counter 5. A gate signal is output as shown in FIG. 3(e). This operation is explained by the carry signal (b) output at a period T.
This is repeated until the detection pulse (a) is output at the timing . If the detection pulse (a) is output at the timing of the carry signal (b), the gate signal generator 3 continues to inhibit the output of the gate circuit 4, so that the frame counter is subsequently controlled by the pseudo synchronization codes f0, f1, f2. 5
is not reset, and the protection counter 6 receives the detection pulse (a) output from the pattern comparator 2 as shown in FIG.
(c2), and when the detected pulses continue for the set number of frames n or more, a signal indicating a synchronized state is outputted to the output terminal 7 as shown in (g) of FIG.

0012

[Effects of the Invention] As explained above, the present invention resets the frame counter and applies a gate signal from the gate signal generator to the gate circuit, thereby allowing the detection pulse to be input from the pattern comparator to the gate circuit. , is prohibited from being output from the gate circuit, so that the effect is obtained that the frame counter is not reset again due to a pseudo synchronization code existing within one frame after being reset.

[Brief explanation of drawings]

FIG. 1 shows a block diagram of an embodiment of the invention.

FIG. 2 is a diagram showing waveforms until synchronization occurs in an embodiment of the present invention.

FIG. 3 is a diagram showing waveforms until the synchronization state is returned again in an embodiment of the present invention.

[Explanation of symbols]

1 Input terminal 2 Pattern comparator 3 Gate signal generator 4 Gate circuit 5 Frame counter 6 Protection counter 7 Output terminal

Claims (2)

[Claims] Claim 1: A pattern comparator input with data multiplexed with synchronization codes outputs a detection pulse to its output terminal,
When input to the gate circuit, the detection pulse passes through the gate circuit and inputs to the frame counter to reset the frame counter, and when the frame counter is reset, the gate signal generator outputs the gate signal to the gate circuit. By adding this, even if the detection pulse from the pattern comparator is input to the gate circuit, it is prohibited from being output from the gate circuit, and this prevents the pseudo synchronization code that exists within one frame after the frame counter is reset. The synchronization detection circuit is prevented from being reset again by 2. A pattern comparator input with data multiplexed with synchronization codes outputs a detection pulse to its output terminal,
If there is no detection pulse at the position of the carry signal output from the frame counter, the protection counter counts the number of times, and when the set number of frames continues for a certain number or more, it outputs an out-of-synchronization signal, and this signal is sent to the gate. The detection pulse output from the pattern comparator is supplied to the signal generator and applied from the gate signal generator to the gate circuit, thereby allowing the detection pulse output from the pattern comparator to be input to the frame counter through the gate circuit and to reset the frame counter. A synchronization detection circuit that outputs a signal.