JPH04340636A - Local cache consistency keeping device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a local cache coherency maintenance device for maintaining the coherence of a cache memory (local cache) corresponding to each CPU in a tightly coupled multiprocessor system.

0002

2. Description of the Related Art A multiprocessor system uses multiple C
This is a system that operates by combining PUs in a predetermined manner. Various types of combinations of CPUs are known. One type of such a system is a system called a tightly coupled multiprocessor system.

FIG. 2 shows an example configuration of a tightly coupled multiprocessor system. In the system shown in this figure, a plurality of (four in the figure) CPUs 10 are connected via an interconnection network 12.
A main storage device 14 is further connected to the interconnection network 12 . Each CPU 10 is provided with a local cache (Lc) 16, and each Lc 16 is provided with a local cache consistency maintenance device (Sn) 18, respectively.

[0004] Lc16 is a cache memory that caches data required by the corresponding CPU 10 from the main storage device 14. Data stored on the main storage device 14 and usable by any CPU 10 is called shared data. Therefore, if some shared data is
When 0 is rewritten, there is a possibility that the shared data to be rewritten is also cached in other Lc16. At this time, the shared data on the other Lc16 is invalidated,
Or, by performing similar rewriting, the L belonging to the system
Need to maintain c16 consistency. The process for realizing this consistency maintenance is called consistency process, and Sn18 is a device that executes this process.

[0005] Consistency processing includes the following processing contents.

For example, when the CPU 10-1 writes to shared data, the corresponding Sn 18-1 writes data to other Sns via the interconnection network 12.
Messages are sent to 18-2, 18-3 and 18-4. This message includes information such as the address of the shared data to be rewritten. This address is main memory 1
It shows the address on 4.

Other Sn18-2, 18-3 and 18-4
When this message is supplied to the Sn 18-2, 18-3, and 18-4 that received the message, the addresses of the data cached in the corresponding Lc 16-2, 16-3, or 16-4, and Compare with the address included in the message. As a result of the comparison, the shared data to be rewritten is Lc16-2, 16-3 or 1.
6-4, the corresponding Sn18-2, 18-3 or 18-4 is L
The shared data cached on c16-2, 16-3 or 16-4 is invalidated or similarly rewritten. This rewriting is performed, for example, using write data sent as a message via the interconnection network 12.

[0008] By operating each Sn18 in this way,
The consistency of Lc16 in the system is maintained, and each CPU 10 can utilize the latest shared data. In addition, in order to avoid sending messages when rewriting shared data that is not cached in other Lc16s, processing efficiency can be improved by adding information such as whether or not it is cached in other Lc16s to the data related to caching. It is suitable for

On the other hand, in such a system, cache replacement is executed as a countermeasure against cache misses. A cache miss refers to an access by the CPU to data that has not been cached.
Cache replacement is executed when access to 6 is made to data that is not cached. Cache replacement refers to the process of fetching cache-missed data from the main storage device 14 to the Lc 16. Typically, cache replacement is performed using a technique called block replacement.

[0010] Block replacement means not only the cache miss data but also the data at the nearby address.
This is a method of importing it into c16. "Nearby" refers to a data group in which the value of a predetermined high-order bit of data that has caused a cache miss is the same, and this data group is a block. Therefore, the size of a block is determined according to the number of bits.

Conventionally, consistency processing and block replacement due to a cache miss are considered to be completely unrelated processes, and when each Sn 18 receives a message for consistency processing, it transfers the shared data indicated by the message to the corresponding Lc 16. is caching, even if it is certain that the latest value of the shared data will be read from main memory to Lc16 by block replacement, it is necessary to invalidate the shared data on Lc16 or do something similar. It was performing processing such as writing.

0012

[Problems to be Solved by the Invention] As described above, in conventional systems, when a predetermined state occurs, consistency processing is performed.
Cache replacement was being performed. However, if a situation in which both processes should be executed occurs at the same time, an unnecessary consistency process may be executed.

That is, the corresponding Lc by a certain CPU
If an access to causes a cache miss, it is necessary to replace the cache, and typically enters a wait state for this purpose. At this time, if the shared data is rewritten by another CPU, the other CPU
A message requesting consistency processing is sent from Sn corresponding to . Conventionally, even when cache replacement was scheduled and the latest shared data was decided to be read into the Lc, consistency processing such as updating was executed in response to this message, resulting in unnecessary consistency. Sexual harassment was sometimes carried out. In other words, unnecessary access to Lc occurs, and CPU
operation stoppage occurred.

[0014] The present invention has been made with the aim of solving such problems, and the present invention has been made with the aim of solving such problems. The purpose is to achieve efficient processing without performing consistency processing when reading the value of shared data after it has been written from main memory.

[0015]

[Means for Solving the Problems] In order to achieve such an object, the Sn of the present invention is configured to automatically transmit the corresponding Lc when a message requesting consistency processing is received from another Sn.
Determine whether or not is waiting for cache replacement,
If it is not in the replacement waiting state, execute consistency processing,
If the block is in the replacement waiting state, the block to be replaced is compared with the address of the written shared data indicated in the message, and if the shared data is included in the block, consistency processing is not executed. Also,
When the shared data indicated by the message is read from the main memory after receiving the message, writing by the CPU corresponding to Sn that sent the message is guaranteed to read the reflected value.

[0016]

[Operation] In the present invention, consistency is not performed if the cache is in a state of waiting for replacement that includes shared data written when a message was sent from another Sn. Therefore, unnecessary consistency processing is reduced.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below with reference to the drawings.

The Sn of the present invention can be applied to a system having the same configuration as the conventional one. Therefore, since it can be applied to a system having the configuration as shown in FIG. 2, for example, the embodiment will be described below assuming that it is used in a system having the same configuration as in FIG. 2 and using the same reference numerals.

FIG. 1 shows the structure of Sn according to an embodiment of the present invention. This Sn18 includes a message transmitter 20, a message receiver 22, a cache controller 24
and an address comparison section 26.

[0020] The message transmitting section 20 has a corresponding CPU
10 executes rewriting of the shared data on the main storage device 14, the message is transmitted at the same time as the rewriting starts or at a predetermined timing thereafter. This ensures that when the shared data indicated by the message is read from the main memory after receiving the message, a value that reflects the writing related to the message will be read. The message receiving unit 22 receives messages transmitted from other Sn18. The address comparison unit 26 compares the address related to rewriting included in the received message and the block address related to cache replacement. The cache control unit 24 accesses the Lc16 when a need for consistency processing or the like arises. It also monitors the cache and CPU, and determines whether the cache is in a state of waiting for replacement.

A feature of this embodiment is that if the need for cache replacement and the need for consistency processing occur at the same time, consistency processing may not be performed. That is, when a message is sent from another Sn, it is determined whether the cache is in a waiting state for replacement or not, and if so, the address comparison unit 26 is used to compare the block address and the address of the shared data. Then, it is checked whether the shared data indicated by the message is included in the block, and if it is, no consistency processing is performed. If not, consistency processing is performed using the same method as before.

As a result, in this embodiment, unnecessary consistency processing is less likely to be performed, and accesses to Lc16 by Sn18 are reduced. Further, when performing consistency processing, the CPU 10 stops operating to prevent the CPU 10 from accessing the Lc 16, but the frequency with which this operation stops occurs is also reduced. Therefore, efficiency and performance of the system are improved.

[0023]

[Effects of the Invention] As explained above, according to the present invention,
Consistency processing is not executed when a block containing written shared data is waiting for cache replacement, and unnecessary Lc accesses are reduced, resulting in improved system performance.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the configuration of a local cache coherency maintenance device according to an embodiment of the present invention.

FIG. 2 is a diagram showing an example configuration of a tightly coupled multiprocessor system.

[Explanation of symbols]

10-1,...10-4 CPU 12 Interconnection network 14 Main storage device 16-1,...16-4 Local cache (Lc)
18, 18-1,...18-4 Local cache coherency maintenance device (Sn) 20 Message transmitter 22 Message receiver 24 Cache controller 26 Address comparator

Claims (1)

[Claims] Claim 1: In a system where shared data on the main memory is buffered by a plurality of local caches and used by the corresponding CPU, a local cache provided for each local cache executes consistency processing. In the cache coherency maintenance device, when the shared data indicated by the message is read from the main memory after the arrival of a message requesting coherence processing, by ensuring that a value that reflects the write related to the message is read, When a message requesting consistency processing is received from another local cache consistency maintenance device, it is determined whether the corresponding local cache is in the cache replacement waiting state, and if it is not in the cache replacement waiting state, the consistency processing is performed. A local cache that executes processing and executes consistency processing when the block to be replaced includes shared data indicated by a message when the block is in a replacement wait state, and executes consistency processing when the block does not include shared data. Consistency maintainer.