JPH04338848A - Tlb substitution system - Google Patents

Abstract

PURPOSE:To improve the performance by limiting the occurrence of TLB substitution and suppressing the occurrence of unnecessary TLB substitution to raise the hit rate with respect to TLB entry contents which should be resident in a TLB on the performance. CONSTITUTION:Each entry of a TLB 51 is provided with a substitution inhibiting flag F designating whether substitution of the entry should be inhibited or not, and a work TLB 52 where address conversion information is temporarily stored is provided in an MMU 5. If the access request from a CPU 1 does not hit the work TLB 52 neither the TLB 51 and the substitution inhibiting flag F of the substitution object entry in the TLB 51 is set, the MMU 5 does not store address conversion information, which is includes the physical address obtained by using an address conversion table 21 on a main memory 2, in the substitution object entry but stores it only in the work TLB 52.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a TLB replacement method in a virtual memory control type information processing system equipped with a TLB (address translation buffer).

0002

2. Description of the Related Art Information processing systems using a virtual memory control method generally include a memory management unit (hereinafter referred to as MMU) that manages access to memory (main memory) and peripheral devices in response to access requests from a CPU or the like using virtual addresses. ) is provided.

[0003] The MMU's main function is to
It has an address conversion function that converts virtual addresses output from etc. into physical addresses. This type of MMU is equipped with a TLB (Transformation Block) in order to perform the above address translation at high speed.
nslation Look-aside Buffe
A caching mechanism called r; address translation buffer) is generally provided.

[0004] The TLB has multiple entries (TLB entries and caching entries). This TLB entry contains the virtual address (virtual page address) when the virtual address from the CPU, etc. is converted to a physical address using the address conversion table (address conversion table consisting of segment tables, page tables, etc.) in main memory. ) and a physical address (physical page address) (referred to as address translation information) is stored.

Now, when an access request using a virtual address is issued from a CPU or the like, the MMU uses the virtual address (
(virtual page address) to search the TLB and search for address translation information having that virtual address.

[0006] If there is a hit in which the target address translation information exists in the TLB (TLB hit), the MMU
The requested access is executed at high speed using the physical address in the address translation information.

On the other hand, the target address translation information is T
In the event of a miss that does not exist in the LB, the MMU performs an address translation operation that translates a virtual address into a physical address using an address translation table on the main memory. Then, the MMU performs so-called TLB replacement (replacement of TLB entries) by expelling the storage contents of the entry to be replaced in the TLB and storing address translation information including the currently generated pair of virtual address and physical address. The entry to be replaced at this time is, for example, LRU (Least Re
It is determined by the ``cently Used'' method.

[0008]

[Problems to be Solved by the Invention] As mentioned above, conventionally, when a TLB miss occurs, TLB replacement (TLB replacement) is always performed.
LB entry replacement) has occurred, and the T to be replaced
The original contents of the LB entry were being evicted. However, depending on the contents of the TLB entry to be replaced,
For example, if address conversion information for devices that need to access continuous areas at high speed, such as peripheral devices such as disk devices, is stored in the replacement TLB entry, the entry contents will be changed unconditionally as before. If this type of device is replaced, there is a problem in that performance deteriorates due to a TLB miss that occurs when accessing this type of device.

[0009] This invention was made in view of the above circumstances, and its purpose is to limit the occurrence of TLB replacement, and to avoid unnecessary TLB replacement for TLB entry contents that should be kept resident in the TLB in terms of performance. An object of the present invention is to provide a TLB replacement method that can suppress the occurrence of errors, increase the hit rate, and improve performance.

0010

[Means for Solving the Problems] The present invention sets a substitution prohibition flag in each entry of a TLB to designate substitution prohibition of the corresponding entry, and also provides address translation information including a pair of a virtual address and a physical address. A work buffer (work TLB) for storing the data is provided separately from the TLB, and in the event of a miss when the virtual address to be accessed does not exist in either the TLB or the work buffer, the virtual address is transferred to the physical address using an address translation table. Address conversion means that converts into an address and address conversion information including a pair of this virtual address and the converted physical address are stored in a work buffer, and the replacement prohibition flag in the replacement target entry of the TLB does not indicate replacement prohibition. Only in cases where the entry is provided with means for performing TLB replacement that stores address translation information including a pair of the virtual address and the translated physical address in the same entry, and the replacement prohibition flag in the replacement target entry indicates that replacement is prohibited. This feature is characterized in that, if there is a change in the entry, replacement of the same entry is prohibited from occurring.

[0011]

[Operation] According to the above configuration, when there is an access request from the CPU or the like using a virtual address, the TLB and work buffer are searched using that virtual address, and if at least one of them is hit, the virtual address and the pair are searched. Since the physical address that was previously stored can be used, the requested access can be performed at high speed.

On the other hand, if there is no hit in either the TLB or the work buffer, the well-known address conversion (
A so-called table walk) is performed to obtain a physical address corresponding to the virtual address to be accessed. This pair of virtual address and physical address is first stored in a work buffer.

At this time, the state of the replacement prohibition flag of the replacement target entry in the TLB is checked. If this replacement prohibition flag does not indicate that replacement is prohibited, TLB replacement (replacement) in which address translation information including the address pair stored in the work buffer is stored in the replacement target entry.
I do. On the other hand, if the replacement prohibition flag of the replacement target entry indicates that replacement is prohibited, replacement of the replacement target entry is prohibited.

[0014] In this manner, when the replacement prohibition flag of the replacement target entry indicates that replacement is prohibited, the replacement target entry is not replaced, and the contents of the replacement target entry can be prevented from being deleted. Therefore, when there is an access request based on the virtual address in the address translation information stored in this entry, the physical address can be obtained immediately, making high-speed access possible.

[0015] Furthermore, even if the entry to be replaced is not replaced, the pair of the physical address and the virtual address to be accessed obtained by the table walk is stored in the work buffer, so it is not evicted from the work buffer. However, if access using this virtual address is requested again, high-speed address translation will be possible.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram showing an embodiment of an information processing system using a virtual storage control method to which the present invention is applied.

In FIG. 1, 1 is a CPU that forms the core of the system, and 2 is a main memory in which various programs, data, etc. are stored. Main memory 2 has a virtual address (virtual page address) and a physical address (physical page address).
A well-known address conversion table 21 consisting of a segment table, a page table, etc. for conversion to . 3a, 3b, . . . are peripheral devices such as disk devices and display devices, and 4 is a cache memory capable of caching using virtual addresses.

[0018] 5 receives an access request from the CPU 1 etc. using a virtual address and accesses the main memory 2 and peripheral devices 3a, 3b.
It is an MMU (memory management unit) that manages access to...

The MMU 5 has a plurality of entries for storing address translation information including pairs of virtual addresses (virtual page addresses therein) and physical addresses (physical page addresses) corresponding to the same address. An associative TLB 51 is provided.

Each entry in the TLB 51 has a valid bit V (V=1) indicating that the contents of the corresponding entry are valid.
In addition to the substitution prohibition flag F (true when F = 1) to specify that replacement (replacement) of the corresponding entry is prohibited (true when F = 1)
is set. In addition, each entry in the TLB 51 is provided with an LR indicating how recently the entry has been accessed, in order to apply replacement control using the LRU method, for example.
The U value is set. This LRU value is, for example, cleared when a corresponding entry is hit, and is incremented by, for example, +1 when there is no hit.

The MMU 5 further contains address translation information (which has the same format as the address translation information in the TLB 51), which includes a pair of a virtual address (virtual page address therein) and a physical address (physical page address) corresponding to the same address. A work buffer (hereinafter referred to as work TLB) 52 is provided for storing a plurality (for example, two) of TLBs (without limitation). Each entry in the work TLB 52 has a valid bit V (V=
1 = true) is set. It is assumed that the work TLB 52 has a ring buffer structure, for example, and the storage destination entries are used in a circular manner.

Next, the operation of the system shown in FIG.
A case will be described with reference to the flowchart of FIG. 2, taking as an example a case where there is an access request from a virtual address. First M
When the MU5 receives an access request from the CPU 1 using a virtual address, the MU5 searches the TLB 51 and the work TLB 52 with the virtual page address to be converted in order to convert the virtual page address in the virtual address to a physical page address (step S1). .

[0023] If TLB51 or work TLB52
If the conversion target virtual page address is stored in , that is, if the TLB 51 or work TLB 52 is hit, the MMU 5 immediately obtains the physical page address stored in a pair with the conversion target virtual page address,
Using that physical page address (and the physical address consisting of the offset within the page in the virtual address to be translated),
Execute the requested access (steps S2, S3)
.

On the other hand, TLB51 and work TL
If the conversion target virtual page address is not stored in any of the TLB51 and the work TL
If you miss hit any of the B52, first MMU
5 stores the virtual page address in the work TLB 52 (step S4). And MMU5 is main memory 2
A table walk is performed using the above address translation table 21 to convert the virtual page address to be translated into a physical page address (step S5).

[0025] When the MMU 5 obtains the physical page address by the table walk, the MMU 5 converts the physical page address into
The virtual page address to be converted is stored in the entry in the work TLB 52 in which it is stored in step S4 so as to form a pair with the virtual page address, and the valid bit V in the entry is stored as a pair with the virtual page address.
is set to "1" (step S6). Note that step S4 may be omitted and the pair of virtual page address and physical page address may be stored in the work TLB 52 in step S6.

Next, the MMU 5 checks the TLB 51 and determines the LR
The entry with the largest U value is searched as the replacement target entry, and the state of the replacement prohibition flag F of the replacement target entry is checked (step S7).

If the replacement prohibition flag F of the replacement target entry in the TLB 51 is "0", that is, if the target entry is not a replacement designated entry, the MM
U5 moves the pair of virtual page address and physical page address stored in the entry in the work TLB 52 to the entry to be replaced, and returns the valid bit V of the original entry in the work TLB 52 to "0" (step S8). At this time, the MMU 5 sets the valid bit V of the replacement target entry in the TLB 51 to "1", clears the LRU value, and further sets the replacement prohibition flag F to "0" or "1". Whether this replacement prohibition flag F is set to "0" or "1" is specified in the virtual address access request from the CPU 1.

When the MMU 5 executes step S8, T
The requested access is executed using the physical page address (and the physical address consisting of the intra-page offset in the virtual address to be converted) stored in the LB 51 (step S3).

On the other hand, if the replacement prohibition flag F of the replacement target entry in the TLB 51 is "1", that is, if the target entry is a replacement designated entry, the MMU
5 first checks whether substitution prohibition is specified by the access request from the CPU 1 (step S9).
).

[0030] If replacement prohibition is specified by the access request from the CPU 1, the MMU 5 determines whether it is necessary to make the physical page address (including address translation information) obtained by table walk resident in the TLB 51. Then, the TLB 51 is checked, and the entry with the largest LRU value among the entries whose replacement prohibition flag F is "0" (entries for which replacement prohibition is not specified) is searched as a replacement target entry (step S10).

Then, the MMU 5 moves the pair of virtual page address and physical page address stored in the entry in the work TLB 52 to the replacement target entry found in step S10, and sets the valid bit V of the original entry in the work TLB 52 to "0". ” (step S11). At this time MM
U5 sets both the valid bit V and the replacement prohibition flag F of the replacement target entry in the TLB 51 to "1" and clears the LRU value.

On the other hand, if prohibition of replacement is not specified in the access request from the CPU 1, the MMU 5 does not need to make the physical page address (including address translation information) obtained by table walk resident in the TLB 51. judge it as something. In this case, MMU5 is TLB5
1, and executes the requested access using the physical page address stored in the work TLB 52 (step S3).

Now, after the above operation of MMU5, CPU
It is assumed that the following access request is issued from 1 to 1. if,
If the same page address as the virtual page address in the virtual address associated with this access request is stored in the work TLB 52, that is, if the work TLB 52 is hit, the MMU 5 performs the work in a pair with the virtual page address. The physical page address stored in the TLB 52 can be immediately obtained and the access request can be executed.

On the other hand, work TLB52 and TL
If there is a mishit in any of the B51s, a table walk is required to rewrite the work TLB52 as described above. However, if the access request from the CPU 1 specifies that substitution is prohibited (that is, if the access request requires address translation information to remain resident in the TLB 51), the address translation information is not registered in the entry in the TLB 51. Moreover, since the same entry is designated as prohibited from being replaced by the replacement prohibition flag F, unless special processing is performed, such as invalidating all entries in TLB 51, the address translation information will not be replaced by TLB51.
The probability that the access request will not be evicted from the LB 51 and will hit the TLB 51 for this type of access request increases.

The above operation of the MMU 5 is performed when the virtual address from the CPU 1 misses the cache memory 4, that is, when the cache block data specified by the virtual address does not exist in the cache memory 4. . If the cache memory 4 is hit, the requested access to the cache memory 4 is executed.

In the above embodiment, the work TLB (work buffer) 52 has been described as having a plurality of entries, but the number of entries may be one. Furthermore, the cache memory 4 is not necessarily required.

In the above embodiment, when address translation information is stored in an entry in the TLB 51, it is determined whether or not to prohibit substitution of the entry (that is, whether to set the substitution prohibition flag F in the entry to "1"). Although the description has been made assuming that the access request (whether or not) is specified by the access request from the CPU 1,
Specify whether or not to prohibit replacement for each virtual address (virtual page address) (can be rewritten by CPU1)
A table may also be used. This table is
For example, it is preferable to place it in the MMU5.

Further, in the above embodiment, the case where the application is applied to the fully associative type TLB 51 has been described, but the present invention is applicable to the TLB 51 of the set associative type, for example.
It is also applicable to

[0039]

[Effects of the Invention] As detailed above, according to the present invention,
A replacement prohibition flag is provided in the TLB entry to specify prohibition of replacement to restrict the occurrence of TLB replacement, and address translation information that cannot be stored in the TLB due to this restriction is temporarily stored in the work buffer. As a result, for TLB entry contents that should be kept resident in the TLB in terms of performance, it is possible to suppress the occurrence of unnecessary TLB replacement, increase the hit rate, and improve performance.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of an information processing system using a virtual storage control method to which the present invention is applied.

FIG. 2 is a flowchart for explaining the operation of the embodiment.

[Explanation of symbols]

1...CPU, 2...Main memory, 3a, 3b...Peripheral equipment, 4
...cache memory, 5...MMU (memory management unit), 21...address translation table, 51...TLB (address translation buffer), 52...work TLB (work buffer).

Claims (1)

[Claims] 1. An information processing system using a virtual memory control method, comprising a TLB (address translation buffer) having a plurality of entries for storing address translation information including pairs of virtual addresses and physical addresses corresponding to the virtual addresses. , a substitution prohibition flag provided in each entry of the TLB to specify substitution prohibition for that entry, a work buffer for storing address translation information including a pair of a virtual address and a physical address, and a virtual address. When it is necessary to convert the above virtual address to a physical address, the above TLB and work buffer are searched using the same virtual address, and if the same virtual address does not exist in either the above TLB and the work buffer, the same virtual address is searched in the address translation table. address translation means for converting into a physical address using the address translation means, and address translation information including a pair of the physical address translated by the address translation means and its virtual address in the work buffer;
Only if the above-mentioned replacement prohibition flag in the replacement target entry of the above-mentioned TLB does not indicate that replacement is prohibited,
means for storing address translation information including a pair of the translated physical address and its virtual address,
A TLB replacement method characterized in that, when the replacement prohibition flag in the replacement target entry of the TLB indicates that replacement is prohibited, the replacement target entry is prohibited from being replaced.