JPH04333952A - Dma control lsi - Google Patents

Abstract

PURPOSE:To efficiently transfer data even to a two-dimensional memory area by providing an address generation circuit to generate the address of the two-dimensional area according to a prescribed parameter. CONSTITUTION:A DMA control LSI 1 has plural channels for data transfer, and an address generation circuit 13 is provided to generate the address of the two-dimensional area for each channel according to the prescribed parameter. In this case, the circuit 13 constitutes the address of the two-dimensional area based on the parameter composed of a value showing the number of words in the X direction of the transfer area of the two-dimensional area at a transfer memory, a value showing the number of lines in a Y direction orthogonal to the X direction of the transfer area, the memory width of the transfer memory and the start address of data transfer.

Description

[Detailed description of the invention]

[Object of the invention]

0002

[Industrial Application Field] DMA control LSI that transfers large amounts of data between memories and between memories and I/O devices
In particular, the present invention relates to a DMA control LSI that can efficiently transfer two-dimensional data including a two-dimensional area.

0003

[Prior Art] First, the conventional method of transferring one-dimensional data is
The basic functions of the MA control LSI will be described. For example, in a block transfer of data that handles data in a certain area of memory, you can store the address value that points to the beginning of that area in a register, and increment it by 1 each time a 1-byte transfer is completed. Data groups of consecutive addresses can be transferred. BA this register
R (byte address register)
and WAR (word address register)
r ), and generally a counter is used.

[0004] Even if the contents of the memory are to be transferred continuously, the size, that is, the range thereof, is finite, so another counter is also required to manage the number of transferred words in the memory. Therefore, one block is 128 bytes or 256 bytes.
A counter whose count value can be preset for each byte is used. This counter is defined as BCR (byte
count register) and WCR (wo
The required number of bytes is set as an initial value, and is decremented by 1 each time one byte transfer is completed. If the DMA is terminated when the content becomes 0, the transfer of one block can be completed using the function with the previous BAR. Having these two counters is a major element of the DMA controller.

[0005]

In the conventional DMA controller described above, the addresses generated for the memory area to be transferred are limited to a continuous one-dimensional area. For example, in a system where the host CPU uses a DMA controller to process data for a two-dimensional frame memory (local memory) managed by a graphics controller in a graphics system, it is possible to Data transfer was not possible.

Next, referring to FIG. 8, a case will be described in which a conventional DMA controller is used to transfer data from a one-dimensional area main memory to a two-dimensional area local memory.

As shown in FIG. 8, using a conventional DMA controller 101, a one-dimensional area of main memory 103 to 2
When data is transferred to the local memory 105 in the dimensional area, two DMA channels, A and B, are used. The A channel manages the address of the main memory 103, and the B channel manages the address of the local memory 105. Perform address management. The host CPU 107, which manages commands/parameters of the DMA controller 101, controls the DMA controller 101 according to the following procedure.

First, the transfer destination address of the frame memory 105 is set in the WAR register of the B channel. Further, the number of words corresponding to one line of the two-dimensional area is set in the B channel WCR register. Next, the transfer source address of the main memory is set in the WAR register of the A channel, and the same value as the WCR register of the B channel is set in the WCR register of the A channel.

Second, after the above set, the host CPU 1
07 sets a transfer start command to the DMA controller 101. Third, upon receiving the transfer start command, the DMA controller 101 activates and outputs an HRQ signal requesting bus ownership to the host CPU 107. Upon receiving the HRQ signal, the host CPU 107 outputs the HLDA signal to the DMA controller 101 when it is ready to grant bus rights. Fourth, upon receiving the HLDA signal, the DMA controller 101 enters a data transfer cycle, reads out the contents of the main memory 103 using the address generated on channel A, and stores it in a register inside the DMA controller. Next, the contents of the register are written to the local memory 105 using the address generated in channel B, the contents of the WCR registers of both channels are incremented by -1, and the contents of the WAR registers of both channels are incremented by -1 or +1. These series of operations are repeated until the contents of WCR become 0. Fifth, after the transfer cycle ends, the DMA controller 101 makes the HRQ signal inactive, and the host CP
Relinquish bus rights to U107.

In order to transfer all data, WAR is required for all lines in the Y direction of the two-dimensional area of the local memory.
Change the transfer start address in the register and repeat the steps 1 to 1 above.
The process will be repeated up to the fifth point. That is, D.M.A.
Since the operation procedure of the controller 101 is performed line by line, the overhead becomes large, and the conventional DMA controller 10
Data transfer including a two-dimensional area according to No. 1 cannot efficiently transfer data.

The present invention was made to solve the conventional problems as described above, and its purpose is to provide a DMA control LSI that can efficiently transfer two-dimensional data including a two-dimensional area. It is to be.

[Configuration of the invention]

[0013]

[Means for Solving the Problems] In order to achieve the above object, the present invention is a DMA control LSI that transfers data between memories having two-dimensional memory areas, defined in X and Y directions orthogonal to each other. from the number of words in the X direction of the transfer area of the two-dimensional memory area, the number of lines in the Y direction of the transfer area, the width of the memory area along the X direction, and the start address of data transfer. address generating means for generating an address of a transfer area in a two-dimensional memory area according to predetermined parameters; and means for transferring data between the memories according to the address of the transfer area in the two-dimensional area generated by the address generating means. It is characterized by comprising:

[0014]

[Operation] With the above configuration, it is possible to generate the address of the transfer area of the two-dimensional memory area for each channel, so that it is possible to generate the address of the transfer area of the two-dimensional memory area for each channel. Two-dimensional data can be transferred easily.

[0015]

[Example] Hereinafter, DMA control LS according to the present invention
An embodiment of I will be described based on the drawings.

FIG. 2 is an overall configuration diagram of an example of a data transfer system using a DMA control LSI according to the present invention.
3 to transfer the two-dimensional data from the main memory (frame memory) 5 of the two-dimensional area to the local memory 9 of the two-dimensional area managed by the graphic controller 7 via the system bus 11. It is configured.

FIG. 1 shows the above DMA control LSI 1.
FIG. 2 is a block diagram showing the internal configuration of the computer.

The main feature of the DMA control LSI 1 of the present invention is that it has a plurality of channels (four channels in this embodiment) for data transfer, and each channel is controlled according to predetermined parameters described later. A generation circuit 13 is provided for an address capable of generating an address in a two-dimensional area.

Furthermore, the DMA control LSI 1
The address generation control circuit 15 controls the address generation circuit 13 according to instructions from the host CPU 3, and transmits the addresses of the two-dimensional area generated by the address generation circuit 13 to the corresponding frame memories 5 and 9 on the system bus 11. An I/O buffer 19 and a command control unit 21 for sending data to the address bus 17, and a system bus 11 according to the addresses sent to the frame memories 5 and 9.
It has a FIFO register 25 for storing data transferred via a data bus 23. Further, the DMA control LSI 1 further includes a timing controller 27, a priority controller 29, and a timing controller 27 for controlling the data bus 23 in data transfer.
It has a command register 31, a mask register 33, a request register 35, a mode register 37, a status register 39, and an I/O buffer 41.

Next, the address generation circuit 13, which is the main part of the present invention, will be explained with reference to FIG.

The address generation circuit 13, as shown in FIG.
Two-dimensional data transfer based on parameters consisting of the number of words in the direction X1, the number of lines in the Y direction perpendicular to the X direction of the transfer area Y1, the memory width Xo of the transfer memory, and the start address of data transfer. Configured to generate an address for the area. That is, the address generation circuit 13 includes an XWC register 51 for setting a value X1 of the number of words in the X direction of the two-dimensional transfer area, and a YLC register 51 for setting a value Y1 of the number of lines in the Y direction of the transfer area. a register 53, a MW register 55 for setting the memory width Xo of the transfer memory, and a W register 55 for setting the start address of data transfer.
An adder (or subtracter) 59. The address generation circuit 13 further includes an address counter 61 that counts for each transfer address set in the WAR register 57, and a counter 63 that counts the number of words X1 set in the XWC register 51. have.

Further, the size of the two-dimensional transfer area is managed by the XWC register 51 and the YLC register 53.

Next, the operation of the DMA control LSI will be explained with reference to FIGS. 1 and 4.

In this case, two channels of the DMA control LSI are used to transfer data from the two-dimensional area of the main memory 5 to the two-dimensional area of the local memory 9. That is, the address generation circuit 13 of channel 1
Address generation is performed using the address generation circuit 13 of channel 2 and the address generation circuit 13 of channel 2. Here, the address generation circuit 13 of channel 1 generates an address for the source area (two-dimensional area of the main memory 5), and the address generation circuit 13 of channel 2 generates an address for the destination area (two-dimensional area of the local memory 9). It is designed to generate addresses.

First, in accordance with instructions from the host CPU 3, the address generation control circuit 15 sets the XWC registers 51, Y
The LC register 53, MW register 55, and WAR register 57 contain predetermined parameters, namely, the number of words in the X direction of the transfer area X1, and the number of lines Y in the Y direction of the transfer area.
1. Set the memory width Xo of the transfer memory and the start address of data transfer. Here, the number of words in the X direction of the XWC register 51 of both channels Xo and Y
The value of the number of lines Y1 in the Y direction of the LC register 53 is usually the same value (see FIG. 4).

Next, the host CPU 3 sets a transfer start command to the priority controller 29 of the DMA control LSI 1, and in response, the priority controller 29 outputs an HRQ signal requesting bus ownership to the host CPU 3. Upon receiving the HRQ signal, the host CPU 3 sends the HLD to the priority controller 29 when it is ready to grant the bus right.
Outputs A signal.

Upon receiving the HLDA signal, the DMA control LSI enters a data transfer cycle and transfers data from the source area (transfer area) according to the start address of the source area set in the WAR register 57 of the address generation circuit 13 of channel 1. is written to the FIFO register 25 via the data bus 23 and the I/O buffer 41. Next, the address counter 61 is counted up (+1) or down (-1),
The next data is read from the source area and written to the FIFO register 25 according to the next start address.

The above operation is repeated, and the FIFO
A plurality of data of the first line are sequentially written into the register 25 (see FIG. 4). In the above write, the XWC register 5 of the address generation circuit 13 of channel 1
The value of 1 (number of words in the X direction X1) is counted down (-1) by the counter 63 every time the above data is written.
be done.

Next, in parallel with the above writing, the DMA control LSI moves to a process of writing the data written in the FIFO register 25 to the transfer area of the local memory 9, which is the destination area. First, the start address set in the WAR register of the address generation circuit 13 of channel 2 is read, and the first line of data from the FIFO register 25 is transferred via the data bus 23 and I/O buffer 41 according to the start address. The data is then transferred to the destination area of the local memory 9. The address counter 61 of the WAR register 57 of the address generation circuit 13 of channel 2 is counted up (+1) or down (-1) for each write process, and the write process is performed sequentially.

[0030] The above writing process and transfer process are as follows:
This process is repeated until the value of the XWC register 51 (the number of words in the X direction X1) of the address generation circuit 13 of channel 1 becomes 0 by the counter 63. Number of words in the above X direction X1
When becomes 0, in order to calculate the start address of the second line of the two-dimensional transfer area of the source area and destination area, the adder 59 of each address generation circuit 13 of channels 1 and 2 inputs the WAR register 57.
The start address of the previous line (first line) set in MW register 55 is added (or subtracted) from the memory width set in MW register 55. The above addition result is set in the address counter 61 and the WAR register 57,
The writing and transfer processing of the second line is executed. When the above addition is performed, the value of the YLC register 53 (number of lines in the Y direction Y1) counts down (-1).
The write and transfer processes are performed until the value of the YLC register 53 becomes 0 (that is, until the last line ends). When the value of the YLC register 53 becomes 0, the transfer cycle ends, and the DMA control LSI makes the HRQ signal inactive.
The bus right is relinquished to the host CPU3.

As described above, D according to the present invention
The operation of the MA control LSI is simpler than that of conventional devices that perform two-dimensional transfer.

Further, in this embodiment, the case of transfer from two-dimensional area to two-dimensional area has been explained, but as shown in FIGS. 5 and 6, transfer from one-dimensional area to two-dimensional area and transfer from two-dimensional area to It goes without saying that transfer of a one-dimensional area can also be carried out by slightly modifying the method of using the apparatus of the above embodiment.

Furthermore, according to this embodiment, it goes without saying that various combinations of transfers can be performed, as illustrated in FIG.

[0034]

[Effects of the Invention] As explained above, in the present invention, DM
Since the A control LSI is provided with an address generation circuit that generates an address for a two-dimensional area according to predetermined parameters, data can be transferred efficiently even to a two-dimensional memory area.

[Brief explanation of drawings]

FIG. 1 is an internal block diagram of a DMA control LSI embodying the present invention.

FIG. 2 is an overall block diagram of a system in which the DMA control LSI shown in FIG. 1 is used.

FIG. 3 is an explanatory diagram of predetermined parameters for generating addresses in a two-dimensional area.

FIG. 4 is a diagram for explaining the operation of the DMA control LSI shown in FIG. 1;

FIG. 5 is an explanatory diagram of data transfer from a one-dimensional area to a two-dimensional area.

FIG. 6 is an explanatory diagram of data transfer from a two-dimensional area to a one-dimensional area.

FIG. 7 is an explanatory diagram showing examples of various transfer combinations.

FIG. 8 is an explanatory diagram of conventional data transfer from a one-dimensional area to a two-dimensional area.

[Explanation of symbols]

1 DMA control LSI 3 Host CPU 5 Main memory 9. Local memory 13 Address generation circuit 25 FIFO register

Claims (3)

[Claims] 1. Address generation means for generating an address of a transfer area of a two-dimensional memory area according to predetermined parameters in a DMA control LSI that transfers data to a memory having at least a two-dimensional memory area; A DMA control LSI comprising: means for transferring data to the memory according to an address of a transfer area in a two-dimensional area generated by an address generating means. 2. The predetermined parameter is a value of the number of words in the X direction of the transfer area of the two-dimensional area defined by mutually orthogonal X and Y directions, and a value of the number of lines in the Y direction of the transfer area. , the width of the memory area along the X direction, and a data transfer start address. 3. The address generating means includes an XWC register for setting a value of the number of words in the X direction of the transfer area, and a YLC register for setting a value of the number of lines in the Y direction of the transfer area; A MW register for setting the width of the memory area along the X direction, a WAR register for setting the start address of data transfer, and a memory width set in the MW register and the WAR register. an adder for calculating a line-by-line start address in the Y direction of the transfer area from the start address; an address counter that counts for each start address set in the WAR register; 3. The DMA control LSI according to claim 2, further comprising a counter that counts each value of the number of words.