JPH04332214A - high speed interpolator - Google Patents

Abstract

PURPOSE:To obtain a high speed interpolation device to apply precise, high order, high clock time precision interpolation to a high speed signal such as image signal and further to make it possible to realize such interpolation with low speed circuit elements by using a fixed oscillator and variable delay element to equivalently enhance a time resolution. CONSTITUTION:Counter 1 is reset by a input sampling signal fS1 at every cycle T1=1/fS1), while at the same time the clock position for delay unit 2 is preserved in a latch 5, and further the clock position is converted to clock time 11 by a decoder 7. Next, a counter value of counter 1 and a clock position of delay device 2 are preserved in latches 3 and 4 by an output sampling signal fS2 at every cycle T2=1/fS2, respectively. The value of latch 4 is converted to clock time l2 by decoder 6, and the value of latch 3 is input in the decoder 6 to obtain an output sampling point of time t2. Adder 8 subtracts value t1 of decoder 7 from value t2 of decoder 6, and preserves the result of the subtraction in a latch 9. Accordingly, an interpolating point of time tau can be obtained in terms of the precision of delay time d.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interpolation device, and more particularly to an interpolation device most suitable for processing signals such as image signals that require a high sampling frequency.

0002

2. Description of the Related Art In TV image signal processing, conversion of sampling frequency is often required. In image signal processing, the sampling frequency can be as high as 10-odd MHz, so a high-speed circuit is required to convert the sampling frequency, and if the conversion ratio of the sampling frequency is not a power of 2, the configuration hardware becomes complex. Therefore, linear interpolation with the lowest interpolation order is often used. An example of this is Sakamoto et al., "Adaptive Sample Frequency Converter," TV Society Technical Report pp. 1-6
, vol. 11, no. There is a sampling frequency converter described in No. 15, 1986. Furthermore, as a sampling frequency converter that can freely select the conversion ratio of the sampling frequency, there is an interpolation method described in Japanese Patent Application No. 15633/1983.

0003

SUMMARY OF THE INVENTION The interpolation device requires a timekeeping circuit for determining the output data point in time with respect to the sample point in the input data series. The sampling frequency of signals used in image signal processing is several tens of MHz, so to convert the sampling frequency between systems with different sampling frequencies,
A timekeeping device that operates with a high-speed clock signal on the order of GHz is required. Therefore, in order to increase the time resolution of the clock pulse, the first example of the prior art uses a timing device as shown in FIG. 3.

In FIG. 3, 311, 312, 313,
~, 31N is a delay element, 32 is an N-bit latch circuit,
33 is a ROM. Input the input sampling signal f1 to the delay element arrays 311, 31N, and calculate the delay time τ of the delay elements.
A sampled signal shifted by d is obtained. By latching these signals with the output sampling signal f2, the time difference between f1 and f2 can be read with a time accuracy of τd. By using the gate delay time of a logic gate circuit as a delay element, a time resolution of several nS can be achieved. However, there are problems such as an extremely large number of elements used, poor clock time accuracy due to inter-element deviations, temperature fluctuations, etc., increased jitter, and inability to perform accurate sampling frequency conversion. Also, because the circuit becomes complicated, only low-order interpolation can be achieved.
There is also the drawback that interpolation accuracy deteriorates.

On the other hand, the method described in Japanese Patent Application No. 15633/1983 allows high-order interpolation, but the clock of the timekeeping device still needs to be high-speed, so it cannot be said to be fully practical. do not have.

An object of the present invention is to provide a circuit element that is capable of performing high-order interpolation with higher precision than linear interpolation for high-speed signals such as image signals, has high clock time precision, and is relatively slow. The object of the present invention is to provide an interpolation device that can be realized using the following methods.

[0007]

[Means for Solving the Problems] In order to achieve the above object, an interpolation device using a time-varying coefficient filter uses a fixed oscillator and a variable delay element instead of using a high-speed clock to achieve equivalent time resolution. Use the method of increasing Regarding the interpolation device using a time-varying coefficient filter, the above-mentioned patent application No. 6
Although it is detailed in No. 1-15633, I will explain it briefly.

According to the sampling theorem, as shown in FIG. 4, from the data sequence f(nT1) sampled at period T1, the original time function f(t) is calculated as Sinc(t)=sint
/t using f(t)=Σf(nT)
Sinc{π(t-nT1)/T1}=Σf(nT1)
It can be expressed as Sc(n, τ) (Equation 1). Here, τ=t/T1 is a fraction when measuring the output time t in T1 period. Equation 1 shows the coupling coefficient Sc(n,
τ) is a function of t. Time-varying coefficient Sc
(n, τ) is 1 at t=nT1, t=mT1 (m≠n, m
, n is an integer) and has the property of being 0, such as Sinc(t) in Equation 1 and Lagr used in numerical analysis.
Various functions are known, such as ange's interpolation polynomial.

In addition, Equation 1 shows that when approximated by a finite number of data N, the interpolated value f(t) can be obtained as the output of an acyclic (FIR) filter with time-varying coefficients Sc(n, τ). It shows. This shows that interpolation (or sampling frequency conversion) can be implemented in hardware using a time-varying coefficient filter. The parameters n, τ that determine the time-varying coefficient Sc(n, τ) are determined by the data output time t given by the second sampling period T2, and are determined by the following formula: t=nT1+τ=mT2

(Math. 2)

FIG. 5 shows the hardware configuration of the entire interpolation device. In the figure, 510, ~, 51N-1, 51N are coefficient multipliers, 521, ~, 52N are delay elements, 531,
. . . , 53N are adders/subtractors, 54 is a ROM, 55 is a clock device, 56 is a counter, and 57 is a latch. The timekeeping device 55 that calculates τ that determines the interpolation time t in Equation 2 is T1
This can be achieved by inputting a sufficiently faster clock pulse to the counter 56, resetting it at the T1 period, and reading the counted value to the latch 57 at the T2 period. Time-varying coefficient Sc(
n, τ) is written in advance in the ROM 54, read out using the determined τ, and given as a coefficient of the FIR filter, an interpolation device using a time-varying coefficient filter can be realized.

The disadvantage of the method using the above-mentioned timing device is that if the ratio of the input/output sampling frequencies fs1 and fs2 is not a simple integer, the clock frequency fCLK becomes very high, making it difficult to implement. . Therefore, a method is used in which a fixed oscillator, a variable frequency divider, and a variable delay element are combined as a clock oscillator to equivalently increase the time resolution.

The basic configuration is shown in FIG. In the figure, 61
is a fixed frequency oscillator, 62 is a frequency divider, 63 is a delay device, 6
4 and 65 are latches. If the clock period from the fixed oscillator 61 is TCLK=1/fCLK, the number of division stages of the frequency divider 62 is M, and the delay time per delay element of the delay device 63 is d, then the number of delay stages of the delay device 63 is L= M・TCLK/d
It is sufficient to have the above prepared. If the count number m of the frequency divider 62 and the number l of delay stages of the delay device are measured at the input/output sample time, and the difference between t1 = (m1, l1) and t2 = (m2, l2) is calculated, the interpolation time τ = t2-t1={(m2-m1
)・L+l2−l1}・d is obtained.

[0013]

[Operation] The effects of the timekeeping device using the frequency divider and delay device described above will be explained using a specific numerical example. When controlling a signal with a period of 100 nS (frequency 10 MHz) with a time resolution of 1 nS, if you try to realize it with a single oscillator, it will require 1 GHz.
A variable oscillator of z and a high speed divider of 100 are required. To achieve this, high-speed circuit elements such as ECL are required. Furthermore, if we tried to achieve the same thing using only delay elements, we would need a delay element consisting of 100 stages of a 10MHz oscillator and a 1nS delay element, and a selection control circuit for the delay element, which would result in a high-speed and complicated circuit. . Therefore, if we use the method described in the [Means for solving the problem] section, we can create a delay device that combines a 100MHz fixed oscillator, a 2-frequency divider, and 20 stages of 1nS delay elements. If so, equivalent functionality can be achieved. These are all moderate values and can be easily realized using commonly used IC technology.

[0014] To explain time measurement using a ruler for measuring length, the above-mentioned timekeeping device can be compared to a caliper having a main scale and a vernier scale. The frequency divider corresponds to a main scale with coarse graduations, and the delay device corresponds to a vernier scale with fine graduations. It is difficult to increase accuracy with only the main scale, and with only a vernier scale, accuracy is high, but
Can only measure short distances. By combining the two, large lengths can be measured with high accuracy.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Examples of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing the configuration of an embodiment of the present invention. In the diagram, 1 is a counter, 2 is a delay device, 21, 22, . . .
, 2N are delay elements, 3, 4, 5, and 9 are latches, 6 and 7 are decoders, and 8 is an adder/subtractor. Clock signal fCLK
is input to the counter 1 and also to the delay device 2. The delay device 2 includes delay elements 21, 22, with a delay time d.
. . , 2N are connected in cascade.

Counter 1 receives input sampled signal fs1,
It is reset every cycle T1=1/fs1. At the same time, the clock position of the delay device 2 is stored in the latch 5, and further converted into a clock time l1 by the decoder 7. Since the count value m1 of counter 1 is 0 (because it is reset every fs1), the input time t1 of the input sample value mentioned in the section of means becomes t1 = (m1, l1) = (0, l1). . Next, the count value of counter 1 and the clock position of delay device 2 are set at period T2 = 1/f using output sampling signal fs2.
Each time s2 is stored in latches 3 and 4, respectively. The value of latch 4 is converted to clock time l2 by decoder 6, and the value of latch 3 is input to decoder 6 to obtain output sample time t2=(m2,l2)=m2·L+l2. Here, L is the number of delay stages of delay device 2, and the clock period TC
From LK=1/fCLK and delay time d per delay element of delay device 2, it is determined that L=TCLK/d. The adder/subtractor 8 subtracts the value t1 of the decoder 7 from the value t2 of the decoder 6, and stores the result in the latch 9. In this way, the interpolated time τ=t2 −t1 can be determined with the accuracy of the delay time d. Specifically, if TTL or the like is used and the gate delay time is used as the above d, a value of about 5 nS can be easily obtained. As a result, the time accuracy is 200MH
The same effect as using a high speed clock of z can be obtained.

On the other hand, if a high-speed clock of 200 MHz is actually used, the number of delay stages will be about 20 for a sampling frequency of 10-odd MHz, and the scale of the circuit required to operate at high speed will become large. However, in the above embodiment, the clock frequency can be set to a value of about 20 to 50 MHz,
Since there is no need for high-speed operation and only a few delay stages are required, the circuit size can be reduced.

Another embodiment according to the invention is shown in FIG. In FIG. 2, 20 is a clock device having the same configuration as the first embodiment, 21, 22, 23 are latches, 24 is an adder/subtractor, and 25 is a decoder. This embodiment is applied when the input sampling frequency is unknown or not constant. In such a case, it is necessary to measure the input sampling period T1. Therefore, the count value of counter 1 (the value immediately before being reset with fs1) and the value of decoder 7 are input at sampling period T1.
It is held in the latches 21 and 23. The adder/subtracter 24 adds and subtracts t1n-1 held in the latch 23 and the value t1n of the decoder 7.
and calculate the difference δ=t1n-1-t1n. The count value m1 of counter 1 is multiplied by L and added to obtain the input sampling period T1=m1L+δ. This calculation is executed by the decoder 25. The obtained result is held in the latch 22 and input to the coefficient ROM 54 of the digital interpolator. By calculating τ/T1 using the coefficient ROM, the present invention can be implemented even when T1 is unknown or varies.

The actual delay time of a logic gate varies depending on the power supply voltage, ambient temperature, manufacturing deviation of the device, and the like. Therefore, when configuring the delay device using an IC or the like, consideration must be given to this point. Specifically, the value of the number of delay stages L=TCLK/d, which is determined by the ratio between the clock period TCLK and the delay time d of the delay element, changes. The value of L is the count value of counter 1 in the embodiment (FIG. 1) at interpolation time τ or input sampling period T1.
Since it is input to decoder 6 or 25,
If this value is not accurate, the values of τ and T1 will be incorrect. Therefore, a circuit for measuring L is required.

FIG. 7 shows another embodiment of the present invention that takes this point into account. In the figure, 2 is a delay device having the same configuration as the embodiment in FIG.
2N is a delay element, 71 is a latch, and 72 is a decoder. The number of delay stages L and N is L=TC, where the average value of the delay time of the delay element is d0, and the minimum value of the variation range is dm.
LK/d0, N=TCLK/dm. It is input to the latch 71 and held by a clock signal so as to include all clock outputs due to variations in delay time. Since the latch 71 outputs an output whose logic level changes before and after the clock time position, the decoder 72 converts this into the number of delay stages L corresponding to the clock position. Accurate values of τ and T1 can be obtained by inputting the obtained L to the decoder 6 or 23 (embodiment shown in FIG. 2), which converts it into an interpolation time τ or an input sampling period T1. The embodiments described above provide an interpolation device that operates accurately even when the delay time of the delay element varies.

[0021]

Effects of the Invention According to the present invention, sampling is performed when the sampling frequency becomes high, such as when the conversion ratio of the sampling frequency is not a power of 2 or when handling high-speed signals such as image signal processing. Frequency conversion can be easily performed. Unlike conventional circuits, this can be done using relatively low-speed commonly used circuit technology without using high-speed operating circuit elements, making it possible to simplify the circuit and facilitate its design.

On the other hand, since high-order interpolation with high conversion accuracy can be used without making the circuit scale very complicated, there is an advantage that the accuracy of sampling frequency conversion is improved.

In addition, since it has means for correcting element delay time fluctuations due to power supply voltage fluctuations, ambient temperature fluctuations, manufactured element characteristic deviations, etc., it is easy to integrate it into an IC, resulting in miniaturization of the circuit and Economicalization can be achieved. Furthermore, since it is entirely composed of digital circuits, it can be applied to a wide range of fields as digital processing technology spreads.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram of one embodiment of the present invention.

FIG. 2 is a configuration diagram of another embodiment of the present invention.

FIG. 3 is a partial configuration diagram of a conventional example of an interpolator.

FIG. 4 is a diagram illustrating the principle of interpolation used in the present invention.

FIG. 5 is a configuration diagram of another conventional example of a digital interpolator.

FIG. 6 is a principle diagram of a timekeeping circuit according to the invention.

FIG. 7 is a partial configuration diagram of yet another embodiment according to the present invention.

[Explanation of symbols]

1, 56... Counter, 2... Delay device, 21, 22, ~, 2
L-1, 2L, 2L+1, ~, 2N, 311, 312,
313, ~, 31N, 521, ~, 52N...delay element,
3, 4, 5, 9, 21, 22, 23, 32, 57, 71
...Latch, 6, 7, 25, 72...Decoder, 8, 24,
531, ~, 53N... Adder, 33, 54... ROM, 5
10, ~, 51N-1,51N...Coefficient multiplier, 20,5
5... Timing device.

Claims (4)

[Claims] Claim 1: First sampling pulse signal (frequency fs1)
Then, the sampling time of the second sampling pulse signal (frequency fs2) is measured by a clock device that is periodically initialized, and a time-varying coefficient filter having a coefficient determined by the sampling time is used to calculate the above-mentioned In an interpolation device that converts an input signal sequence sampled at a first sampling frequency fs1 to an output signal sequence resampled at a second sampling frequency fs2,
A clock signal faster than either of the first and second sampling frequencies is inputted through a counter to a multistage delay circuit including a delay element array having a delay time shorter than the clock signal cycle, the multistage delay circuit a latch circuit that holds the output from each stage at the first and second sampling times, and a decoder that decodes the latch output and converts it into clock position information, and the decoder output value and A high-speed interpolation device characterized by using a timekeeping device that calculates the first and second sampling times from the counter output value. 2. The timing device of the interpolation device according to claim 1, wherein the clock signal is set at the first sampling frequency fs.
1, and a clock output from each stage of the multistage delay circuit.
first and second latch circuits that hold at the first and second sampling times, and decoding the first latch output;
a first decoder for converting to the first sampling time; a third latch for holding the output value of the counter at the second sampling time; and decoding the third and second latch outputs. and a second decoder that converts the sampling time to the second sampling time, and the sampling time is determined by subtracting the first decoder output value from the second decoder output value. A high-speed interpolation device characterized by using a timing device. 3. The timekeeping device of the interpolation device according to claim 1 and claim 2, further comprising: a fourth latch that holds the output value of the counter at the first sampling time; and the first decoder output value. a fifth latch that holds the value at the first sampling time, subtracts the first decoder output value from the value held in the fifth latch, and inputs the result and the fourth latch. and the period of the first sampling signal (1/fs
A high-speed interpolation device characterized in that a third decoder for determining 1) is provided, and a coefficient of the time-varying coefficient filter is determined using an output value of the decoder. 4. In the timing device of the interpolation device according to claims 1 and 2, the number of stages of the delay element array of the multistage delay circuit is greater than the value obtained by dividing the maximum delay time of the delay element by the clock period. a sixth latch that holds the clock output from each stage of the multi-stage delay circuit using the input clock of the multi-stage delay circuit; and the latch output is decoded to convert the clock period into the number of delay stages. coefficient(
A high-speed interpolation device, characterized in that a fourth decoder is provided for determining L), and the conversion coefficient is input to the first, second, and third decoders.